ninja: Entering directory `out/gn' [0/1] ACTION //clang/test:check-clang(//llvm/utils/gn/build/toolchain:unix) llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using clang: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using lld-link: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/lld-link llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using ld64.lld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/ld64.lld llvm-lit: /usr/local/google/home/thakis/src/llvm-project/llvm/utils/lit/lit/llvm/config.py:572: note: using wasm-ld: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/wasm-ld -- Testing: 27911 tests, 64 workers -- Testing: FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c (1 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp uge <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp uge <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp uge <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmaxa.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmaxa.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f5ae9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556f5ae950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556f5ae9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f338f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f338f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f338f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f338f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f5ae2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556f5ae2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556f5ae12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556f5aac20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556f5aac1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f338f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f338f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f338f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f5aac1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c (2 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c (3 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64dsm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64dsm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ds(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ds(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64im(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.aes64im(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64dsm(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ds(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64im(i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563efe80915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563efe8060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563efe80989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47a701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47a70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47a701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47a7003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563efe79ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563efe79ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563efe783b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563efe4330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563efe432dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f47a7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47a70050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47a70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563efe432cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c -check-prefix=RV64ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c (4 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c (5 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c (6 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b7900815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558b790050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558b7900889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3b1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b78f9de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558b78f9dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558b78f82b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558b78c320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558b78c31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc3b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b78c31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c (7 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpkhi.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpkhi.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpkhi_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpkhi.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpkhi.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005604f5eb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604f5eb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604f5eb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d32249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d32249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d32231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604f5e48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604f5e48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604f5e2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604f5add0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604f5adcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d32232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d322330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604f5adccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c (8 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2afc0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2afc0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2afc0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28ed249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28ed2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28ed249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28ed231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2afba3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2afba3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2afb88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2af8380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2af837dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28ed232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28ed2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28ed2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2af837cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c (9 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557960b1315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557960b100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557960b1389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70ec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70ec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70ec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70ec91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557960aa8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557960aa8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557960a8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055796073d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055796073cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70ec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70ec91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70ec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055796073ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c (10 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055624b9e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055624b9e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055624b9e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c64a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c64aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c64a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c64a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055624b978e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055624b978c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055624b95db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055624b60d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055624b60cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c64a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c64a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c64a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055624b60ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c (11 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c0720b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c072080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c0720b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9663333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f966338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9663333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f966331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c071a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c071a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c07185b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c06e350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c06e34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f966331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f966331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f966331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c06e34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c (12 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c (13 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da7ff6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da7ff610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da7ff6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ac7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ac7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ac7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ac7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da7fef9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da7fef9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da7fedeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da7fb8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da7fb8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ac7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ac7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ac7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da7fb8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c (14 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align # | ... # `---data was truncated (10240/29111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055859837b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585983780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055859837b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2234f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2234f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2234f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2234eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558598310e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558598310c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585982f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558597fa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558597fa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2234eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2234eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2234eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558597fa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/2005-09-24-AsmUserPrefix.c (15 of 27911) ******************** TEST 'Clang :: CodeGen/2005-09-24-AsmUserPrefix.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 | llc | not grep _foo2 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-09-24-AsmUserPrefix.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @bar() #0 { # | entry: # | call void @foo2() # | ret void # | } # | # | declare void @foo2() #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 # | #0 0x00005654dbfe915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005654dbfe60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005654dbfe989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9441d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9441d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9441d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9441d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654dbf7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005654dbf7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005654dbf63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654dbc130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005654dbc12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9441d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9441d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9441d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654dbc12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: llc # executed command: not grep _foo2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c (16 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586021f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005586021f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005586021f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc97401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9740725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc97401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc974003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558602188e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558602188c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055860216db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558601e1d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558601e1cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc974004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9740050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9740050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558601e1ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c (17 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c (18 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c (19 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df08d7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df08d730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df08d7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e42d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e42d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e42d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e42d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df08d0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df08d0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df08cf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df089a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df0899fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e42d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e42d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e42d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df0899fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll (20 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/objc-contract-pass.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/objc-contract-pass.ll # | #0 0x000055bc5f6b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc5f6ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc5f6b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cef231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc5f645e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc5f645c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc5f62ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc5f2da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc5f2d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1cef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc5f2d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c (21 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a35e26615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a35e2630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a35e26689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5655a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5655aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5655a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5655a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a35e1fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a35e1fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a35e1e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a35de900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a35de8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5655a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5655a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5655a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a35de8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c (22 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056467843d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056467843a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056467843d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e90533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e9058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e90533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e9051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646783d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005646783d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005646783b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646780670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564678066dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8e9051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e9051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e9051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564678066cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c (23 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed3886915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed388660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed3886989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd1fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd1faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd1fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd1fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed387fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed387fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed387e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed384930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed38492dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd1fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd1fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd1fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed38492cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c (24 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055984466e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055984466b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055984466e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4e7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4e7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4e7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4e7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559844603e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559844603c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598445e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598442980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559844297dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4e7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4e7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4e7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559844297cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c (25 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569911a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569911a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569911a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d4d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d4d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d4d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d4d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055699113ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055699113cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556991121b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556990dd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556990dd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d4d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d4d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d4d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556990dd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c (26 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6ffff715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6ffff40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6ffff789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f36333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f3638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f36333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f3631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6fff8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6fff8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6fff71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6ffc210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6ffc20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f3631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f3631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f3631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6ffc20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c (27 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i1 # | ... # `---data was truncated (10240/182173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627c7bc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627c7bbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627c7bc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36aea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36aeaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36aea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36aea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627c7b55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005627c7b55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005627c7b3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627c77ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627c77e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f36aea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36aea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36aea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627c77e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c (28 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643859a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643859a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643859a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d1fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d1fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d1fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d1fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056438593be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056438593bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564385920b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643855d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643855cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d1fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d1fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d1fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643855cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c (29 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ad2c8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ad2c890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ad2c8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61f5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61f578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61f5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61f571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ad2c21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ad2c21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ad2c06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ad28b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ad28b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61f571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61f571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61f571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ad28b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c (30 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5ac4c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5ac4c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5ac4c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd22db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd22db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd22db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd22db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5ac459e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5ac459c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5ac43eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5ac0ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5ac0eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd22db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd22db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd22db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5ac0edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c (31 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7410b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a7410b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a7410b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f821401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82140725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f821401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8214003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a74104ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a74104ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a741033b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a740ce30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a740ce2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8214004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82140050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82140050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a740ce2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c (32 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ad69df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560ad69dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560ad69df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9de5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9de5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9de5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9de5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ad6974e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560ad6974c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560ad6959b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560ad66090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560ad6608dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9de5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9de5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9de5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ad6608cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c (33 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, # | ... # `---data was truncated (10240/12298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a174e5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a174e530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a174e5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f50d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f50d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f50d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f50ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a174debe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a174debc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a174dd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a174a800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a174a7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f50ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f50cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f50cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a174a7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-neon-dot-product.c (34 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 8 # | %__s0_827 = alloca <4 x i32>, align 8 # | %__s1_827 = alloca <16 x i8>, align 8 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x i32>, align 8 # | %tmp2 = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0_827, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %1, ptr %__s1_827, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 8 # | %4 = load <16 x i8>, ptr %__s1_827, align 8 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c (35 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055596357315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005559635700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055596357389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2ba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2ba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2ba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2ba51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555963508e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555963508c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005559634edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055596319d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055596319cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd2ba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2ba51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2ba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055596319ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c (36 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define d # | ... # `---data was truncated (10240/25350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055772da3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055772da340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055772da3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb76733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb7678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb76733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb7671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055772d9cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055772d9ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055772d9b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055772d6610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055772d660dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb7671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb7671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb7671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055772d660cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c (37 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb0dfae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb0dfab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb0dfae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd92ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd92ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd92ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd92ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb0df43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb0df43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb0df28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb0dbd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb0dbd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd92ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd92ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd92ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb0dbd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c (38 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmset_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmset.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmset.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfb1d9515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cfb1d920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cfb1d9589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7df601bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7df60725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7df601ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7df6003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfb1d2ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cfb1d2ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cfb1d0fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cfb19bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cfb19bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7df6004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7df60050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7df60050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfb19becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c (39 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601f4da215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005601f4d9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005601f4da289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc36b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc36b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc36b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc36b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601f4d37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005601f4d37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005601f4d1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005601f49cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005601f49cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc36b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc36b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc36b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601f49cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c (40 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644f4bff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644f4bfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644f4bff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f90eb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90eb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f90eb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f90eb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644f4b94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644f4b94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644f4b79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644f48290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644f4828dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f90eb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90eb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90eb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644f4828cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c (41 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f0ecdf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561f0ecdc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561f0ecdf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0412933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f041298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0412933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f041291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f0ec74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561f0ec74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561f0ec59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561f0e9090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561f0e908dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f041291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f041291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f041291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f0e908cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c (42 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e988a4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e988a430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e988a4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a7c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a7c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a7c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a7c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9889dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9889dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9889c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9886700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e98866fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a7c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a7c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a7c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e98866fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c (43 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d11d4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d11d3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d11d4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5922649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5922649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5922631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d11cd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d11cd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d11cbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d1196b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d1196add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5922632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59226330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d1196acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c (44 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560bcbec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560bcbe90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560bcbec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc4e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc4e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc4e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc4e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560bcb81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560bcb81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560bcb66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560bc8160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560bc815dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efc4e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc4e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc4e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560bc815cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c (45 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d337e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d337e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d337e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72b801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72b80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72b801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72b8003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d3377ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d3377ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d33763b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d334130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d33412dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72b8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72b80050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72b80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d33412cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c (46 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575f7e2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575f7e230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575f7e2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f575e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f575e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f575e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f575e431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575f7dbbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575f7dbbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575f7da0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575f7a500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575f7a4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f575e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f575e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f575e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575f7a4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c (47 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055823743f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055823743c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055823743f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd181b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd181b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd181b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd181b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582373d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582373d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582373b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582370690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558237068dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd181b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd181b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd181b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558237068cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c (48 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e91229d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e91229a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e91229d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eba51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e912232e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e912232c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e912217b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e911ec70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e911ec6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9eba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eba51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e911ec6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c (49 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea266b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dea26680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dea266b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efded249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efded2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efded249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efded231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea2600e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dea2600c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dea25e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dea22950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dea2294dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efded232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efded2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efded2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea2294cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c (50 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_u16mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b2c14f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b2c14c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b2c14f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0176649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01766a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0176649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0176631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b2c0e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b2c0e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b2c0c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b2bd790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b2bd78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0176632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01766330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01766330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b2bd78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c (51 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c (52 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv4f32( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fdot.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32( %0, %1, %2, i32 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8dot2,+fp8dot4,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560cad37115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560cad36e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560cad37189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bb5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bb56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bb5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bb5631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cad306e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560cad306c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560cad2ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560cacf9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560cacf9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7bb5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bb56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bb56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cacf9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c (53 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c (54 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056259a66015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056259a65d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056259a66089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f693b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f693b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f693b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f693b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056259a5f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056259a5f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056259a5dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056259a28a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056259a289dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f693b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f693b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f693b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056259a289cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c (55 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b624f0115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b624efe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b624f0189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65ecf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65ecf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65ecf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65ecf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b624e96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b624e96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b624e7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b624b2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b624b2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f65ecf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65ecf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65ecf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b624b2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c (56 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594b830215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594b82ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594b830289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86e5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86e578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86e5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86e571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594b8297e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594b8297c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594b827cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594b7f2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594b7f2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f86e571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86e571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86e571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594b7f2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c (57 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649618c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005649618be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005649618c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8baed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8baed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8baed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8baed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564961856e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564961856c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056496183bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649614eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649614eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8baed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8baed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8baed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649614eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c (58 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c (59 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056459bc8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056459bc8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056459bc8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0e721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0e72725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0e721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0e7203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056459bc22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056459bc22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056459bc07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056459b8b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056459b8b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0e7204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0e72050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0e72050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056459b8b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c (60 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b03597c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b0359790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b03597c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd492933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd49298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd492933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd49291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b035911e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b035911c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b0358f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b0355a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b0355a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd49291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd49291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd49291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0355a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c (61 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560826fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560826f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560826fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8d0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8d0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8d0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8d0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556082690e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556082690c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556082675b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560823250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556082324dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8d0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8d0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8d0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556082324cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c (62 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570a008415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570a00810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570a008489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5418333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f541838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5418333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f541831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570a0019e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570a0019c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055709fffeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055709fcae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055709fcaddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f541831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f541831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f541831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055709fcadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c (63 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568c5b1c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568c5b190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005568c5b1c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568c5ab1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005568c5ab1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005568c5a96b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005568c57460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005568c5745dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f5af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568c5745cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c (64 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i64 immar # | ... # `---data was truncated (10240/14780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5a405515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5a40520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5a405589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6939533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f693958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6939533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f693951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5a3feae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5a3feac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5a3fcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5a3c7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5a3c7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f693951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f693951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f693951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5a3c7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c (65 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612495e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612495e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005612495e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc667d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc667d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc667d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc667d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056124957de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056124957dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561249562b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005612492120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561249211dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc667d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc667d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc667d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561249211cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c (66 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b239bd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b239bcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b239bd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe15cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe15cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe15cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe15cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b239b67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b239b67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b239b4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2397fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2397fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe15cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe15cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe15cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2397fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c (67 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv64i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i8.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr # | ... # `---data was truncated (10240/26240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec64e4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec64e3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec64e4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd446133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd44618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd446133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd44611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec64dd6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec64dd6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec64dbbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec64a6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec64a6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd44611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd44611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd44611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec64a6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c (68 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv8i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv8i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfh.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfh_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c (69 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, ali # | ... # `---data was truncated (10240/58334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b0425b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561b042580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561b0425b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dcf505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dcf55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dcf505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dcf4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b041f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561b041f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561b041d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561b03e850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561b03e84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1dcf4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dcf4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dcf4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b03e84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c (70 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/410391) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f09eb2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f09eb280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f09eb2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc833f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc833f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc833f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc833f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f09eac0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f09eac0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f09eaa5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f09e7550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f09e754dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc833f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc833f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc833f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f09e754cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c (71 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsli # | ... # `---data was truncated (10240/14908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65de8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f65de800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f65de8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65de18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f65de18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f65ddfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f65daad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f65daacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1c0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65daaccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c (72 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564eb60015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564eb5fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005564eb60089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc53f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc53f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc53f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc53f231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564eb595e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005564eb595c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005564eb57ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005564eb22a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005564eb229dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc53f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc53f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc53f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564eb229cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c (73 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/builtins-riscv.c (74 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-riscv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 10, ptr %res, align 4 # | store volatile i32 11, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055672046615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567204630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055672046689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaf7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaf778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaf7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaf771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567203fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567203fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567203e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567200900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055672008fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faaf771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaf771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaf771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055672008fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-riscv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c (75 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c (76 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx. # | ... # `---data was truncated (10240/28427) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056451247615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645124730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056451247689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6df049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6df0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6df049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6df031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056451240be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056451240bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645123f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645120a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056451209fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa6df032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6df0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6df0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056451209fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c (77 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bc17c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563bc17bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563bc17c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0e451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bc1755e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563bc1755c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563bc173ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563bc13ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563bc13e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0e451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bc13e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c (78 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfs # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b45b9c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b45b9be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b45b9c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffaf5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffaf518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffaf5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffaf511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b45b956e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b45b956c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b45b93bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b45b5eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b45b5eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffaf511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffaf511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffaf511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b45b5eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c (79 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusdot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055725328715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005572532840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055725328789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f5ca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f5ca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f5ca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f5ca03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055725321ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055725321cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557253201b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557252eb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557252eb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f5ca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f5ca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f5ca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557252eb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c (80 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.bic.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.bic.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.bic.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbic_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560807bfe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560807bfb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560807bfe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06bd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06bd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06bd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06bd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560807b93e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560807b93c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560807b78b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005608078280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560807827dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f06bd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06bd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06bd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560807827cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c (81 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8ebc1c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8ebc190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8ebc1c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f013c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f013c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f013c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f013c0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8ebbb1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8ebbb1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8ebb96b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8eb8460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8eb845dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f013c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f013c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f013c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8eb845cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c (82 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056021504715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602150440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056021504789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54dc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54dc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54dc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54dc631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560214fdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560214fdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560214fc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560214c710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560214c70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f54dc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54dc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54dc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560214c70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c (83 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ecbfd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ecbfcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ecbfd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a00933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a00933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ecbf67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ecbf67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ecbf4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ecbbfc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ecbbfbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a0091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ecbbfbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c (84 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/68073) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055887d7e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055887d7dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055887d7e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1009933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f100998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1009933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f100991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055887d775e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055887d775c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055887d75ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055887d40a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055887d409dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f100991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f100991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f100991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055887d409cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c (85 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e47fd4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e47fd490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e47fd4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bc6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bc6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bc6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bc6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e47fce1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e47fce1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e47fcc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e47f9760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e47f975dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5bc6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bc6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bc6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e47f975cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c (86 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmpuo.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f16( %pg, %op1, half noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv8f16( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpuo_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fcmpuo.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055622839d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055622839a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055622839d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff12e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff12e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff12e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff12e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556228332e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556228332c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556228317b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556227fc70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556227fc6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff12e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff12e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff12e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556227fc6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c (87 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smax.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smax.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umax.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umax.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umax.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c (88 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clo_32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f89f9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563f89f9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563f89f9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcd281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcd28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcd281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcd2803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f89f32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563f89f32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563f89f17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563f89bc70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563f89bc6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdcd2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcd28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcd28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f89bc6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c -check-prefix=RV32XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c (89 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +lut -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcreate_mf8(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <8 x i8>, ptr %__promote, align 8 # | store <8 x i8> %1, ptr %__ret, align 8 # | %2 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %2, ptr %tmp, align 8 # | %3 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vdup_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <8 x i8>, align 8 # | %.compoundliteral.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <8 x i32> # | %vecinit.i = shufflevector <8 x i8> %vext.i, <8 x i8> poison, <8 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <8 x i32> # | %vecinit2.i = shufflevector <8 x i8> %vecinit.i, <8 x i8> %vext1.i, <8 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <8 x i32> # | %vecinit4.i = shufflevector <8 x i8> %vecinit2.i, <8 x i8> %vext3.i, <8 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <8 x i32> # | %vecinit6.i = shufflevector <8 x i8> %vecinit4.i, <8 x i8> %vext5.i, <8 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <8 x i32> # | %vecinit8.i = shufflevector <8 x i8> %vecinit6.i, <8 x i8> %vext7.i, <8 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <8 x i32> # | %vecinit10.i = shufflevector <8 x i8> %vecinit8.i, <8 x i8> %vext9.i, <8 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <8 x i32> # | %vecinit12.i = shufflevector <8 x i8> %vecinit10.i, <8 x i8> %vext11.i, <8 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <8 x i32> # | %vecinit14.i = shufflevector <8 x i8> %vecinit12.i, <8 x i8> %vext13.i, <8 x i32> # | store <8 x i8> %vecinit14.i, ptr %.compoundliteral.i, align 8 # | %9 = load <8 x i8>, ptr %.compoundliteral.i, align 8 # | store <8 x i8> %9, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vdupq_n_mf8(<1 x i8> %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i8>, align 1 # | %__ret.i = alloca <16 x i8>, align 16 # | %.compoundliteral.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <1 x i8>, align 1 # | store <1 x i8> %a, ptr %a.addr, align 1 # | %0 = load <1 x i8>, ptr %a.addr, align 1 # | store <1 x i8> %0, ptr %__p0.addr.i, align 1 # | %1 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext.i = shufflevector <1 x i8> %1, <1 x i8> poison, <16 x i32> # | %vecinit.i = shufflevector <16 x i8> %vext.i, <16 x i8> poison, <16 x i32> # | %2 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext1.i = shufflevector <1 x i8> %2, <1 x i8> poison, <16 x i32> # | %vecinit2.i = shufflevector <16 x i8> %vecinit.i, <16 x i8> %vext1.i, <16 x i32> # | %3 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext3.i = shufflevector <1 x i8> %3, <1 x i8> poison, <16 x i32> # | %vecinit4.i = shufflevector <16 x i8> %vecinit2.i, <16 x i8> %vext3.i, <16 x i32> # | %4 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext5.i = shufflevector <1 x i8> %4, <1 x i8> poison, <16 x i32> # | %vecinit6.i = shufflevector <16 x i8> %vecinit4.i, <16 x i8> %vext5.i, <16 x i32> # | %5 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext7.i = shufflevector <1 x i8> %5, <1 x i8> poison, <16 x i32> # | %vecinit8.i = shufflevector <16 x i8> %vecinit6.i, <16 x i8> %vext7.i, <16 x i32> # | %6 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext9.i = shufflevector <1 x i8> %6, <1 x i8> poison, <16 x i32> # | %vecinit10.i = shufflevector <16 x i8> %vecinit8.i, <16 x i8> %vext9.i, <16 x i32> # | %7 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext11.i = shufflevector <1 x i8> %7, <1 x i8> poison, <16 x i32> # | %vecinit12.i = shufflevector <16 x i8> %vecinit10.i, <16 x i8> %vext11.i, <16 x i32> # | %8 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext13.i = shufflevector <1 x i8> %8, <1 x i8> poison, <16 x i32> # | %vecinit14.i = shufflevector <16 x i8> %vecinit12.i, <16 x i8> %vext13.i, <16 x i32> # | %9 = load <1 x i8>, ptr %__p0.addr.i, align 1 # | %vext15.i = shufflevector <1 x i8> %9, <1 x i8> poison, <16 x i32> # | %vecinit16.i = shufflevector <16 x i8> %vecinit14.i, <16 x i8> %vext15.i, <16 x i32> ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c (90 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648b98c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648b98c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648b98c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bbf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bbf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bbf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bbf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648b985de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648b985dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648b9842b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648b94f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648b94f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4bbf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bbf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bbf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648b94f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c (91 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i64, i64, # | ... # `---data was truncated (10240/120460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645fae0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645fae000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645fae0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfc5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfc5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfc5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfc5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645fad98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645fad98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645fad7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645faa2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645faa2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdfc5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfc5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfc5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645faa2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c (92 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_s64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u8( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u16( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u32( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_u64( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = load , ptr %x.addr, align 16 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c (93 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056519a9d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056519a9d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056519a9d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9126449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91264a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9126449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9126431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056519a96ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056519a96cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056519a951b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056519a6010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056519a600dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9126432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91264330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91264330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056519a600cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c (94 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a22ec0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a22ec070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a22ec0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff00ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff00ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff00ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff00ec03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22eb9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a22eb9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a22eb84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a22e8340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a22e833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff00ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff00ec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff00ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a22e833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c (95 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s8_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s32_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_s64_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv16i8( %0, %1, i32 255) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8i16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv4i32( %0, %1, i32 63) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv2i64( %0, %1, i32 31) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ext.nxv8f16( %0, %1, i32 127) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ext.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svext_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr # | ... # `---data was truncated (10240/12880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559f92eff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f92efc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f92eff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fcbd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fcbd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fcbd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fcbced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f92e94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f92e94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f92e79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f92b290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f92b28dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0fcbceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fcbcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fcbcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f92b28cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-crc32.c (96 of 27911) ******************** TEST 'Clang :: CodeGen/arm-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.arm.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.arm.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32w(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32w(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = trunc i64 %1 to i32 # | %3 = lshr i64 %1, 32 # | %4 = trunc i64 %3 to i32 # | %5 = call i32 @llvm.arm.crc32cw(i32 %0, i32 %2) # | %6 = call i32 @llvm.arm.crc32cw(i32 %5, i32 %4) # | ret i32 %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8-a,+crc,-thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edcd12315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055edcd1200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055edcd12389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc051849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc051849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc051831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edcd0b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055edcd0b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055edcd09db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055edccd4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055edccd4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc051832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0518330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edccd4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c (97 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f733bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560f733ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560f733bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd85b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd85b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd85b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd85b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f73352e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560f73352c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560f73337b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560f72fe70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560f72fe6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd85b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd85b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd85b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f72fe6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/getset.c (98 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 3 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_vget_lane_mf8(<8 x i8> %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <1 x i8>, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <1 x i8>, align 1 # | %tmp = alloca <1 x i8>, align 1 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 7 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load <1 x i8>, ptr %ref.tmp, align 1 # | store <1 x i8> %2, ptr %__ret, align 1 # | %3 = load <1 x i8>, ptr %__ret, align 1 # | store <1 x i8> %3, ptr %tmp, align 1 # | %4 = load <1 x i8>, ptr %tmp, align 1 # | ret <1 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_847 = alloca half, align 2 # | %__s0_847 = alloca <4 x half>, align 8 # | %ref.tmp = alloca i16, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp1 = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %tmp2 = alloca half, align 2 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_847, align 8 # | %1 = load <4 x i16>, ptr %__s0_847, align 8 # | store <4 x i16> %1, ptr %__s0, align 8 # | %2 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %2, i32 1 # | store i16 %vget_lane, ptr %ref.tmp1, align 2 # | %3 = load i16, ptr %ref.tmp1, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | store i16 %5, ptr %ref.tmp, align 2 # | %6 = load half, ptr %ref.tmp, align 2 # | store half %6, ptr %__ret_847, align 2 # | %7 = load half, ptr %__ret_847, align 2 # | store half %7, ptr %tmp2, align 2 # | %8 = load half, ptr %tmp2, align 2 # | %conv = fpext half %8 to float # | ret float %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vget_lane_f32(<2 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %1, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vget_lane_f64(<1 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %1, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align # | ... # `---data was truncated (10240/76998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055851ec2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055851ec290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055851ec2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff818b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff818b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff818b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff818b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055851ebc1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055851ebc1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055851eba6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055851e8560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055851e855dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff818b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff818b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff818b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055851e855cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c (99 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpgt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005577e3d1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005577e3d140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005577e3d1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7358649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73586a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7358649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7358631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577e3cace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005577e3cacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005577e3c91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005577e39410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005577e3940dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7358632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73586330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73586330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577e3940cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c (100 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cls.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cls.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.cls.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cls.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cls.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcls_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/11769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557c3391c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c339190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c3391c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa57f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa57f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa57f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa57f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c338b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c338b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c33896b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c335460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c33545dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa57f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa57f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa57f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c33545cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c (101 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svqdmulh_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s8_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svqdmulh_single_s16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c (102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c6745a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c674570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c6745a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff736449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7364a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff736449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff736431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c673efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c673efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c673d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c670840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c67083dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff736432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7364330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7364330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c67083cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c (103 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c (104 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpeq.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpeq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpeq_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpeq.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005653118a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653118a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653118a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f173fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f173fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f173fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f173fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056531183ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056531183ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565311823b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653114d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005653114d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f173fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f173fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f173fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653114d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c (105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5f8be015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5f8bdd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5f8be089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa918649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9186a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa918649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa918631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5f8b75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5f8b75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5f8b5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5f880a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5f8809dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa918632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9186330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9186330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5f8809cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c (106 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frecpx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frecpx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a9855da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9855d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9855da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa84c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa84c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa84c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa84c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a98556fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a98556fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a985554b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9852040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a985203dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa84c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa84c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa84c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a985203cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c (107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c503c9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c503c9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c503c9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff182533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff18258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff182533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff18251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c503c32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c503c32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c503c17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5038c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5038c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff18251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff18251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff18251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5038c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c (108 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pnext.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv8i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv8i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv4i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv4i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpnext_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.pnext.nxv2i1( %2, %3) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pnext.nxv2i1(, ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b54a02715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b54a0240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b54a02789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71bc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71bc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71bc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71bc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b549fbce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b549fbcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b549fa1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b549c510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b549c50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f71bc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71bc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71bc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b549c50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c (109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca # | ... # `---data was truncated (10240/153805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e212fb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e212fad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e212fb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9709505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f970955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9709505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97094ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e212f45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e212f45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e212f2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e212bda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e212bd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97094eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97094ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97094ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e212bd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c (110 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_bf16_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055774ebba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055774ebb70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055774ebba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23eda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23edaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23eda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23eda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055774eb4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055774eb4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055774eb34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055774e7e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055774e7e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23eda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23eda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23eda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055774e7e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c (111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c (112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4f5e6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c4f5e5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c4f5e6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eae505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eae55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eae505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eae4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4f5df6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c4f5df6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c4f5ddbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4f5a8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4f5a8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9eae4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eae4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eae4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4f5a8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c (113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555bea6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005555bea6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005555bea6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f311af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f311af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f311af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f311af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555bea04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005555bea04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005555be9e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005555be6990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005555be698dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f311af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f311af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f311af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555be698cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c (114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c (115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056055a56b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056055a5680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056055a56b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0978d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0978d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0978d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0978ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000056055a500e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056055a500c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056055a4e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056055a1950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056055a194dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0978ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0978cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0978cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056055a194cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCXX/virtual-base-ctor.cpp (116 of 27911) ******************** TEST 'Clang :: CodeGenCXX/virtual-base-ctor.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp -emit-llvm -triple x86_64-unknown-linux-gnu -o - -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type { ptr, ptr, %struct.A } # | %struct.A = type { i32 } # | # | $_ZTV1B = comdat any # | # | $_ZTI1B = comdat any # | # | $_ZTS1B = comdat any # | # | $_ZTI1A = comdat any # | # | $_ZTS1A = comdat any # | # | @y = local_unnamed_addr global i8 2, align 1 # | @x = local_unnamed_addr global %struct.B { ptr getelementptr inbounds inrange(-24, 0) (i8, ptr @_ZTV1B, i64 24), ptr null, %struct.A zeroinitializer }, align 8 # | @_ZTV1B = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr inttoptr (i64 16 to ptr), ptr null, ptr @_ZTI1B] }, comdat, align 8 # | @_ZTI1B = linkonce_odr constant { ptr, ptr, i32, i32, ptr, i64 } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 16), ptr @_ZTS1B, i32 0, i32 1, ptr @_ZTI1A, i64 -6141 }, comdat, align 8 # | @_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global [0 x ptr] # | @_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00", comdat, align 1 # | @_ZTI1A = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (i8, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 16), ptr @_ZTS1A }, comdat, align 8 # | @_ZTVN10__cxxabiv117__class_type_infoE = external global [0 x ptr] # | @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00", comdat, align 1 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000056492d1b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056492d1b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056492d1b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05ae533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05ae58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05ae533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05ae51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056492d14be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056492d14bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056492d130b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056492cde00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056492cddfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f05ae51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05ae51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05ae51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056492cddfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/virtual-base-ctor.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm_neon_intrinsics.c (117 of 27911) ******************** TEST 'Clang :: CodeGen/arm_neon_intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7s-apple-darwin -target-abi apcs-gnu -target-cpu swift -target-feature +fullfp16 -ffreestanding -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7s-apple-darwin" # | # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, ptr %__p0.addr.i1, align 8 # | store <8 x i8> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vabd_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %8, ptr %__ret.i3, align 8 # | %9 = load <8 x i8>, ptr %__ret.i3, align 8 # | %add.i = add <8 x i8> %3, %9 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %10 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @test_vaba_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x i16>, align 8 # | %__p1.addr.i2 = alloca <4 x i16>, align 8 # | %__ret.i3 = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %5 = load <4 x i16>, ptr %__p2.addr.i, align 8 # | store <4 x i16> %4, ptr %__p0.addr.i1, align 8 # | store <4 x i16> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <4 x i16> # | %vabd_v1.i = bitcast <8 x i8> %7 to <4 x i16> # | %vabd_v2.i = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %vabd_v.i, <4 x i16> %vabd_v1.i) # | %vabd_v3.i = bitcast <4 x i16> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %8, ptr %__ret.i3, align 8 # | %9 = load <4 x i16>, ptr %__ret.i3, align 8 # | %add.i = add <4 x i16> %3, %9 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %10 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @test_vaba_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <2 x i32>, align 8 # | %__p1.addr.i2 = alloca <2 x i32>, align 8 # | %__ret.i3 = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x i32>, ptr %__p2.addr.i, align 8 # | store <2 x i32> %4, ptr %__p0.addr.i1, align 8 # | store <2 x i32> %5, ptr %__p1.addr.i2, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %vabd_v.i = bitcast <8 x i8> %6 to <2 x i32> # | %vabd_v1.i = bitcast <8 x i8> %7 to <2 x i32> # | %vabd_v2.i = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %vabd_v.i, <2 x i32> %vabd_v1.i) # | %vabd_v3.i = bitcast <2 x i32> %vabd_v2.i to <8 x i8> # | store <8 x i8> %vabd_v3.i, ptr %ref.tmp.i, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %8, ptr %__ret.i3, align 8 # | %9 = load <2 x i32>, ptr %__ret.i3, align 8 # | %add.i = add <2 x i32> %3, %9 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %10 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x i8>, align 8 # | %__p1.addr.i2 = alloca <8 x i8>, align 8 # | %__ret.i3 = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | store <8 x i8> %4, pt # | ... # `---data was truncated (10240/2159854) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559e203e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559e203e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559e203e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa564733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa56478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa564733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa56471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e2037ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559e2037cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559e20361b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559e200110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559e20010dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa56471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa56471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa56471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e20010cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_neon_intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c (118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | s # | ... # `---data was truncated (10240/12680) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb977e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb977e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb977e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6e7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6e70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6e7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6e7031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb9777ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb9777cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb97761b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb974110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb97410dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd6e7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6e70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6e70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb97410cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c (119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c (120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e5517515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e551720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e5517589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c71b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c71b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c71b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c71b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e5510ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e5510ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e550efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e54d9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e54d9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c71b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c71b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c71b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e54d9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c (121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c (122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559548b5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559548b5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559548b5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e2af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e2af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e2af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e2aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559548af3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559548af3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559548ad8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595487880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559548787dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e2aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e2aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e2aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559548787cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c (123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055795c88415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055795c8810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055795c88489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0b0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0b06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0b0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0b0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055795c819e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055795c819c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055795c7feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055795c4ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055795c4addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0b0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0b06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0b06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055795c4adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c (124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a35c81115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a35c80e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a35c81189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8288e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8288ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8288e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8288e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a35c7a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a35c7a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a35c78bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a35c43b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a35c43add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8288e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8288e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8288e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a35c43acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c (125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055797689815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005579768950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055797689889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c2d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c2d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c2d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c2d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055797682de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055797682dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557976812b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579764c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005579764c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c2d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c2d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c2d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579764c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c (126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055692bb7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055692bb6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055692bb7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb799649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7996a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb799649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb799631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055692bb05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055692bb05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055692baeab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055692b79a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055692b799dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb799632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7996330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7996330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055692b799cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c (127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbc6e3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cbc6e370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cbc6e3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5734449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5734449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5734431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbc6dcfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cbc6dcfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cbc6db4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cbc6a640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cbc6a63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5734432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57344330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbc6a63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c (128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d7cccd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d7ccca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d7cccd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe79e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe79e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe79e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe79e431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d7cc62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d7cc62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d7cc47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d7c8f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d7c8f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe79e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe79e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe79e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d7c8f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c (129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563abf16115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563abf15e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563abf16189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe581733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe58178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe581733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe58171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563abf0f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563abf0f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563abf0dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563abed8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563abed8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe58171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe58171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe58171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563abed8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c (130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621734f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621734f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005621734f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff16ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff16eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff16ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff16ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056217348ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056217348ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056217346fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056217311f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056217311edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff16ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff16ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff16ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056217311ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c (131 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uunpklo.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uunpklo.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svunpklo_b( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.punpklo.nxv16i1( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.punpklo.nxv16i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563fc7f0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563fc7f000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563fc7f0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a4cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a4cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a4cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a4cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fc7e98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563fc7e98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563fc7e7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563fc7b2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563fc7b2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a4cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a4cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a4cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fc7b2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c (132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574bd3c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574bd3bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574bd3c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8a1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8a18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8a1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8a1831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574bd357e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005574bd357c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005574bd33cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574bcfec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005574bcfebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe8a1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8a18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8a18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574bcfebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c (133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615f54c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615f54bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005615f54c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3bd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3bd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3bd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3bd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615f5457e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615f5457c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615f543cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615f50ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615f50ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe3bd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3bd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3bd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615f50ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c (134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr % # | ... # `---data was truncated (10240/29809) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae814ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae814ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae814ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0c9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0c94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0c9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0c9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae81443e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae81443c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae81428b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae810d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae810d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0c9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0c94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0c94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae810d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c (135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c (136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) % # | ... # `---data was truncated (10240/27994) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a337d8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a337d810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a337d8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefa9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefa9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefa9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefa9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a337d19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a337d19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a337cfeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3379ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3379addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fefa9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefa9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefa9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3379adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c (137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/29136) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f12ac6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f12ac640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f12ac6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe76b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe76b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe76b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe76b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f12abfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f12abfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f12abe1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f12a8910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f12a890dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe76b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe76b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe76b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f12a890cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c (138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv64i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv64i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv32i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv32i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv16i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv16i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv8i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv8i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b16(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv4i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv4i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b32(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv2i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv2i1.i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmclr_m_b64(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vmclr.nxv1i1.i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmclr.nxv1i1.i64(i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d9377c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d937790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d9377c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f516ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f516cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f516ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f516ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d93711e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d93711c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d936f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d933a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d933a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f516ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f516ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f516ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d933a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c (139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c (140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556213cee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556213ceb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556213cee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56bb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56bb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56bb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56bb031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556213c83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556213c83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556213c68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005562139180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556213917dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56bb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56bb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56bb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556213917cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c (141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/70971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055566b81a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055566b8170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055566b81a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f406f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f406f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f406f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f406f431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055566b7afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055566b7afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055566b794b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055566b4440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055566b443dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f406f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f406f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f406f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055566b443cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c (142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c (143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640fc94215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640fc93f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640fc94289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dd861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dd86725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dd861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dd8603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640fc8d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005640fc8d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005640fc8bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640fc56c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640fc56bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9dd8604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dd86050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dd86050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640fc56bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/arm-neon-directed-rounding.c (144 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnda_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnda_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnda_v1.i = call <2 x float> @llvm.round.v2f32(<2 x float> %vrnda_v.i) # | %vrnda_v2.i = bitcast <2 x float> %vrnda_v1.i to <8 x i8> # | store <8 x i8> %vrnda_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndaq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndaq_v1.i = call <4 x float> @llvm.round.v4f32(<4 x float> %vrndaq_v.i) # | %vrndaq_v2.i = bitcast <4 x float> %vrndaq_v1.i to <16 x i8> # | store <16 x i8> %vrndaq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm_v1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm_v.i) # | %vrndm_v2.i = bitcast <2 x float> %vrndm_v1.i to <8 x i8> # | store <8 x i8> %vrndm_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndmq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndmq_v1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndmq_v.i) # | %vrndmq_v2.i = bitcast <4 x float> %vrndmq_v1.i to <16 x i8> # | store <16 x i8> %vrndmq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn_v1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn_v.i) # | %vrndn_v2.i = bitcast <2 x float> %vrndn_v1.i to <8 x i8> # | store <8 x i8> %vrndn_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndnq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndnq_v1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndnq_v.i) # | %vrndnq_v2.i = bitcast <4 x float> %vrndnq_v1.i to <16 x i8> # | store <16 x i8> %vrndnq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndp_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndp_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndp_v1.i = call <2 x float> @llvm.ceil.v2f32(<2 x float> %vrndp_v.i) # | %vrndp_v2.i = bitcast <2 x float> %vrndp_v1.i to <8 x i8> # | store <8 x i8> %vrndp_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndpq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndpq_v1.i = call <4 x float> @llvm.ceil.v4f32(<4 x float> %vrndpq_v.i) # | %vrndpq_v2.i = bitcast <4 x float> %vrndpq_v1.i to <16 x i8> # | store <16 x i8> %vrndpq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndx_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndx_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndx_v1.i = call <2 x float> @llvm.rint.v2f32(<2 x float> %vrndx_v.i) # | %vrndx_v2.i = bitcast <2 x float> %vrndx_v1.i to <8 x i8> # | store <8 x i8> %vrndx_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndxq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndxq_v1.i = call <4 x float> @llvm.rint.v4f32(<4 x float> %vrndxq_v.i) # | %vrndxq_v2.i = bitcast <4 x float> %vrndxq_v1.i to <16 x i8> # | store <16 x i8> %vrndxq_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd_v1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrnd_v.i) # | %vrnd_v2.i = bitcast <2 x float> %vrnd_v1.i to <8 x i8> # | store <8 x i8> %vrnd_v2.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x # | ... # `---data was truncated (10240/16447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000563191f8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563191f8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563191f8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b8ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b8ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b8ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b8aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563191f22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563191f22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563191f07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563191bb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563191bb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b8aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b8aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b8aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563191bb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c (145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055563b18c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055563b1890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055563b18c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6f6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6f60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6f6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6f6031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055563b121e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055563b121c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055563b106b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055563adb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055563adb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd6f6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6f60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6f60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055563adb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c (146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c (147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c (148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2ccc7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2ccc7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2ccc7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf5fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf5fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf5fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf5fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2ccc14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a2ccc14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2ccbf9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2cc8a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2cc8a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf5fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf5fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf5fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2cc8a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c (149 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555aacbeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555aacbe80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555aacbeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21b5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21b5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21b5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21b5aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555aacb80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555aacb80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555aacb65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555aac8150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555aac814dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21b5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21b5aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21b5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555aac814cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c (150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580a2b6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580a2b680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580a2b6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1d5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1d58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1d5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1d5831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580a2b00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580a2b00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580a2ae5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580a27950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580a2794dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1d5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1d58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1d58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580a2794cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c (151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 # | ... # `---data was truncated (10240/27063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604a006315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604a00600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604a006389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8025249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80252a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8025249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8025231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056049fff8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056049fff8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056049ffddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056049fc8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056049fc8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8025232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80252330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80252330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056049fc8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c (152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560745caa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560745ca70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560745caa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91ef41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91ef4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91ef41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91ef403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560745c3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560745c3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560745c24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607458d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607458d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f91ef404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91ef4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91ef4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607458d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c (153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bae74715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563bae7440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563bae74789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f448be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f448bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f448be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f448be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bae6dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563bae6dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563bae6c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563bae3710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563bae370dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f448be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f448be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f448be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bae370cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c (154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/14044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b88808215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b88807f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b88808289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7eec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7eeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7eec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7eec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b888017e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b888017c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b887ffcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b887cac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b887cabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd7eec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7eec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7eec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b887cabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c (155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %b # | ... # `---data was truncated (10240/38307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4485a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4485a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4485a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8024705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f802475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8024705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80246ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f44853de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f44853dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f448522b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4481d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4481d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80246eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80246ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80246ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4481d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c (156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562afe11215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562afe10f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562afe11289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2110b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2110b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2110b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2110b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562afe0a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562afe0a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562afe08cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562afdd3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562afdd3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2110b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2110b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2110b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562afdd3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c (157 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmulx.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmulx.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulx_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c (158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613c1a6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613c1a660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005613c1a6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22fc831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613c19fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005613c19fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005613c19e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005613c16930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005613c1692dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f22fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22fc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613c1692cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c (159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.a # | ... # `---data was truncated (10240/33190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6e9ec515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6e9ec20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6e9ec589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5b1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5b1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5b1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5b1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6e9e5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f6e9e5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6e9e3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6e9aef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6e9aeedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5b1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5b1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5b1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6e9aeecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c (160 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-f8f32 -target-feature +sme-f8f16 -target-feature +sme-mop4 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za16_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za16_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1.nxv16i8(i32 immarg, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za16_mf8_mf8_fpm( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %10) # | call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2.nxv16i8(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_mf8_mf8_fpm( %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %2) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1.nxv16i8(i32 immarg, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_mf8_mf8_fpm( %zn, %zm.coerce0, %zm.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2.nxv16i8(i32 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c (161 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-tmop -target-feature +sme-f16f16 -target-feature +sme-f8f32 -target-feature +sme-b16b16 -target-feature +sme-f8f16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.utmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sutmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.ustmopa.za32.nxv16i8(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_s16_s16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = load , ptr %zk.addr, align 16 # | call void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 1, %3, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.stmopa.za32.nxv8i16(i32 immarg, , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svtmopa_lane_za32_u16_u16( %zn.coerce0, %zn.coerce1, %zm, %zk) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %zk.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store %zk, ptr %zk.addr, align 16 # | %2 = load { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c (162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624687b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624687ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624687b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62be333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62be38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62be333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62be31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562468746e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562468746c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056246872bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624683db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624683dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62be31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62be31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62be31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624683dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c (163 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecd.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecd.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecd.nxv2i64( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecd.nxv2i64( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005644bc0c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644bc0c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644bc0c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff1f5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff1f598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff1f5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff1f591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644bc05ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644bc05ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644bc043b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644bbcf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644bbcf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff1f591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff1f591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff1f591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644bbcf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c (164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d10c33d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d10c33a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d10c33d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3278c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3278ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3278c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3278c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d10c2d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d10c2d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d10c2b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d10bf670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d10bf66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3278c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3278c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3278c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d10bf66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c (165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x # | ... # `---data was truncated (10240/164783) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1cec4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e1cec490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e1cec4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e29333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e2938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e29333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e2931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1cebe1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e1cebe1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1cebc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1ce8760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1ce875dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e2931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e2931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e2931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1ce875cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c (166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056249876c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624987690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056249876c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62bd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62bd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62bd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62bd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562498701e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562498701c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624986e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624983960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562498395dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62bd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62bd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62bd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562498395cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve/recps.c (167 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recps.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecps_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frecps.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecps.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000559cb58b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559cb58ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559cb58b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62ef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62ef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62ef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62ef031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cb5846e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559cb5846c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559cb582bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559cb54db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559cb54dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62ef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62ef0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62ef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cb54dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recps.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c (168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b4cd8215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b4cd7f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b4cd8289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f814cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f814cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f814cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f814cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b4cd17e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b4cd17c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b4ccfcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b4c9ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b4c9abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f814cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f814cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f814cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b4c9abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c (169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/100960) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056229f9bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056229f9ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056229f9bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe961049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9610a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe961049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe961031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056229f952e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056229f952c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056229f937b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056229f5e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056229f5e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe961032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9610330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9610330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056229f5e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c (170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , flo # | ... # `---data was truncated (10240/34773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b48492d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b48492a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b48492d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f30333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f3038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f30333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f3031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4848c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4848c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4848a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4845570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b484556dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f3031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f3031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f3031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b484556cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c (171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7f2e7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7f2e6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7f2e7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f806981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80698725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f806981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8069803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f2e05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e7f2e05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e7f2deab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e7f2a9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e7f2a99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8069804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80698050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80698050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f2a99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c (172 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_f16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c (173 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clz.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.clz.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.clz.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.clz.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.clz.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclz_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c (174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c75f9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c75f9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c75f9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14aa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14aa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14aa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14aa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c75f34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c75f34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c75f19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c75bc90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c75bc8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14aa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14aa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14aa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c75bc8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/X86/avx-shuffle-builtins.c (175 of 27911) ******************** TEST 'Clang :: CodeGen/X86/avx-shuffle-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @x(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %shufp = shufflevector <8 x float> %0, <8 x float> %1, <8 x i32> # | ret <8 x float> %shufp # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_mm_permute_pd(<2 x double> noundef %a) #1 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %permil = shufflevector <2 x double> %0, <2 x double> poison, <2 x i32> # | ret <2 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute_pd(<4 x double> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %permil = shufflevector <4 x double> %0, <4 x double> poison, <4 x i32> # | ret <4 x double> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_permute_ps2(<4 x float> noundef %a) #1 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %permil = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute_ps(<8 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %permil = shufflevector <8 x float> %0, <8 x float> poison, <8 x i32> # | ret <8 x float> %permil # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_permute2f128_pd(<4 x double> noundef %a, <4 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <4 x double>, align 32 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <4 x double> %b, ptr %b.addr, align 32 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <4 x double>, ptr %b.addr, align 32 # | %vperm = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> # | ret <4 x double> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_permute2f128_ps(<8 x float> noundef %a, <8 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <8 x float>, align 32 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <8 x float> %b, ptr %b.addr, align 32 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <8 x float>, ptr %b.addr, align 32 # | %vperm = shufflevector <8 x float> %1, <8 x float> %0, <8 x i32> # | ret <8 x float> %vperm # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_permute2f128_si256(<4 x i64> noundef %a, <4 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <4 x i64>, align 32 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <4 x i64> %b, ptr %b.addr, align 32 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <4 x i64>, ptr %b.addr, align 32 # | %3 = bitcast <4 x i64> %2 to <8 x i32> # | %vperm = shufflevector <8 x i32> %1, <8 x i32> %3, <8 x i32> # | %4 = bitcast <8 x i32> %vperm to <4 x i64> # | ret <4 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_mm_broadcast_ss(ptr noundef %__a) #1 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <4 x float> %vecinit3.i, float %6, i32 3 # | store <4 x float> %vecinit4.i, ptr %.compoundliteral.i, align 16 # | %7 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_broadcast_sd(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__d.i = alloca double, align 8 # | %.compoundliteral.i = alloca <4 x double>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load double, ptr %1, align 1 # | store double %2, ptr %__d.i, align 8 # | %3 = load double, ptr %__d.i, align 8 # | %vecinit.i = insertelement <4 x double> poison, double %3, i32 0 # | %4 = load double, ptr %__d.i, align 8 # | %vecinit2.i = insertelement <4 x double> %vecinit.i, double %4, i32 1 # | %5 = load double, ptr %__d.i, align 8 # | %vecinit3.i = insertelement <4 x double> %vecinit2.i, double %5, i32 2 # | %6 = load double, ptr %__d.i, align 8 # | %vecinit4.i = insertelement <4 x double> %vecinit3.i, double %6, i32 3 # | store <4 x double> %vecinit4.i, ptr %.compoundliteral.i, align 32 # | %7 = load <4 x double>, ptr %.compoundliteral.i, align 32 # | ret <4 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_broadcast_ss(ptr noundef %__a) #0 { # | entry: # | %__a.addr.i = alloca ptr, align 8 # | %__f.i = alloca float, align 4 # | %.compoundliteral.i = alloca <8 x float>, align 32 # | %__a.addr = alloca ptr, align 8 # | store ptr %__a, ptr %__a.addr, align 8 # | %0 = load ptr, ptr %__a.addr, align 8 # | store ptr %0, ptr %__a.addr.i, align 8 # | %1 = load ptr, ptr %__a.addr.i, align 8 # | %2 = load float, ptr %1, align 1 # | store float %2, ptr %__f.i, align 4 # | %3 = load float, ptr %__f.i, align 4 # | %vecinit.i = insertelement <8 x float> poison, float %3, i32 0 # | %4 = load float, ptr %__f.i, align 4 # | %vecinit2.i = insertelement <8 x float> %vecinit.i, float %4, i32 1 # | %5 = load float, ptr %__f.i, align 4 # | %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %5, i32 2 # | %6 = load float, ptr %__f.i, align 4 # | %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %6, i32 3 # | %7 = load float, ptr %__f.i, align 4 # | %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %7, i32 4 # | %8 = load float, ptr %__f.i, align 4 # | %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %8, i32 5 # | %9 = load float, ptr %__f.i, align 4 # | %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %9, i32 6 # | %10 = load float, ptr %__f.i, align 4 # | %vecinit8.i = insertelement <8 x float> %vecinit7.i, float %10, i32 7 # | store <8 x float> %vecinit8.i, ptr %.compoundliteral.i, align 32 # | %11 = load <8 x float>, ptr %.compoundliteral.i, align 32 # | ret <8 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x float> @test_mm256_insertf128_ps_0(<8 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 32 # | %b.addr = alloca <4 x float>, align 16 # | store <8 x float> %a, ptr %a.addr, align 32 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <8 x float>, ptr %a.addr, align 32 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %widen = shufflevector <4 x float> %1, <4 x float> poison, <8 x i32> # | %insert = shufflevector <8 x float> %0, <8 x float> %widen, <8 x i32> # | ret <8 x float> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x double> @test_mm256_insertf128_pd_0(<4 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 32 # | %b.addr = alloca <2 x double>, align 16 # | store <4 x double> %a, ptr %a.addr, align 32 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <4 x double>, ptr %a.addr, align 32 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %widen = shufflevector <2 x double> %1, <2 x double> poison, <4 x i32> # | %insert = shufflevector <4 x double> %0, <4 x double> %widen, <4 x i32> # | ret <4 x double> %insert # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i64> @test_mm256_insertf128_si256_0(<4 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 32 # | %b.addr = alloca <2 x i64>, align 16 # | store <4 x i64> %a, ptr %a.addr, align 32 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <4 x i64>, ptr %a.addr, align 32 # | %1 = bitcast <4 x i64> %0 to <8 x i32> # | %2 = load <2 x i64>, ptr # | ... # `---data was truncated (10240/21933) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055853732915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585373260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055853732989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f138c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f138c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f138c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f138c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585372bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585372bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585372a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558536f530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558536f52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f138c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f138c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f138c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558536f52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-shuffle-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c (176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574fec8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574fec800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574fec8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc248105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc24815c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc248105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2480ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574fec18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005574fec18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005574febfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574fe8ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005574fe8acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc2480eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2480ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2480ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574fe8accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c (177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650fa22a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650fa2270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650fa22a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5a2c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5a2c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5a2c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5a2c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650fa1bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650fa1bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650fa1a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650f9e540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650f9e53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe5a2c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5a2c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5a2c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650f9e53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c (178 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinta.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinta.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinta_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinta.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cf7b54415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf7b5410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf7b54489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaee31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf7b4d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf7b4d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf7b4beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf7b16e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf7b16ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faaee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaee31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf7b16dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c (179 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.not.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.not.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.not.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.not.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.not.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_not.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c (180 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_bf16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtn_f8_f16( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtn.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnb_f8_f32( %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load { , }, ptr %zn_zm.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvtnb.nxv4f32( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_f8_f32( %zd, %zn_zm.coerce0, %zn_zm.coerce1, i64 noundef %fpm) #0 { # | entry: # | %zn_zm = alloca { , }, align 16 # | %zd.addr = alloca , align 16 # | %zn_zm.addr = alloca { , }, align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn_zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zn_zm.coerce1, 1 # | store { , } %1, ptr %zn_zm, align 16 # | %zn_zm1 = load { , }, ptr %zn_zm, align 16 # | store %zd, ptr %zd.addr, align 16 # | store { , } %zn_zm1, ptr %zn_zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load , ptr %zd.addr, align 16 # | %3 = load { , }, ptr %zn_zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %6) # | %7 = call @llvm.aarch64.sve.fp8.cvtnt.nxv4f32( %2, %4, %5) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563c27e9e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c27e9b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c27e9e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feca6e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feca6e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feca6e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feca6e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c27e33e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c27e33c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c27e18b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c27ac80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c27ac7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feca6e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feca6e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feca6e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c27ac7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c (181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b679f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b679f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b679f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16bb933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16bb98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16bb933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16bb91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b6798ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b6798ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b6796fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b6761f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b6761edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f16bb91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16bb91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16bb91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b6761ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c (182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558957e6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558957e620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558957e6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff33ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff33ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff33ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff33ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558957dfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558957dfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558957ddfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558957a8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558957a8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff33ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff33ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff33ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558957a8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c (183 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntd(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntd_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntd(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055746ef4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055746ef400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055746ef4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb622449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6224a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb622449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb622431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055746eed8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055746eed8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055746eebdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055746eb6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055746eb6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb622432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6224330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6224330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055746eb6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c (184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559325ac015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559325abd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559325ac089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe01eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe01eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe01eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe01eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559325a55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559325a55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559325a3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005593256ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005593256e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe01eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe01eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe01eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593256e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c (185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c (186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fd8fc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562fd8fbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562fd8fc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe90a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe90a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe90a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe90a231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fd8f56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562fd8f56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562fd8f3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562fd8beb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562fd8beadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe90a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe90a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe90a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fd8beacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c (187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c (188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c (189 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s8_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u8_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_s16_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x1_za32_u16_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 1, %0, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x1_za32_f16_f16( # | ... # `---data was truncated (10240/27272) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000557c4359c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c435990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c4359c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d53a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d53aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d53a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d53a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c43531e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c43531c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c43516b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c431c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c431c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7d53a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d53a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d53a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c431c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c (190 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sub.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sub.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sub.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb9dc4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb9dc440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb9dc4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9835333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f983538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9835333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f983531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb9dbdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb9dbdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb9dbc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb9d8710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb9d870dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f983531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f983531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f983531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb9d870cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c (191 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_s8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn1.coerce3, 3 # | store { , , , } %3, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %4 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zn2.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zn2.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zn2.coerce3, 3 # | store { , , , } %7, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | %8 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %9 = load { , , , }, ptr %zn1.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zn2.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | %19 = call { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret { , , , } %19 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount"), , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svsel_u8_x4(target("aarch64.svcount") %pn, %zn1.coerce0, %zn1.coerce1, %zn1.coerce2, %zn1.coerce3, %zn2.coerce0, %zn2.coerce1, %zn2.coerce2, %zn2.coerce3, ptr nofreeobj noundef align 16 dead_on_return %0, ptr nofreeobj noundef align 16 dead_on_return %1) #0 { # | entry: # | %zn1 = alloca { , , , }, align 16 # | %zn2 = alloca { , , , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn1.addr = alloca { , , , }, align 16 # | %zn2.addr = alloca { , , , }, align 16 # | %zn3.addr = alloca { , , , }, align 16 # | %zn4.addr = alloca { , , , }, align 16 # | %2 = insertvalue { , , , } poison, %zn1.coerce0, 0 # | %3 = insertvalue { , , , } %2, %zn1.coerce1, 1 # | %4 = insertvalue { , , , } %3, %zn1.coerce2, 2 # | %5 = insertvalue { , , , } %4, %zn1.coerce3, 3 # | store { , , , } %5, ptr %zn1, align 16 # | %zn11 = load { , , , }, ptr %zn1, align 16 # | %6 = insertvalue { , , , } poison, %zn2.coerce0, 0 # | %7 = insertvalue { , , , } %6, %zn2.coerce1, 1 # | %8 = insertvalue { , , , } %7, %zn2.coerce2, 2 # | %9 = insertvalue { , , , } %8, %zn2.coerce3, 3 # | store { , , , } %9, ptr %zn2, align 16 # | %zn22 = load { , , , }, ptr %zn2, align 16 # | %zn3 = load { , , , }, ptr %0, align 16 # | %zn4 = load { , , , }, ptr %1, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , , , } %zn11, ptr %zn1.addr, align 16 # | store { , , , } %zn22, ptr %zn2.addr, align 16 # | store { , , , } %zn3, ptr %zn3.addr, align 16 # | store { , , , } %zn4, ptr %zn4.addr, align 16 # | %10 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %11 = load { , , , }, ptr %zn1.addr, align 16 # | %12 = extractvalue { , , , } %11, 0 # | %13 = extractvalue { , , , } %11, 1 # | %14 = extractvalue { , , , } %11, 2 # | %15 = extractvalue { , , , } %11, 3 # | %16 = load { , , , }, ptr %zn2.addr, align 16 # | %17 = extractvalue { , , , } %16, 0 # | %18 = extractvalue { , , , } %16, 1 # | %19 = extractvalue { , , , } %16, 2 # | %20 = extractvalue { , , , } %16, 3 # | %21 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c (192 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svldr_zt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.ldr.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.ldr.zt.p0(i32, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svstr_zt(ptr noundef %base) #2 { # | entry: # | %base.addr = alloca ptr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sme.str.zt.p0(i32 0, ptr %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) # | declare void @llvm.aarch64.sme.str.zt.p0(i32, ptr) #3 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, target_mem0: readwrite) } # | attributes #2 = { noinline nounwind "aarch64_in_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write, target_mem0: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056516130c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005651613090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056516130c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b1b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b1b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b1b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b1b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651612a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005651612a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565161286b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565160f360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565160f35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b1b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b1b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b1b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565160f35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c (193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bea3bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558bea3b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558bea3bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f934a61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f934a6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f934a61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f934a603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bea350e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558bea350c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558bea335b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558be9fe50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558be9fe4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f934a604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f934a6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f934a6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558be9fe4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c (194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563df8f4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563df8f4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563df8f4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f1fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f1fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f1fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f1fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563df8ee3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563df8ee3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563df8ec8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563df8b780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563df8b77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f1fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f1fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f1fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563df8b77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c (195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca6eb3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca6eb350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca6eb3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47d3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47d378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47d3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47d371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca6eacde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca6eacdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca6eab2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca6e7620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca6e761dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f47d371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47d371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47d371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca6e761cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c (196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606a4d6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005606a4d640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005606a4d6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4276705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f427675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4276705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42766ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606a4cfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005606a4cfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005606a4ce1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005606a49910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005606a4990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42766eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42766ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42766ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606a4990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c (197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c (198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a96b8cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a96b8cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a96b8cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93d1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93d115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93d1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93d10ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a96b864e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a96b864c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a96b849b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a96b4f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a96b4f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93d10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93d10ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93d10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a96b4f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c (199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641a6b4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641a6b450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641a6b4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f777f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f777f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f777f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f777f803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641a6adde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005641a6addc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005641a6ac2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641a67720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641a6771dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f777f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f777f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f777f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641a6771cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon/store.c (200 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16(ptr noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | store <4 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32(ptr noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <2 x float> # | store <2 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | store <1 x double> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_mf8(ptr noundef %a, <8 x i8> %val) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %val.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %val, ptr %val.addr, align 8 # | %0 = load <8 x i8>, ptr %val.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p16(ptr noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | store <4 x i16> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p64(ptr noundef %ptr, <1 x i64> noundef %val) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store <1 x i64> %val, ptr %val.addr, align 8 # | %0 = load <1 x i64>, ptr %val.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %ptr.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | store <1 x i64> %3, ptr %1, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_p8(ptr noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | store <8 x i8> %2, ptr %1, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f16(ptr noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | store <8 x half> %3, ptr %1, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f32(ptr noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <4 x float>, align 16 # | %__s1 = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <4 x float> # | store <4 x float> %3, ptr %1, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1q_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr # | ... # `---data was truncated (10240/446007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000564b327a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b327a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b327a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a11d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a11d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a11d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a11ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b32738e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b32738c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b3271db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b323cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b323ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a11ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a11cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a11cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b323cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/store.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c (201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu( %ma # | ... # `---data was truncated (10240/619127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055666121c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566612190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055666121c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8117505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f811755c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8117505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81174ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566611b1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566611b1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556661196b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556660e460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556660e45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81174eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81174ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81174ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556660e45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c (202 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svuzp_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uzp.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ca2830415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca283010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca2830489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa2da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa2daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa2da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa2da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca28299e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca28299c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca2827eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca27f2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca27f2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa2da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa2da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa2da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca27f2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c (203 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005582dde9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582dde980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582dde9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f1cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f1cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f1cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f1cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582dde30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582dde30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582dde15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582ddac50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582ddac4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f1cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f1cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f1cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582ddac4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c (204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea4a6ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea4a6eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea4a6ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88e5333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88e538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88e5333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88e531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea4a683e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea4a683c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea4a668b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea4a3180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea4a317dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f88e531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88e531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88e531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea4a317cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c (205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608f0f6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005608f0f6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005608f0f6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f4b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f4b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f4b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f4b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608f0f04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005608f0f04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005608f0ee9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005608f0b990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005608f0b98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f4b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f4b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f4b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608f0b98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c (206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a540c5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a540c550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a540c5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc25ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc25eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc25ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc25ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a540bede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a540bedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a540bd2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5408820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a540881dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc25ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc25ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc25ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a540881cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c (207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d28f6ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d28f6fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d28f6ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6c3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6c3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6c3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6c3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d28f694e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d28f694c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d28f679b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d28f3290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d28f328dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff6c3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6c3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6c3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d28f328cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c (208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0aaf1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b0aaf0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b0aaf1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5d831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0aaea5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b0aaea5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b0aae8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b0aab3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b0aab39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f5d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0aab39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c (209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563aedc1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563aedc150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563aedc1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe124b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe124b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe124b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe124b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563aedbade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563aedbadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563aedb92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563aed8420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563aed841dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe124b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe124b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe124b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563aed841cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c (210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fbb55915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fbb5560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fbb55989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65ea733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65ea78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65ea733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65ea71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fbb4eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fbb4eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fbb4d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fbb1830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fbb182dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f65ea71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65ea71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65ea71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fbb182cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c (211 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmaxnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmaxnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmaxnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005616c6e4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005616c6e410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005616c6e4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6a4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6a458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6a4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6a451b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616c6dd9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005616c6dd9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005616c6dbeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005616c6a6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005616c6a6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa6a451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6a451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6a451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616c6a6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c (212 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005597d1cd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597d1ccd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597d1cd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f317af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f317af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f317af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f317af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597d1c65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597d1c65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597d1c4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597d18fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597d18f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f317af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f317af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f317af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597d18f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c (213 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564db5ee915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564db5ee60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564db5ee989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a06733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a06733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564db5e7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564db5e7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564db5e63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564db5b130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564db5b12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a0671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564db5b12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c (214 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret # | ... # `---data was truncated (10240/58597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055cc4d63f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc4d63c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc4d63f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f679b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f679b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f679b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f679b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc4d5d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc4d5d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc4d5b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc4d2690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc4d268dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f679b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f679b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f679b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc4d268cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/neon-intrinsics.c (215 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vmul_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <8 x i8> %2, %3 # | store <8 x i8> %mul.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmul_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <4 x i16> %2, %3 # | store <4 x i16> %mul.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmul_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %mul.i = mul <2 x i32> %2, %3 # | store <2 x i32> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <8 x i16> %2, %3 # | store <8 x i16> %mul.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmulq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <4 x i32> %2, %3 # | store <4 x i32> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vmulq_u8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %mul.i = mul <16 x i8> %2, %3 # | store <16 x i8> %mul.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmulq_u16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | s # | ... # `---data was truncated (10240/798827) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055efa77e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055efa77e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055efa77e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99b8505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99b855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99b8505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99b84ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efa777de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055efa777dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055efa7762b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055efa74120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055efa7411dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99b84eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99b84ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99b84ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efa7411cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp (216 of 27911) ******************** TEST 'Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z9cond_boolu10__SVBool_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ult %0, %1 # | %2 = load , ptr %a.addr, align 2 # | %3 = load , ptr %b.addr, align 2 # | %vector_select = select %cmp, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_i8u10__SVInt8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z7cond_u8u11__SVUint8_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i16u11__SVInt16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u16u12__SVUint16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i32u11__SVInt32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u32u12__SVUint32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_i64u11__SVInt64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp slt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_u64u12__SVUint64_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ult %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f16u13__SVFloat16_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load , ptr %b.addr, align 16 # | %vector_cond = icmp ne %sext, zeroinitializer # | %vector_select = select %vector_cond, %2, %3 # | ret %vector_select # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local @_Z8cond_f32u13__SVFloat32_tS_( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp olt %0, %1 # | %sext = sext %cmp to # | %2 = load , ptr %a.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c (217 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svminnm_single_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svminnm_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Funct # | ... # `---data was truncated (10240/50311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055598650115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005559864fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055598650189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bc0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bc038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bc0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bc031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555986496e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555986496c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055598647bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055598612b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055598612add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0bc031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bc031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bc031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055598612acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c (218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/92362) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a3134215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a3133f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a3134289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed54333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed5438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed54333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed5431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a312d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a312d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a312bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a30f6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a30f6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed5431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed5431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed5431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a30f6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c (219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c (220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/23405) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056420262815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005642026250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056420262889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ca5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ca5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ca5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ca5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642025bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005642025bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005642025a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005642022520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564202251dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7ca5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ca5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ca5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564202251cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c (221 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clastb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clastb.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclastb_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clastb.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c (222 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s8( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2q.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s16( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_u32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2q.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2q_s32( %pg, ptr noundef %base, %zt.coerce0, %zt.coerce1) #0 { # | entry: # | %zt = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zt.coerce0, 0 # | %1 = insertvalue { , } %0, %zt.coerce1, 1 # | store { , } %1, ptr %zt, align 16 # | %zt1 = load { , }, ptr %zt, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %zt1, ptr %zt.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %zt.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2q.nxv4i32.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c (223 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.ad # | ... # `---data was truncated (10240/17434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558d23ea115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d23e9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d23ea189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f479d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f479d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f479d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f479d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d23e36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d23e36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d23e1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d23acb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d23acadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f479d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f479d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f479d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d23acacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c (224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 # | ... # `---data was truncated (10240/28361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c12c74915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c12c7460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c12c74989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb888a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb888aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb888a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb888a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c12c6dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c12c6dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c12c6c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c12c3730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c12c372dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb888a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb888a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb888a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c12c372cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c (225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7668da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7668d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f7668da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f604e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f604e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f604e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f604e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f76686fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f76686fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f766854b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f7665040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f766503dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f604e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f604e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f604e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f766503cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c (226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c (227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634318d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005634318d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005634318d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfc4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfc4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfc4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfc4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056343186ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056343186ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563431853b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005634315030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563431502dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfc4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfc4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfc4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563431502cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c (228 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mla.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mla.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mla.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c (229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e2120315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e212000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e2120389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d8c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d8c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d8c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d8c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e21198e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e21198c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e2117db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e20e2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e20e2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d8c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d8c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d8c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e20e2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c (230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653db0c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653db0c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653db0c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca43a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca43aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca43a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca43a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653db058e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005653db058c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005653db03db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653daced0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005653dacecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca43a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca43a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca43a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653daceccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c (231 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmple_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005623bd22915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005623bd2260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005623bd22989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f654b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f654b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f654b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f654b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623bd1bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005623bd1bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005623bd1a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005623bce530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005623bce52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f654b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f654b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f654b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623bce52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c (232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d75a1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d75a1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d75a1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa24fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa24faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa24fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa24fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d759b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d759b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d75999b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d756490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d75648dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa24fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa24fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa24fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d75648cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c (233 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.x2.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32_x2( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_f32_x2( %op1, %op2, half noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store half %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load half, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, half %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.fdot.x2.nxv4f32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_f32_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fdot.lane.x2.nxv4f32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(, , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync no # | ... # `---data was truncated (10240/10512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005609f350c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609f35090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609f350c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb647049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6470a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb647049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb647031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609f34a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005609f34a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005609f3486b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609f31360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609f3135dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb647032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6470330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6470330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609f3135cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c (234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbba2d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbba2ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbba2d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d73249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d732a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d73249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d73231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbba266e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbba266c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbba24bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbb9efb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbb9efadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d73232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d732330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d732330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbb9efacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c (235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f66ac815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560f66ac50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560f66ac889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f50d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f50d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f50d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f50d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f66a5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560f66a5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560f66a42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560f666f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560f666f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f50d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f50d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f50d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f666f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c (236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1b5ddc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a1b5dd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a1b5ddc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafa0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafa078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafa0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafa071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1b5d71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a1b5d71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a1b5d56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a1b5a060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a1b5a05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fafa071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafa071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafa071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1b5a05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c (237 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldff1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/64727) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d51186f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d51186c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d51186f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f07533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f0758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f07533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f0751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d511804e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d511804c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5117e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5114990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d511498dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f0751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f0751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f0751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d511498cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c (238 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f16_1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv4f32( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtmad_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftmad.x.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftmad.x.nxv2f64(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005569dff7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569dff720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569dff7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f018d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f018d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f018d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f018d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569dff0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569dff0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569dfeefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569dfb9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569dfb9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f018d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f018d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f018d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569dfb9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c (239 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %and = and <8 x i8> %2, %3 # | store <8 x i8> %and, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %and = and <8 x i64> %0, %1 # | store <8 x i64> %and, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %and = and <64 x i8> %0, %1 # | store <64 x i8> %and, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %and = and <32 x i16> %0, %1 # | store <32 x i16> %and, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %and = and <16 x i32> %0, %1 # | store <16 x i32> %and, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c (240 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 1 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %x) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = load , ptr %x.addr, align 16 # | %5 = insertvalue { , , } %3, %4, 0 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svset3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c (241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560de647315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560de64700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560de647389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f06733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f0678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f06733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f0671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560de6408e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560de6408c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560de63edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560de609d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560de609cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f0671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f0671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f0671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560de609ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c (242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c044c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c044c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c044c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21d401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21d40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21d401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21d4003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c0445be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c0445bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c04440b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c040f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c040efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21d4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21d40050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21d40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c040efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/pfalse.c (243 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfalse_b() #0 { # | entry: # | ret zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055d92990015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9298fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d92990089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d78249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d782a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d78249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d78231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d929895e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d929895c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d92987ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d92952a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d929529dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4d78232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d782330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d782330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d929529cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/pfalse.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/eorv.c (244 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/eorv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.eorv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.eorv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.eorv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.eorv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_sveorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.eorv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_sveorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.eorv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_sveorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.eorv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_sveorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.eorv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000556a613ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a613ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a613ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f0b505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f0b55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f0b505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f0b4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a61343e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a61343c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a61328b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a60fd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a60fd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f0b4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f0b4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f0b4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a60fd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/eorv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddq.c (245 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = add <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fadd <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = add <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vaddq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fadd <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vaddq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055cd34d6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd34d6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd34d6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49b4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49b46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49b4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49b4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd34d04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd34d04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd34ce9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd349990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd34998dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f49b4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49b46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49b46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd34998cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c (246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c (247 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smax.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmax_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umax.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umax.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005609565b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609565b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609565b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd71ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd71ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd71ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd71ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056095654de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056095654dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560956532b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609561e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609561e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd71ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd71ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd71ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609561e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c (248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1f1f6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a1f1f6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a1f1f6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3999649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39996a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3999649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3999631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1f1f04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a1f1f04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a1f1ee9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a1f1b990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a1f1b98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3999632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39996330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39996330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1f1b98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c (249 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.add.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.add.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.add.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/72449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d3bdad415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3bdad10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3bdad489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3df5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3df598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3df5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3df591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3bda69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3bda69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3bda4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3bd6fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3bd6fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3df591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3df591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3df591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3bd6fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c (250 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +f64mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1ro.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1ro.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1ro.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ro_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055703af5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055703af4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055703af5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf58733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf5878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf58733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf5871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055703aee6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055703aee6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055703aecbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055703ab7b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055703ab7add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbf5871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf5871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf5871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055703ab7acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c (251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstrid # | ... # `---data was truncated (10240/28111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8af1b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d8af1b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d8af1b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ca4849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ca48a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ca4849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ca4831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8af148e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d8af148c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d8af12db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d8aeddd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d8aeddcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ca4832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ca48330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ca48330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8aeddccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c (252 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpa_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.fexpa.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fexpa.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d8f8e6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d8f8e610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d8f8e6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d6b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d6b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d6b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d6b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8f8df9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d8f8df9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d8f8ddeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d8f8a8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d8f8a8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d6b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d6b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d6b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8f8a8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c (253 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_int16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @subscript_uint16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_int32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @subscript_uint32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_int64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @subscript_uint64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @subscript_float16( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @subscript_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @subscript_float64( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecins = insertelement %1, float 1.000000e+00, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %2 = load , ptr %a.addr, align 16 # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @subscript_read_write_float32( %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i64, align 8 # | store %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %b.addr, align 8 # | %1 = load , ptr %a.addr, align 16 # | %vecext = extractelement %1, i64 %0 # | %add = fadd float %vecext, 1.000000e+00 # | %2 = load , ptr %a.addr, align 16 # | %vecins = insertelement %2, float %add, i64 %0 # | store %vecins, ptr %a.addr, align 16 # | %3 = load , ptr %a.addr, align 16 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000056366c25815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056366c2550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056366c25889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25e2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25e2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25e2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25e2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056366c1ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056366c1edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056366c1d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056366be820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056366be81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25e2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25e2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25e2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056366be81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c (254 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x1_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 1, %3, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.2x1.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x1_za32_u8_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { < # | ... # `---data was truncated (10240/50499) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562c4d93515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c4d9320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c4d93589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdebc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdebc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdebc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdebc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c4d8cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c4d8cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c4d8afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c4d55f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c4d55edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdebc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdebc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdebc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c4d55ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c (255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b00d39e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b00d39b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b00d39e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b5c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b00d333e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b00d333c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b00d318b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b00cfc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b00cfc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b00cfc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c (256 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u8( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u16( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.add.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_u32( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.add.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svadd_vector_single2_s64( %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c (257 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincw.n32(i32 %0, i32 4, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincw.n64(i64 %0, i32 5, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincw.n32(i32 %0, i32 6, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincw.n64(i64 %0, i32 7, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincw.nxv4i32( %0, i32 8, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincw.nxv4i32( %0, i32 9, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560188ff415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560188ff10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560188ff489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5648133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f564818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5648133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f564811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560188f89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560188f89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560188f6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560188c1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560188c1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f564811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f564811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f564811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560188c1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c (258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c (259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee47cce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee47ccb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee47cce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20b7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20b76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20b7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20b7631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee47c63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee47c63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee47c48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee478f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee478f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f20b7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20b76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20b76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee478f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c (260 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c (261 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000558ab551515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ab55120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ab551589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6771f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6771f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6771f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6771f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ab54aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ab54aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ab548fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ab513f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ab513edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6771f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6771f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6771f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ab513ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c (262 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg1x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg1x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg2x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg2x4(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x1(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x1(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x2(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svzero_za64_vg4x4(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.zero.za64.vg4x4(i32) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sme2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c42f60415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c42f6010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c42f60489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0c4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0c40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0c4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0c4031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c42f599e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c42f599c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c42f57eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c42f22e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c42f22ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd0c4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0c40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0c40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c42f22dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c (263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9000c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9000c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9000c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63b9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63b998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63b9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63b991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c90005ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c90005ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c900043b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8ffcf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8ffcf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63b991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63b991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63b991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8ffcf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c (264 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055db2ed2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db2ed1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db2ed2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e5ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e5eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e5ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e5ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db2ecb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db2ecb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db2ec9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db2e94a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db2e949dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2e5ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e5ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e5ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db2e949cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c (265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056135bbd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056135bbd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056135bbd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4759333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f475938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4759333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f475931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056135bb6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056135bb6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056135bb51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056135b8010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056135b800dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f475931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f475931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f475931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056135b800cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c (266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055effb81115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055effb80e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055effb81189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e45733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e4578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e45733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e4571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055effb7a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055effb7a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055effb78bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055effb43b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055effb43add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e4571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e4571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e4571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055effb43acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c (267 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za16_vg2x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %4, %6, %7, %8, %9, %10, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x1(i32 noundef %slice, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store i32 %slice, ptr %slice.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %0, %1, %2, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %2, %4, %5, %6, i32 15) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_lane_za32_vg4x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | %0 # | ... # `---data was truncated (10240/39820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055c9a5d7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9a5d790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9a5d7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf1e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf1e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf1e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf1e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9a5d11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9a5d11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9a5cf6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9a59a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9a59a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf1e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf1e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf1e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9a59a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c (268 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_s64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_u64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f16() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f32() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_f64() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_mf8() #0 { # | entry: # | ret undef # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svundef_bf16() #0 { # | entry: # | ret undef # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c95432815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9543250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c95432889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc744849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7448a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc744849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc744831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9542bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9542bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9542a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c953f520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c953f51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc744832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7448330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7448330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c953f51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c (269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6ae64415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6ae6410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a6ae64489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e20a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e20aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e20a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e20a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6ae5d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a6ae5d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a6ae5beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a6ae26e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a6ae26ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7e20a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e20a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e20a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6ae26dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c (270 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e80806115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e80805e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e80806189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d43d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d43d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d43d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d43d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e807ff6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e807ff6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e807fdbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e807c8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e807c8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d43d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d43d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d43d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e807c8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c (271 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d9d929f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9d929c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9d929f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bb981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bb98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bb981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bb9803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9d9234e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9d9234c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9d9219b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9d8ec90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9d8ec8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bb9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bb98050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bb98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9d8ec8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: Modules/pr93497.cppm (272 of 27911) ******************** TEST 'Clang :: Modules/pr93497.cppm' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: rm -rf /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 3 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/Modules/pr93497.cppm /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.cppm -emit-module-interface -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp -fmodule-file=mod=/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/mod.pcm -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.Thing = type { i32 } # | %struct.C = type { i32 } # | %struct.NonConstexprDtor = type { i32 } # | # | $needed = comdat any # | # | @_ZNW3mod5Thing3OneE = external global %struct.Thing, align 4 # | @_ZW3mod13ConstantValue = available_externally constant %struct.C { i32 1 }, align 4 # | @_ZW3mod11ConstantPtr = external global ptr, align 8 # | @_ZW3mod16NonConstantValue = external global %struct.C, align 4 # | @_ZW3mod21NonConstexprDtorValue = external global %struct.NonConstexprDtor, align 4 # | @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_use.cpp, ptr null }] # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z3usev() #0 { # | entry: # | %t1 = alloca %struct.Thing, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %t1, ptr align 4 @_ZNW3mod5Thing3OneE, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.Thing, ptr %t1, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | declare noundef i32 @_Z7consumei(i32 noundef) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use2v() #0 { # | entry: # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 @_ZW3mod13ConstantValue, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %0 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %0) # | ret i32 %call # | } # | # | declare noundef i32 @_Z8consumeCW3mod1C(i32) #2 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use3v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ptr = alloca ptr, align 8 # | %agg.tmp = alloca %struct.C, align 4 # | %0 = load ptr, ptr @_ZW3mod11ConstantPtr, align 8 # | store ptr %0, ptr %Ptr, align 8 # | %1 = load ptr, ptr %Ptr, align 8 # | %value = getelementptr inbounds nuw %struct.C, ptr %1, i32 0, i32 0 # | %2 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %2, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %3 = load ptr, ptr %Ptr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %3, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %4 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %4) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr i32 @needed() #0 comdat { # | entry: # | %call = call noundef i32 @_Z7consumei(i32 noundef 43) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use4v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %Ref = alloca %struct.C, align 4 # | %agg.tmp = alloca %struct.C, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %Ref, ptr align 4 @_ZW3mod16NonConstantValue, i64 4, i1 false) # | %value = getelementptr inbounds nuw %struct.C, ptr %Ref, i32 0, i32 0 # | %0 = load i32, ptr %value, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp, ptr align 4 %Ref, i64 4, i1 false) # | %coerce.dive = getelementptr inbounds nuw %struct.C, ptr %agg.tmp, i32 0, i32 0 # | %1 = load i32, ptr %coerce.dive, align 4 # | %call = call noundef i32 @_Z8consumeCW3mod1C(i32 %1) # | store i32 %call, ptr %retval, align 4 # | br label %return # | # | if.end: ; preds = %entry # | %call1 = call i32 @needed() # | store i32 %call1, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %if.end, %if.then # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z4use5v() #0 { # | entry: # | %retval = alloca i32, align 4 # | %V = alloca %struct.NonConstexprDtor, align 4 # | %cleanup.dest.slot = alloca i32, align 4 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %V, ptr align 4 @_ZW3mod21NonConstexprDtorValue, i64 4, i1 false) # | %raw = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %0 = load i32, ptr %raw, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.end # | # | if.then: ; preds = %entry # | %raw1 = getelementptr inbounds nuw %struct.NonConstexprDtor, ptr %V, i32 0, i32 0 # | %1 = load i32, ptr %raw1, align 4 # | %call = call noundef i32 @_Z7consumei(i32 noundef %1) # | store i32 %call, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | if.end: ; preds = %entry # | %call2 = call i32 @needed() # | store i32 %call2, ptr %retval, align 4 # | store i32 1, ptr %cleanup.dest.slot, align 4 # | br label %cleanup # | # | cleanup: ; preds = %if.end, %if.then # | call void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %V) #5 # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind # | declare void @_ZNW3mod16NonConstexprDtorD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4)) unnamed_addr #3 # | # | declare void @_ZGIW3mod() # | # | ; Function Attrs: noinline nounwind # | define internal void @_GLOBAL__sub_I_use.cpp() #4 section ".text.startup" { # | entry: # | call void @_ZGIW3mod() # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #2 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #3 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #4 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #5 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=simplifycfg # | #0 0x00005609f77c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609f77c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609f77c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8aa221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8aa22725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8aa221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8aa2203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609f775de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005609f775dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005609f7742b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609f73f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609f73f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8aa2204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8aa22050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8aa22050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609f73f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/Modules/Output/pr93497.cppm.tmp/use.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c (273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566bf5f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566bf5ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566bf5f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f9ec1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f9ec725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f9ec1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f9ec03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566bf586e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566bf586c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566bf56bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566bf21b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566bf21add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6f9ec04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f9ec050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f9ec050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566bf21acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c (274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055780821015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055780820d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055780821089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfc8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfc878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfc8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfc871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578081a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005578081a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055780818ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557807e3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557807e39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfc871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfc871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfc871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557807e39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c (275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d08205815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d0820550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d08205889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3f5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3f5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3f5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3f5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d081fede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d081fedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d081fd2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d081c820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d081c81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3f5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3f5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3f5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d081c81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c (276 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv8f16(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f16mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005583f878615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583f87830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005583f878689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3057133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f305718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3057133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f305711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583f871be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583f871bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583f8700b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583f83b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005583f83afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f305711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f305711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f305711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583f83afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c (277 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635eece815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005635eece50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005635eece889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f069cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f069cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f069cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f069cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635eec7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005635eec7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005635eec62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635ee9120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005635ee911dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f069cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f069cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f069cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635ee911cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c (278 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uzp.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svuzp_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005574cd8fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574cd8fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574cd8fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff88d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff88d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff88d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff88d831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574cd893e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005574cd893c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005574cd878b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574cd5280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005574cd527dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff88d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff88d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff88d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574cd527cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c (279 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdech.n32(i32 %0, i32 10, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdech.n64(i64 %0, i32 11, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdech_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %0, i32 12, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdech_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %0, i32 13, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdech.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdech.nxv8i16( %0, i32 29, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdech_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdech.nxv8i16( %0, i32 30, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557ed90be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557ed90bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557ed90be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f919e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f919e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f919e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f919e231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ed9053e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557ed9053c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557ed9038b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557ed8ce80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557ed8ce7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f919e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f919e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f919e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ed8ce7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c (280 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vsqrt_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vsqrt.i = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %vsqrt.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %3, ptr %__ret.i, align 8 # | %4 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vsqrtq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vsqrt.i = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %3, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vsqrtq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %vsqrt.i = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double> %2, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055aa8823615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aa882330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aa8823689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe14001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1400725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe14001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe140003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa881cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aa881cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aa881b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aa87e600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aa87e5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe140004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1400050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1400050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa87e5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics-constrained.c --check-prefix=LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c (281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , al # | ... # `---data was truncated (10240/226593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9dd5d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9dd5d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9dd5d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe84a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe84a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe84a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe84a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9dd569e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9dd569c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9dd54eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9dd1fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e9dd1fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe84a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe84a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe84a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9dd1fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c (282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c (283 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f16_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f32_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_f64_x2( %op1.coerce0, %op1.coerce1, %op2) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = call { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.fp8.scale.single.x2.nxv2f64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f16_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %op2.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sme.fp8.scale.single.x4.nxv8f16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_f32_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr # | ... # `---data was truncated (10240/37349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005644fbae715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644fbae40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644fbae789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ffd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ffd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ffd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ffd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644fba7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644fba7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644fba61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644fb7110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644fb710dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ffd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ffd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ffd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644fb710cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c (284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559baa9f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559baa9f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559baa9f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f443dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f443dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f443dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f443dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559baa98ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559baa98ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559baa973b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559baa6230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559baa622dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f443dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f443dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f443dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559baa622cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (285 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_b( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | %x2.addr = alloca , align 2 # | %x4.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | store %x2, ptr %x2.addr, align 2 # | store %x4, ptr %x4.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = load , ptr %x2.addr, align 2 # | %3 = load , ptr %x4.addr, align 2 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562c6141615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c614130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c6141689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb34621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3462725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb34621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb346203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c613abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c613abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c61390b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c610400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c6103fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb346204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3462050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3462050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c6103fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c (286 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_u8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_1x2_za32_s8_u8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { , }, ptr %zm, align 16 # | store %zn, ptr %zn.addr, align 16 # | store { , } %zm1, ptr %zm.addr, align 16 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load { , }, ptr %zm.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 1, %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 immarg, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_1x2_za32_u8_s8( %zn, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zm = alloca { , }, align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zm.coerce0, 0 # | %1 = insertvalue { , } %0, %zm.coerce1, 1 # | store { , } %1, ptr %zm, align 16 # | %zm1 = load { < # | ... # `---data was truncated (10240/50724) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eebd2ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eebd2cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eebd2ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe161b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe161b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe161b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe161b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eebd263e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eebd263c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eebd248b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eebcef80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eebcef7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe161b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe161b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe161b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eebcef7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c (287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef722ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef722c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef722ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb35c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb35ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb35c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb35c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef7225fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef7225fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef72244b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef71ef40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef71ef3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbb35c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb35c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb35c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef71ef3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-2velem.c (288 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-2velem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_72 = alloca <4 x i16>, align 8 # | %__s0_72 = alloca <4 x i16>, align 8 # | %__s1_72 = alloca <4 x i16>, align 8 # | %__s2_72 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_72, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_72, align 8 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_72, align 8 # | %3 = load <4 x i16>, ptr %__s0_72, align 8 # | %4 = load <4 x i16>, ptr %__s1_72, align 8 # | %5 = load <4 x i16>, ptr %__s2_72, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_72, align 8 # | %11 = load <4 x i16>, ptr %__ret_72, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_lane_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <4 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <4 x i16>, align 8 # | %__ret_62 = alloca <8 x i16>, align 16 # | %__s0_62 = alloca <8 x i16>, align 16 # | %__s1_62 = alloca <8 x i16>, align 16 # | %__s2_62 = alloca <4 x i16>, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <4 x i16> %v, ptr %v.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_62, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_62, align 16 # | %2 = load <4 x i16>, ptr %v.addr, align 8 # | store <4 x i16> %2, ptr %__s2_62, align 8 # | %3 = load <8 x i16>, ptr %__s0_62, align 16 # | %4 = load <8 x i16>, ptr %__s1_62, align 16 # | %5 = load <4 x i16>, ptr %__s2_62, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | %mul = mul <8 x i16> %4, %10 # | %add = add <8 x i16> %3, %mul # | store <8 x i16> %add, ptr %__ret_62, align 16 # | %11 = load <8 x i16>, ptr %__ret_62, align 16 # | store <8 x i16> %11, ptr %tmp1, align 16 # | %12 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vmla_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_70 = alloca <2 x i32>, align 8 # | %__s0_70 = alloca <2 x i32>, align 8 # | %__s1_70 = alloca <2 x i32>, align 8 # | %__s2_70 = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_70, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_70, align 8 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_70, align 8 # | %3 = load <2 x i32>, ptr %__s0_70, align 8 # | %4 = load <2 x i32>, ptr %__s1_70, align 8 # | %5 = load <2 x i32>, ptr %__s2_70, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | %mul = mul <2 x i32> %4, %10 # | %add = add <2 x i32> %3, %mul # | store <2 x i32> %add, ptr %__ret_70, align 8 # | %11 = load <2 x i32>, ptr %__ret_70, align 8 # | store <2 x i32> %11, ptr %tmp1, align 8 # | %12 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmlaq_lane_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <2 x i32> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <2 x i32>, align 8 # | %__ret_60 = alloca <4 x i32>, align 16 # | %__s0_60 = alloca <4 x i32>, align 16 # | %__s1_60 = alloca <4 x i32>, align 16 # | %__s2_60 = alloca <2 x i32>, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <2 x i32> %v, ptr %v.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_60, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1_60, align 16 # | %2 = load <2 x i32>, ptr %v.addr, align 8 # | store <2 x i32> %2, ptr %__s2_60, align 8 # | %3 = load <4 x i32>, ptr %__s0_60, align 16 # | %4 = load <4 x i32>, ptr %__s1_60, align 16 # | %5 = load <2 x i32>, ptr %__s2_60, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <4 x i32> # | store <4 x i32> %lane, ptr %ref.tmp, align 16 # | %8 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %8, ptr %__ret, align 16 # | %9 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %9, ptr %tmp, align 16 # | %10 = load <4 x i32>, ptr %tmp, align 16 # | %mul = mul <4 x i32> %4, %10 # | %add = add <4 x i32> %3, %mul # | store <4 x i32> %add, ptr %__ret_60, align 16 # | %11 = load <4 x i32>, ptr %__ret_60, align 16 # | store <4 x i32> %11, ptr %tmp1, align 16 # | %12 = load <4 x i32>, ptr %tmp1, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vmla_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_482 = alloca <4 x i16>, align 8 # | %__s0_482 = alloca <4 x i16>, align 8 # | %__s1_482 = alloca <4 x i16>, align 8 # | %__s2_482 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_482, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_482, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_482, align 16 # | %3 = load <4 x i16>, ptr %__s0_482, align 8 # | %4 = load <4 x i16>, ptr %__s1_482, align 8 # | %5 = load <8 x i16>, ptr %__s2_482, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | %mul = mul <4 x i16> %4, %10 # | %add = add <4 x i16> %3, %mul # | store <4 x i16> %add, ptr %__ret_482, align 8 # | %11 = load <4 x i16>, ptr %__ret_482, align 8 # | store <4 x i16> %11, ptr %tmp1, align 8 # | %12 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_472 = alloca <8 x i16>, align 16 # | %__s0_472 = alloca <8 x i16>, align 16 # | %__s1_472 = alloca <8 # | ... # `---data was truncated (10240/857511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c44a6a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c44a6a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c44a6a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3b9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3b98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3b9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3b9831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c44a63be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c44a63bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c44a620b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c44a2d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c44a2cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc3b9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3b98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3b98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c44a2cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-2velem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c (289 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tblq.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtblq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.tblq.nxv16i8( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "sta # | ... # `---data was truncated (10240/10820) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005621e374a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621e37470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005621e374a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe364d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe364d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe364d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe364d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621e36dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621e36dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621e36c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621e33740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005621e3373dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe364d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe364d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe364d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621e3373cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c (290 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmla.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563a9afdf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a9afdc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a9afdf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9157649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91576a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9157649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9157631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a9af74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a9af74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a9af59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a9ac090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a9ac08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9157632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91576330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91576330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a9ac08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c (291 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u16_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_s64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.sunpk.x4.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svunpk_u64_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64( %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.uunpk.x4.nxv2i64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560ec53fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560ec53fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560ec53fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70ae049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70ae0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70ae049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70ae031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ec5392e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560ec5392c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560ec5377b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560ec50270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560ec5026dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70ae032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70ae0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70ae0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ec5026cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c (292 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.lsr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsr_u8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.lsr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/33353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005642ee0a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005642ee09f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005642ee0a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe6f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe6f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe6f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe6f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642ee037e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005642ee037c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005642ee01cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005642edccc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005642edccbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbe6f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe6f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe6f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642edccbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c (293 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = select %0, %1, zeroinitializer # | %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 8) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %3, i32 16) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, %3, i32 32) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 1) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asrd.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s64_z_1( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = select %2, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asrd.nxv2i64( %2, %3, i32 64) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s8_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s16_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv8i16( %2, %1, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasrd_n_s32_m( %pg, %op1) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.asrd.nxv4i32( %2, # | ... # `---data was truncated (10240/14353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563657a2d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563657a2a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563657a2d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02d7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02d72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02d7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02d7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636579c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005636579c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005636579a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636576570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563657656dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02d7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02d72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02d72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563657656cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c (294 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.lsl.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.lsl.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.lsl.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svlsl_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/53158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dedeed315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dedeed00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dedeed389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dedee68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dedee68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dedee4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dedeafd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dedeafcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff9b331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dedeafccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c (295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a20288015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a20287d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a20288089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f222e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f222e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f222e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f222e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a202815e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a202815c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2027fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2024aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2024a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f222e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f222e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f222e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2024a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c (296 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmov_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.and.z.nxv16i1( %0, %1, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055dd6262c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd626290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd6262c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd04b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd04b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd04b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd04b203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd625c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd625c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd625a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd622560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd62255dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd04b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd04b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd04b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd62255cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-vget-hilo.c (297 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vget-hilo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x half> %1, <8 x half> %2, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <1 x double>, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x double> %1, <2 x double> %2, <1 x i32> # | store <1 x double> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/20383) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a0335515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a033520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a0335589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79a6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79a60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79a6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79a6031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a032eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a032eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a032cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a02f7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a02f7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f79a6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79a60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79a60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a02f7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vget-hilo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c (298 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpa_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpa.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpa.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d591a3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d591a350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d591a3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd79cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd79cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd79cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd79cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5919cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5919cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5919b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5916620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d591661dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd79cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd79cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd79cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d591661cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c (299 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za16_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za16(i32 1, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_za32_mf8_m( %pn, %pm, %zn, %zm, i64 noundef %fpmr) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %4) # | call void @llvm.aarch64.sme.fp8.fmopa.za32(i32 3, %0, %1, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fmopa.za32(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055feea8d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055feea8cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055feea8d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd141b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd141b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd141b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd141b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feea865e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055feea865c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055feea84ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055feea4fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055feea4f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd141b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd141b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd141b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feea4f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c (300 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpfirst_b( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.pfirst.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pfirst.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556d2100115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d20ffe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d2100189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bc1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bc175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bc1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bc16ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d20f96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d20f96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d20f7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d20c2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d20c2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3bc16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bc16ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bc16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d20c2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (301 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_0( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_b_1( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055aa0cb3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aa0cb330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aa0cb3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f710d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f710d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f710d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f710d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa0cacbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aa0cacbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aa0cab0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aa0c7600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aa0c75fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f710d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f710d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f710d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa0c75fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c (302 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintz.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintz.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintz_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintz.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564da355915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564da35560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564da355989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fc481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fc48725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fc481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fc4803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564da34eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564da34eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564da34d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564da31830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564da3182dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fc4804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fc48050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fc48050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564da3182cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c (303 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3cc0b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3cc0ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3cc0b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe64d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe64d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe64d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe64d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3cc046e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e3cc046c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e3cc02bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3cbcdb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3cbcdadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe64d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe64d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe64d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3cbcdacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c (304 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd7e52815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd7e5250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd7e52889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1602f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1602f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1602f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1602f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd7e4bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd7e4bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd7e4a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd7e1520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd7e151dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1602f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1602f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1602f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd7e151cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c (305 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000555736bb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555736bb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555736bb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff381933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff38198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff381933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff38191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555736b4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555736b4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555736b33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557367e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557367e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff38191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff38191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff38191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557367e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c (306 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x4.nxv8i16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.udot.za32.vg1x2.nxv16i8(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_u8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align # | ... # `---data was truncated (10240/127452) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005570278dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570278d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570278dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb5c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb5c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb5c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb5c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557027871e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557027871c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557027856b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570275060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557027505dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdb5c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb5c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb5c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557027505cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c (307 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4i32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_u32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_s32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4i32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1wq.nxv4f32.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1wq_vnum_f32( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 1 # | call void @llvm.aarch64.sve.st1wq.nxv4f32.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1dq.nxv2i64.p0(, , ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_u64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_vnum_s64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr, align 16 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %zt.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = getelementptr , ptr %1, i64 -8 # | call void @llvm.aarch64.sve.st1dq.nxv2i64.p0( %2, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1dq_f64( %pred, ptr noundef %base, %zt) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %zt.addr = alloca , align 16 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %zt, ptr %zt.addr # | ... # `---data was truncated (10240/12466) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e54d6b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e54d6b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e54d6b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa54449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa544a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa54449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa54431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e54d64ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e54d64ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e54d633b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e54d2e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e54d2e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa54432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa544330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa544330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e54d2e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c (308 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrffr( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | call void @llvm.aarch64.sve.wrffr( %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.wrffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055617c2ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055617c2a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055617c2ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc38cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc38cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc38cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc38cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055617c241e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055617c241c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055617c226b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055617bed60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055617bed5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc38cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc38cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc38cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055617bed5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c (309 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_u16_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fcvtzs.i32f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtzs.i32f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt_s32_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtzs.i32f16( %0, %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c (310 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c (311 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005582ee45f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582ee45c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582ee45f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5ab249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5ab2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5ab249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5ab231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582ee3f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582ee3f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582ee3d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582ee0890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582ee088dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5ab232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5ab2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5ab2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582ee088cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c (312 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.asr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.asr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svasr_s8_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.asr.u.nxv16i8( %0, %1, %2) # | # | ... # `---data was truncated (10240/46416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562926ac515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562926ac20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562926ac589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8696733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f869678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8696733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f869671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562926a5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562926a5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562926a3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629266ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629266eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f869671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f869671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f869671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629266eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c (313 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-shift-ops.c (314 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = ashr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shl = shl %0, %1 # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @rshift_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %shr = lshr %0, %1 # | ret %shr # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_rsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load , ptr %a.addr, align 16 # | %1 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %1, i64 0 # | %splat.splat = shufflevector %splat.splatinsert, poison, zeroinitializer # | %shl = shl %0, %splat.splat # | ret %shl # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @lshift_i8_lsplat( %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca i8, align 1 # | store %a, ptr %a.addr, align 16 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i8, ptr %b.addr, align 1 # | %splat.splatinsert = insertelement poison, i8 %0, i64 0 # | %splat.splat # | ... # `---data was truncated (10240/32491) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005653c614715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653c61440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653c614789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e5fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e5fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e5fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e5fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653c60dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005653c60dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005653c60c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653c5d710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005653c5d70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e5fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e5fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e5fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653c5d70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-shift-ops.c (315 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = ashr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shl = shl <64 x i8> %0, %1 # | store <64 x i8> %shl, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %shr = lshr <64 x i8> %0, %1 # | store <64 x i8> %shr, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = ashr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shl = shl <32 x i16> %0, %1 # | store <32 x i16> %shl, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %shr = lshr <32 x i16> %0, %1 # | store <32 x i16> %shr, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %shl = shl <16 x i32> %0, %1 # | store <16 x i32> %shl, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 imma # | ... # `---data was truncated (10240/51475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005603d9bbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603d9bbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603d9bbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb47c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb47c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb47c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb47c803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603d9b54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005603d9b54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603d9b39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005603d97e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005603d97e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb47c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb47c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb47c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603d97e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c (316 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_s64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_u64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f32() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_f64() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_mf8() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_bf16() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e31dd9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e31dd900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e31dd9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f8c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f8c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f8c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f8c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e31dd28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e31dd28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e31dd0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e31d9bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e31d9bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f8c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f8c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f8c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e31d9bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c (317 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c552b1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c552b160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c552b1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77f4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77f4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77f4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77f4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c552aaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c552aaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c552a93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5527430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c552742dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f77f4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77f4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77f4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c552742cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c (318 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udivr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udivr.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdivr_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c (319 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mad.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mad.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmad_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mad.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c (320 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d2a3c1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d2a3c140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d2a3c1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda35449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda354a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda35449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda35431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2a3bace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d2a3bacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d2a3b91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d2a38410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d2a3840dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fda35432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda354330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda354330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2a3840cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c (321 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmls.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmls.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c4ae49715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c4ae4940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c4ae49789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb4c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb4c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb4c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb4c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4ae42ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c4ae42cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c4ae411b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4ae0c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4ae0c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb4c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb4c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb4c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4ae0c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c (322 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_u8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 immarg, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_luti4_zt_s8_x4( %op.coerce0, %op.coerce1) #0 { # | entry: # | %op = alloca { , }, align 16 # | %op.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %op.coerce0, 0 # | %1 = insertvalue { , } %0, %op.coerce1, 1 # | store { , } %1, ptr %op, align 16 # | %op1 = load { , }, ptr %op, align 16 # | store { , } %op1, ptr %op.addr, align 16 # | %2 = load { , }, ptr %op.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , , , } @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, %3, %4) # | ret { , , , } %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-lutv2,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055c014d2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c014d250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c014d2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12fc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12fc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12fc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12fc031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c014cbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c014cbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c014ca2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0149520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c014951dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f12fc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12fc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12fc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c014951cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c (323 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx1( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.lane.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx3( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_lane_bf16_idx7( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.fmul.lane.nxv8bf16( %0, %1, i32 7) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055dad595415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dad59510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dad595489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe0901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe090725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe0901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe09003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dad58e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dad58e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dad58ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dad557e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dad557ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe09004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe090050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe090050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dad557dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c (324 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fminnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fminnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svminnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fminnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005557efc6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557efc5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557efc6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f151bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f151bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f151bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f151bced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557efbf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557efbf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557efbdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557ef88a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557ef889dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f151bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f151bcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f151bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557ef889cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c (325 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv16i8(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8i16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4i32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 0, %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare @llvm.aarch64.sme.luti4.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005557b11cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557b11ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557b11cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62f2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62f2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62f2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62f2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557b1162e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557b1162c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557b1147b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557b0df70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557b0df6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62f2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62f2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62f2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557b0df6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c (326 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqsub.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqsub.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqsub_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqsub.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a33307415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3330710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a33307489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c78533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c7858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c78533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c7851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a333009e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a333009c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a332feeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a332c9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a332c9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c7851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c7851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c7851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a332c9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c (327 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmla.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmla_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055938bf3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055938bf310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055938bf3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d16705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d1675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d16705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d166ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055938bec9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055938bec9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055938beaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055938bb5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055938bb5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9d166eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d166ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d166ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055938bb5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c (328 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.and.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.and.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.and.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svand_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556537adb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556537ad80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556537adb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57e961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57e96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57e961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57e9603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556537a70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556537a70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556537a55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005565377050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556537704dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f57e9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57e96050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57e96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556537704cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_and.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c (329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592e979115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005592e978e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005592e979189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1d8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1d858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1d8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1d851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592e9726e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005592e9726c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005592e970bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592e93bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005592e93badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd1d851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1d851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1d851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592e93bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c (330 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_ver_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.ver.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 immarg, i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_s8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_mf8_vg2(i32 noundef %base, %val.coerce0, %val.coerce1) #0 { # | entry: # | %val = alloca { , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %val.coerce0, 0 # | %1 = insertvalue { , } %0, %val.coerce1, 1 # | store { , } %1, ptr %val, align 16 # | %val1 = load { , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , } %val1, ptr %val.addr, align 16 # | %2 = load i32, ptr %base.addr, align 4 # | %3 = load { , }, ptr %val.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | call void @llvm.aarch64.sme.write.hor.vg2.nxv16i8(i32 0, i32 %2, %4, %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svwrite_hor_za8_u8_vg4(i32 noundef %base, %val.coerce0, %val.coerce1, %val.coerce2, %val.coerce3) #0 { # | entry: # | %val = alloca { , , , }, align 16 # | %base.addr = alloca i32, align 4 # | %val.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %val.coerce0, 0 # | %1 = insertvalue { , , , } %0, %val.coerce1, 1 # | %2 = insertvalue { , , , } %1, %val.coerce2, 2 # | %3 = insertvalue { , , , } %2, %val.coerce3, 3 # | store { , , , } %3, ptr %val, align 16 # | %val1 = load { , , , }, ptr %val, align 16 # | store i32 %base, ptr %base.addr, align 4 # | store { , , , } %val1, ptr %val.addr, align 16 # | %4 = load i32, ptr %base.addr, align 4 # | %5 = load { , , , }, ptr %val.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c (331 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalb.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_n_f16_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splatinsert = insertelement poison, i8 %4, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fp8.fmlalt.nxv8f16( %0, %1, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalb_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlalt_lane_f16_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16( %0, %1, %2, i32 7) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_f32_mf8( %zda, %zn, %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmlallbb_n_f32_mf8( %zda, %zn, <1 x i8> %zm, i64 noundef %fpm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca <1 x i8>, align 1 # | %fpm.addr = alloca i64, align 8 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store <1 x i8> %zm, ptr %zm.addr, align 1 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load <1 x i8>, ptr %zm.addr, align 1 # | %3 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = extractelement <1 x i8> %2, i64 0 # | %.splat # | ... # `---data was truncated (10240/24132) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055981bc8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055981bc890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055981bc8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c74a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c74aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c74a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c74a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055981bc21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055981bc21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055981bc06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055981b8b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055981b8b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c74a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c74a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c74a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055981b8b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c (332 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrh.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrh_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrh.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564ced1d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ced1d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ced1d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa98da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa98daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa98da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa98da31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ced168e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ced168c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ced14db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564cecdfd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564cecdfcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa98da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa98da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa98da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cecdfccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c (333 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/len.c (334 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/len.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vscale.i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 16 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 8 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 4 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlen_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call i64 @llvm.vscale.i64() # | %2 = mul nuw i64 %1, 2 # | ret i64 %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000564a7b9e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a7b9df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a7b9e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b89533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b8958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b89533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b8951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a7b977e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a7b977c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a7b95cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a7b60c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a7b60bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3b8951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b8951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b8951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a7b60bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/len.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c (335 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za16_mf8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 7) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdotb_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdott_lane_za32_mf8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32, , , , i32 immarg) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f8f16,+sme-f8f32" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x000055b2f172115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2f171e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2f172189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5135533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f513558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5135533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f513551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2f16b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2f16b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2f169bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2f134b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2f134add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f513551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f513551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f513551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2f134acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c (336 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmsb.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmsb.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmsb_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e3d218815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3d21850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3d218889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb749649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7496a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb749649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb749631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3d211de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e3d211dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e3d2102b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3d1db20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3d1db1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb749632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7496330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7496330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3d1db1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c (337 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintm.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintm_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintm.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056388748c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638874890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056388748c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a37249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a372a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a37249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a37231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563887421e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563887421c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563887406b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638870b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638870b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5a37232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a372330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a372330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638870b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c (338 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055739b33715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055739b3340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055739b33789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89be505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89be55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89be505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89be4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055739b2cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055739b2ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055739b2b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055739af610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055739af60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f89be4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89be4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89be4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055739af60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c (339 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558069cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558069ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558069cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc52ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc52eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc52ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc52ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555806962e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555806962c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555806947b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558065f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558065f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc52ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc52ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc52ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558065f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/load.c (340 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/load.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float64x2x2_t = type { [2 x <2 x double>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly64x2x2_t = type { [2 x <2 x i64>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float64x1x2_t = type { [2 x <1 x double>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly64x1x2_t = type { [2 x <1 x i64>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float64x2x3_t = type { [3 x <2 x double>] } # | %struct.mfloat8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly64x2x3_t = type { [3 x <2 x i64>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float64x1x3_t = type { [3 x <1 x double>] } # | %struct.mfloat8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly64x1x3_t = type { [3 x <1 x i64>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.float64x2x4_t = type { [4 x <2 x double>] } # | %struct.mfloat8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly64x2x4_t = type { [4 x <2 x i64>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.float64x1x4_t = type { [4 x <1 x double>] } # | %struct.mfloat8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly64x1x4_t = type { [4 x <1 x i64>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vld1q_f16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %0, align 2 # | store <8 x half> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %2, ptr %__ret, align 16 # | %3 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %3, ptr %tmp, align 16 # | %4 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vld1q_f32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x float>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %0, align 4 # | store <4 x float> %1, ptr %ref.tmp, align 16 # | %2 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %2, ptr %__ret, align 16 # | %3 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %3, ptr %tmp, align 16 # | %4 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vld1q_f64(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <2 x double>, ptr %0, align 8 # | store <2 x double> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %2, ptr %__ret, align 16 # | %3 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %3, ptr %tmp, align 16 # | %4 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_mf8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_p16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vld1q_p64(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load <2 x i64>, ptr %0, align 8 # | store <2 x i64> %1, ptr %ref.tmp, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %2, ptr %__ret, align 16 # | %3 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %3, ptr %tmp, align 16 # | %4 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vld1q_p8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %0, align 1 # | store <16 x i8> %1, ptr %ref.tmp, align 16 # | %2 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %2, ptr %__ret, align 16 # | %3 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %3, ptr %tmp, align 16 # | %4 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vld1q_s16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %0, align 2 # | store <8 x i16> %1, ptr %ref.tmp, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %2, ptr %__ret, align 16 # | %3 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %3, ptr %tmp, align 16 # | %4 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vld1q_s32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %__ret = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store ptr %a # | ... # `---data was truncated (10240/415795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x00005570dd47515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570dd4720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570dd47589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1248133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1248133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570dd40ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570dd40ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570dd3efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570dd09f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570dd09edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f124811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570dd09ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/load.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c (341 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxth.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxth.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxth.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxth.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexth_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/11908) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557e2a9fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557e2a9f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557e2a9fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27dd61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27dd6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27dd61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27dd603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e2a991e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557e2a991c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557e2a976b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557e2a6260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557e2a625dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f27dd604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27dd6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27dd6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e2a625cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c (342 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fscale.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svscale_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fscale.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svscale_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c (343 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmls.lane.nxv8bf16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx3( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_lane_bf16_idx7( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmls.lane.nxv8bf16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fb60a3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb60a3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb60a3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf12c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf12ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf12c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf12c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb609d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb609d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb609b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb606690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb60668dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf12c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf12c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf12c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb60668cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/recpe.c (344 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/recpe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrecpe_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frecpe.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frecpe.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005590a1d9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590a1d960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590a1d9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cb4e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cb4e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cb4e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cb4e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590a1d2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590a1d2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590a1d13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590a19c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005590a19c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6cb4e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cb4e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cb4e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590a19c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/recpe.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c (345 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_s64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u8( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_u64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f32( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_f64( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbl_bf16( %data, %indices) #0 { # | entry: # | %data.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %data, ptr %data.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %data.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.tbl.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbl.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptra # | ... # `---data was truncated (10240/10361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055afa036315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055afa03600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055afa036389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b4c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b4c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b4c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b4c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afa02f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055afa02f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055afa02ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af9ff8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af9ff8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b4c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b4c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b4c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af9ff8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c (346 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.smin.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmin_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.umin.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.umin.single.x # | ... # `---data was truncated (10240/142195) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005588776b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588776af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588776b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4441b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4441b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4441b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4441b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558877647e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558877647c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055887762cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588772dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588772dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4441b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4441b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4441b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588772dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c (347 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c (348 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p3 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u16_x2( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.x2.nxv8i16( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_u16_x2( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.lane.x2.nxv8i16( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.lane.x2.nxv8i16(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p3" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005558064bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558064b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558064bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88aa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88aa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88aa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88aa51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555806451e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555806451c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555806436b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558060e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558060e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f88aa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88aa51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88aa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558060e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c (349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e56077c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5607790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e56077c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20f1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20f178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20f1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20f171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e560711e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e560711c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5606f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5603a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5603a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f20f171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20f171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20f171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5603a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c (350 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.ad # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005559a911215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005559a910f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005559a911289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0309f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0309f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0309f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0309f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559a90a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005559a90a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005559a908cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005559a8d3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005559a8d3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0309f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0309f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0309f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559a8d3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c (351 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpgt.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpgt.nxv2i64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpgt.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphi.nxv16i8( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv8i16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphi.nxv4i32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphi.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmplt_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556de6ad915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556de6ad60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556de6ad989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2b4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2b40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2b4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2b4031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556de6a6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556de6a6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556de6a53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556de67030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556de6702dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc2b4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2b40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2b40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556de6702cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/andv.c (352 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/andv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.andv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.andv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.andv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.andv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svandv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.andv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svandv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.andv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svandv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.andv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svandv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.andv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x000055da6228315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da622800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da6228389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa40b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa40b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa40b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa40b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da62218e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da62218c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da621fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da61ead0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da61eacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa40b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa40b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa40b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da61eaccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/andv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c (353 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_f64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d8b0c7715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d8b0c740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d8b0c7789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0570a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0570aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0570a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0570a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8b0c0ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d8b0c0cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d8b0bf1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d8b08a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d8b08a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0570a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0570a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0570a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8b08a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c (354 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i32.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i32.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_s64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64(, , , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64base_u64( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv2i32.nxv2i64( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0(, , ptr, ) #4 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_s64offset_u64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load , ptr %data.addr, align 16 # | %4 = trunc %3 to # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.nxv2i32.p0( %4, %5, ptr %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1w_scatter_u64offset_s64( %pg, ptr noundef %base, %offsets, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c (355 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlal_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umla.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single_x1_s16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_uvmlsl_single_x1_u16(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umls.za64.single.vg4x1.nxv8i16(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_sumlall_single_x1_s8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %2, %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_usmlall_single_x1_u8(i32 noundef %slice_base, %zn, %zm) #0 { # | entry: # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load i32, ptr %slice_base.addr, align 4 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.usmla.za32.single.vg4x1.nxv16i8(i32 %0, %1, %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single_x2_s8(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | # | ... # `---data was truncated (10240/178306) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560c2dabd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c2daba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c2dabd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d13449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d134a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d13449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d13431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c2da52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c2da52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c2da37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c2d6e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c2d6e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d13432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d134330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d134330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2d6e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c (356 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uqadd.x.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqadd.x.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %.splatinsert = insertelement poison, i8 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv16i8( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %.splatinsert = insertelement poison, i16 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv8i16( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %.splatinsert = insertelement poison, i32 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv4i32( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqadd_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %.splatinsert = insertelement poison, i64 %1, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %2 = call @llvm.aarch64.sve.sqadd.x.nxv2i64( %0, %.splat) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_l # | ... # `---data was truncated (10240/13780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005635efb7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005635efb790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005635efb7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aafc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aafca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aafc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aafc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635efb11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005635efb11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005635efaf6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635ef7a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005635ef7a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9aafc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aafc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aafc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635ef7a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c (357 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.smmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smmla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_u32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.ummla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.ummla.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svusmmla_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usmmla.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usmmla.nxv4i32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559cd28e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559cd28e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559cd28e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e79133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e7918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e79133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e7911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cd287be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559cd287bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559cd2860b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559cd25100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559cd250fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2e7911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e7911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e7911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cd250fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c (358 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svpfalse_c() #0 { # | entry: # | ret target("aarch64.svcount") zeroinitializer # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055beaacc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055beaacbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055beaacc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac81b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac81b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac81b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac81b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055beaac56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055beaac56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055beaac3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055beaa8eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055beaa8eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fac81b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac81b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac81b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055beaa8eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c (359 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1uw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = zext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000557fd736215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557fd735f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557fd736289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f514f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f514f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f514f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f514f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fd72f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557fd72f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557fd72dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557fd6f8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557fd6f8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f514f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f514f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f514f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fd6f8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-shifts.c (360 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629706a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629706a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005629706a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f181a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f181a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f181a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f181a203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562970638e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562970638c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056297061db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629702cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629702ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f181a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f181a2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f181a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629702cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c (361 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_s64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.clasta.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u8( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.clasta.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u32( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_u64( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclasta_f16( %pg, %fallback, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %fallback.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %fallback, ptr %fallback.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %fallback.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.clasta.nxv8f16(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c (362 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.expand.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.expand.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.expand.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svexpand_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, al # | ... # `---data was truncated (10240/12168) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558ccbbf015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ccbbed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ccbbf089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72acb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72acb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72acb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72acaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ccbb85e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ccbb85c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ccbb6ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ccb81a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ccb819dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72acaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72acaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72acaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ccb819cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c (363 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_multi_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.za32.vg1x4.nxv8f16(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fdot.single.za32.vg1x2.nxv8f16(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_single_za32_vg1x4_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c (364 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqcvtn.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqcvtun.x2.nxv4i32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtun.x2.nxv4i32(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563986f6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563986f610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563986f6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9af1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9af1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9af1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9af1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563986ef9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563986ef9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563986edeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563986b8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563986b8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9af1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9af1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9af1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563986b8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c (365 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmls.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c (366 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalb_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalb.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalb.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalb_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalb( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562795dbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562795db90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562795dbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9cf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9cf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9cf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9cf031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562795d51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562795d51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562795d36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627959e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627959e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9cf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9cf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9cf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627959e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c (367 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv16i8(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8i16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4i32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 0, %0, i32 3) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti4.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005632f55dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632f55d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005632f55dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f8e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f8e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f8e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f8e631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632f5571e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005632f5571c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005632f5556b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632f52060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005632f5205dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f8e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f8e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f8e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632f5205cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c (368 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_u8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_mf8_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv16i8( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svzip_s16_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.zip.x4.nxv8i16(, , , ) #1 # | ... # `---data was truncated (10240/67329) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eb946b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb946ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb946b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8f8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8f858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8f8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8f851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb94646e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb94646c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb9462bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb942db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb942dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc8f851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8f851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8f851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb942dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c (369 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svadd_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c (370 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnt.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnt.nxv4f32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnt.nxv2f64( zeroi # | ... # `---data was truncated (10240/32102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564ebfb6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ebfb640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ebfb6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f131bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f131bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f131bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f131bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ebfafce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ebfafcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ebfae1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564ebf7910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564ebf790dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f131bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f131bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f131bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ebf790cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c (371 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s32( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s16( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_u8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_s8( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f64( %pg, %base, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %4 = call @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64( %3, %1, i64 %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1q_gather_u64base_offset_f32( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c (372 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_z( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_m( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_n_bf16_x( %pg, %op1, i16 noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fscale.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-bfscale" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c73849e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c73849b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c73849e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5ad049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5ad0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5ad049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5ad031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c738433e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c738433c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c738418b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7380c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c7380c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd5ad032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5ad0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5ad0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7380c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c (373 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udiv.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sdiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_u64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.udiv.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdiv_s32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call # | ... # `---data was truncated (10240/48703) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558ea678515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ea67820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ea678589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc214249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2142a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc214249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc214231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ea671ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ea671ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ea66ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ea63af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ea63aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc214232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2142330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2142330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ea63aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_div.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c (374 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = zext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-vector_type-params-returns.c (375 of 27911) ******************** TEST 'Clang :: CodeGen/arm-vector_type-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x half> @test_ret_v8f16(<8 x half> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x half> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x float> @test_ret_v4f32(<4 x float> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x float> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x double> @test_ret_v2f64(<2 x double> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x double> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x bfloat> @test_ret_v8bf16(<8 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x bfloat> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16s8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8s16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32s4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64s2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <16 x i8> @test_ret_v16u8(<16 x i8> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <16 x i8> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <8 x i16> @test_ret_v8u16(<8 x i16> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <8 x i16> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <4 x i32> @test_ret_v32u4(<4 x i32> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x i32> %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local noundef <2 x i64> @test_ret_v64u2(<2 x i64> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <2 x i64> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d55127015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d55126d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d55127089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f289bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f289bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f289bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f289bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d551205e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d551205c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5511eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d550e9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d550e99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f289bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f289bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f289bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d550e99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-vector_type-params-returns.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c (376 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 2 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 1 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , } %1, %tuple.coerce2, 2 # | store { , , } %2, ptr %tuple, align 16 # | %tuple1 = load { , , }, ptr %tuple, align 16 # | store { , , } %tuple1, ptr %tuple.addr, align 16 # | %3 = load { , , }, ptr %tuple.addr, align 16 # | %4 = extractvalue { , , } %3, 0 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget3_u64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2) #0 { # | entry: # | %tuple = alloca { , , }, align 16 # | %tuple.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue # | ... # `---data was truncated (10240/21007) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d918c0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d918c0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d918c0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5b3105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5b315c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5b3105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5b30ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d918ba2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d918ba2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d918b87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9188370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d918836dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd5b30eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5b30ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5b30ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d918836cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c (377 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c (378 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqinch.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqinch.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqinch.n32(i32 %0, i32 30, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqinch.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqinch_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqinch.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqinch_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqinch.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqinch.nxv8i16(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqinch.nxv8i16( %0, i32 2, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqinch_pat_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqinch.nxv8i16( %0, i32 3, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a9aca7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9aca780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9aca7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2038f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2038f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2038f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2038eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9aca10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9aca10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9ac9f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9ac6a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9ac6a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2038eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2038eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2038eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9ac6a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c (379 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_s32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_s64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u32base_u32offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrb_u64base_u64offset( %bases, %offsets) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %offsets.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %offsets.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrb.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000561f2829315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561f282900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561f2829389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f052dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f052dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f052dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f052dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f28228e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561f28228c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561f2820db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561f27ebd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561f27ebcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f052dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f052dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f052dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f27ebccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c (380 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629ee5c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629ee5be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005629ee5c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6abdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6abdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6abdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6abdb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629ee556e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005629ee556c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005629ee53bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629ee1eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629ee1eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6abdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6abdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6abdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629ee1eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c (381 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %vcvtz.i = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %2) # | store <4 x i16> %vcvtz.i, ptr %ref.tmp.i, align 8 # | %3 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %3, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %vcvtz.i = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2) # | store <8 x i16> %vcvtz.i, ptr %ref.tmp.i, align 16 # | %3 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %3, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056332802d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056332802a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056332802d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f043e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f043e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f043e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f043e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563327fc2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563327fc2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563327fa7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563327c570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563327c56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f043e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f043e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f043e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563327c56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/conversion-fullfp16.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c (382 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv16i8(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8i16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4i32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_s64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u8( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv16i8( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8i16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4i32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_u64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f16( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv8f16( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv8f16(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f32( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv4f32( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv4f32(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_lane_f64( %data, i64 noundef %index) #0 { # | entry: # | %data.addr = alloca , align 16 # | %index.addr = alloca i64, align 8 # | store %data, ptr %data.addr, align 16 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %data.addr, align 16 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = call @llvm.aarch64.sve.dupq.lane.nxv2f64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dupq.lane.nxv2f64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdupq_n_s8(i8 noundef %x0, i8 noundef %x1, i8 noundef %x2, i8 noundef %x3, i8 noundef %x4, i8 noundef %x5, i8 noundef %x6, i8 noundef %x7, i8 noundef %x8, i8 noundef %x9, i8 noundef %x10, i8 noundef %x11, i8 noundef %x12, i8 noundef %x13, i8 noundef %x14, i8 noundef %x15) #0 { # | entry: # | %x0.addr = alloca i8, align 1 # | %x1.addr = alloca i8, align 1 # | %x2.addr = alloca i8, align 1 # | %x3.addr = alloca i8, align 1 # | %x4.addr = alloca i8, align 1 # | %x5.addr = alloca i8, align 1 # | %x6.addr = alloca i8, align 1 # | %x7.addr = alloca i8, align 1 # | %x8.addr = alloca i8, align 1 # | %x9.addr = alloca i8, align 1 # | %x10.addr = alloca i8, align 1 # | %x11.addr = alloca i8, align 1 # | %x12.addr = alloca i8, align 1 # | %x13.addr = alloca i8, align 1 # | %x14.addr = alloca i8, align 1 # | %x15.addr = alloca i8, align 1 # | store i8 %x0, ptr %x0.addr, align 1 # | store i8 %x1, ptr %x1.addr, align 1 # | store i8 %x2, ptr %x2.addr, align 1 # | store i8 %x3, ptr %x3.addr, align 1 # | store i8 %x4, ptr %x4.addr, align 1 # | store i8 %x5, ptr %x5.addr, align 1 # | store i8 %x6, ptr %x6.addr, align 1 # | store i8 %x7, ptr %x7.addr, align 1 # | store i8 %x8, ptr %x8.addr, align 1 # | store i8 %x9, ptr %x9.addr, align 1 # | store i8 %x10, ptr %x10.addr, align 1 # | store i8 %x11, ptr %x11.addr, align 1 # | store i8 %x12, ptr %x12.addr, align 1 # | store i8 %x13, ptr %x13.addr, align 1 # | store i8 %x14, ptr %x14.addr, align 1 # | store i8 %x15, ptr %x15.addr, align 1 # | %0 = load i8, ptr %x0.addr, align 1 # | %1 = load i8, ptr %x1.addr, align 1 # | %2 = load i8, ptr %x2.addr, align 1 # | %3 = load i8, ptr %x3.addr, align 1 # | %4 = load i8, ptr %x4.addr, align 1 # | %5 = load i8, ptr %x5.addr, align 1 # | %6 = load i8, ptr %x6.addr, align 1 # | %7 = load i8, ptr %x7.addr, align 1 # | %8 = load i8, ptr %x8.addr, align 1 # | %9 = load i8, ptr %x9.addr, align 1 # | %10 = load i8, ptr %x10.addr, align 1 # | %11 = load i8, ptr %x11.addr, align 1 # | %12 = load i8, ptr %x12.addr, align 1 # | %13 = load i8, ptr # | ... # `---data was truncated (10240/42600) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563cd9cf515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563cd9cf20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563cd9cf589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17f4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17f498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17f4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17f491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cd9c8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563cd9c8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563cd9c6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563cd991f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563cd991edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f17f491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17f491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17f491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cd991ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c (383 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_s64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_u64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f32( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_f64( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_mf8( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_bf16( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c (384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648f4f5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648f4f5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648f4f5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb182a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb182aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb182a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb182a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648f4ef4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648f4ef4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648f4ed9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648f4b890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648f4b88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb182a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb182a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb182a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648f4b88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c (385 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s64( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s32( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s16( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_u8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, %4, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1q_scatter_u64base_offset_s8( %pg, %base, i64 noundef %offset, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca , align 16 # | %offset.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %base, ptr %base.addr, align 16 # | store i64 %offset, ptr %offset.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %base.addr, align 16 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64( %3, % # | ... # `---data was truncated (10240/93831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558dfd3e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dfd3e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dfd3e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fb3905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fb395c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fb3905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fb38ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dfd379e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dfd379c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dfd35eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dfd00e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dfd00ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3fb38eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fb38ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fb38ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dfd00dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c (386 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4i32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2i64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv4f32( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv2f64( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055aca84cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aca84cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aca84cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed50849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed50849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed50831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aca8464e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aca8464c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aca8449b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aca80f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aca80f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed50832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed508330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aca80f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c (387 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/176535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fe2e1e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557fe2e1b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557fe2e1e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cf0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cf038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cf0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cf031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fe2db3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557fe2db3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557fe2d98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557fe2a480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557fe2a47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9cf031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cf031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cf031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fe2a47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c (388 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558385b5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558385b4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558385b5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e5f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e5f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e5f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e5f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558385ae7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558385ae7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558385accb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055838577c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055838577bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8e5f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e5f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e5f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055838577bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c (389 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpge.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpge.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpge.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmphs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmphs.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmphs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpge_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, # | ... # `---data was truncated (10240/41923) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556bbe88115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556bbe87e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556bbe88189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f200fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f200faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f200fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f200fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bbe816e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556bbe816c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556bbe7fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556bbe4ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556bbe4aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f200fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f200fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f200fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bbe4aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c (390 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f64( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv2f64.nxv2f64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055692aaec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055692aae90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055692aaec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbe5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbe515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbe5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbe50ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055692aa81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055692aa81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055692aa66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055692a7160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055692a715dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbe50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbe50ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbe50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055692a715cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c (391 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0( %2, ptr %1) # | ret { , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , } @llvm.aarch64.sve.ld3.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svld3_f64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c (392 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_mf8_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_s64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_u64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_bf16_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f32_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_f64_mf8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = bitcast %0 t # | ... # `---data was truncated (10240/168193) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x000055a3ea3de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3ea3db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a3ea3de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3009133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f300918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3009133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f300911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ea373e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a3ea373c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a3ea358b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3ea0080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3ea007dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f300911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f300911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f300911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ea007cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c (393 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s16_s32_x4( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshr.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqrshr.x4.nxv4i32( %5, %6, %7, %8, i32 8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshr.x4.nxv4i32(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrshr_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqrshr.x4.nxv2i64( %5, %6, %7, %8, i32 16) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshr.x4.nxv2i64(, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/33461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e72be2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e72be290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e72be2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3abd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3abd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3abd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3abd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e72bdc1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e72bdc1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e72bda6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e72ba560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e72ba55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3abd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3abd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3abd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e72ba55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c (394 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv1i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_u32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_s32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4i32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1uwq.nxv4f32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uwq_vnum_f32( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1uwq.nxv4f32.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2i64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_u64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_s64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 -8 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2i64.p0( %2, ptr %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1udq.nxv2f64.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1udq_vnum_f64( %pred, ptr noundef %base) #0 { # | entry: # | %pred.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pred, ptr %pred.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pred.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv1i1( %0) # | %3 = getelementptr , ptr %1, i64 7 # | %4 = call @llvm.aarch64.sve.ld1udq.nxv2f64.p0( %2, ptr %3) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !" # | ... # `---data was truncated (10240/10573) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a8abedd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8abeda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8abedd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ca5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ca5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ca5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ca5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8abe72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8abe72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8abe57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8abb070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8abb06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ca5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ca5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ca5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8abb06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c (395 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c (396 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x bfloat>, align 16 # | %__p2.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_812 = alloca <4 x float>, align 16 # | %__s0_812 = alloca <4 x float>, align 16 # | %__s1_812 = alloca <8 x bfloat>, align 16 # | %__s2_812 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <4 x float>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp2 = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <8 x bfloat> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0_812, align 16 # | %1 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1_812, align 16 # | %2 = load <8 x bfloat>, ptr %b.addr, align 16 # | store <8 x bfloat> %2, ptr %__s2_812, align 16 # | %3 = load <4 x float>, ptr %__s0_812, align 16 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 16 # | %5 = load <4 x float>, ptr %__s2_812, align 16 # | store <4 x float> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 16 # | %8 = load <4 x float>, ptr %ref.tmp1, align 16 # | store <4 x float> %8, ptr %__ret, align 16 # | %9 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %9, ptr %tmp, align 16 # | %10 = load <4 x float>, ptr %tmp, align 16 # | store <4 x float> %10, ptr %ref.tmp, align 16 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <4 x float> %3, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 16 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 16 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %15, ptr %__ret.i, align 16 # | %16 = load <4 x float>, ptr %__ret.i, align 16 # | store <4 x float> %16, ptr %__ret_812, align 16 # | %17 = load <4 x float>, ptr %__ret_812, align 16 # | store <4 x float> %17, ptr %tmp2, align 16 # | %18 = load <4 x float>, ptr %tmp2, align 16 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, # | ... # `---data was truncated (10240/54685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005625aadcf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625aadcc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005625aadcf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8692049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86920a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8692049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8692031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625aad64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625aad64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625aad49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625aa9f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625aa9f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8692032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86920330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86920330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625aa9f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/dup.c (397 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv16i8(i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8i16(i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4i32(i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2i64(i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u8(i8 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %1 = call @llvm.aarch64.sve.dup.x.nxv16i8(i8 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u16(i16 noundef %op) #0 { # | entry: # | %op.addr = alloca i16, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load i16, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8i16(i16 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4i32(i32 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2i64(i64 %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f16(half noundef %op) #0 { # | entry: # | %op.addr = alloca half, align 2 # | store half %op, ptr %op.addr, align 2 # | %0 = load half, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8f16(half %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8f16(half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f32(float noundef %op) #0 { # | entry: # | %op.addr = alloca float, align 4 # | store float %op, ptr %op.addr, align 4 # | %0 = load float, ptr %op.addr, align 4 # | %1 = call @llvm.aarch64.sve.dup.x.nxv4f32(float %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv4f32(float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_f64(double noundef %op) #0 { # | entry: # | %op.addr = alloca double, align 8 # | store double %op, ptr %op.addr, align 8 # | %0 = load double, ptr %op.addr, align 8 # | %1 = call @llvm.aarch64.sve.dup.x.nxv2f64(double %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv2f64(double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b8(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | ret %.splat # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b16(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b32(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_b64(i1 noundef %op) #0 { # | entry: # | %op.addr = alloca i8, align 1 # | %storedv = zext i1 %op to i8 # | store i8 %storedv, ptr %op.addr, align 1 # | %0 = load i8, ptr %op.addr, align 1 # | %loadedv = icmp ne i8 %0, 0 # | %.splatinsert = insertelement poison, i1 %loadedv, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %.splat) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_bf16(bfloat noundef %op) #0 { # | entry: # | %op.addr = alloca bfloat, align 2 # | store bfloat %op, ptr %op.addr, align 2 # | %0 = load bfloat, ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.x.nxv8bf16(bfloat) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s8_z( %pg, i8 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i8, align 1 # | store %pg, ptr %pg.addr, align 2 # | store i8 %op, ptr %op.addr, align 1 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i8, ptr %op.addr, align 1 # | %2 = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.nxv16i8(, , i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_n_s16_z( %pg, i16 noundef %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca i16, align 2 # | store %pg, ptr %pg.addr, align 2 # | store i16 %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load i16, ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/dup.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c (398 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.trn2.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564a4a95515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a4a9520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a4a95589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa377f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa377f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa377f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa377f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a4a8eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a4a8eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a4a8cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a4a57f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a4a57edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa377f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa377f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa377f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a4a57ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c (399 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv16i8(, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8i16(, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4i32(, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_s64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u8( %op1, i8 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store i8 %op2, ptr %op2.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = call @llvm.aarch64.sve.insr.nxv16i8( %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u16( %op1, i16 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store i16 %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8i16( %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u32( %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i32, align 4 # | store %op1, ptr %op1.addr, align 16 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4i32( %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_u64( %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 16 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f16( %op1, half noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca half, align 2 # | store %op1, ptr %op1.addr, align 16 # | store half %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8f16( %0, half %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8f16(, half) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f32( %op1, float noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.insr.nxv4f32( %0, float %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv4f32(, float) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_f64( %op1, double noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load double, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.insr.nxv2f64( %0, double %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv2f64(, double) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svinsr_n_bf16( %op1, bfloat noundef %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.insr.nxv8bf16( %0, bfloat %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.insr.nxv8bf16(, bfloat) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056423a1c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056423a1c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056423a1c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f552e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f552e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f552e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f552e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056423a15be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056423a15bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056423a140b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564239df00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564239defdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f552e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f552e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f552e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564239defcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c (400 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c (401 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revb.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revb.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.revb.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevb_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/16804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f8ccd2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8ccd200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f8ccd2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e23849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e238a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e23849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e23831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8cccb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f8cccb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f8ccc9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f8cc94d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f8cc94cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e23832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e238330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e238330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8cc94ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (402 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , } @test_svundef2_b() local_unnamed_addr #0 { # | entry: # | ret { , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_b() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559abbb7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559abbb730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559abbb7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc203849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2038a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc203849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc203831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559abbb0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559abbb0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559abbaf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559abb7a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559abb79fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc203832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2038330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2038330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559abb79fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c (403 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @l # | ... # `---data was truncated (10240/62760) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e557dd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e557dcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e557dd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1dd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1dd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1dd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1dd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e557d65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e557d65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e557d4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5579fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5579f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1dd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1dd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1dd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5579f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-vld.c (404 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vld.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vld1_f16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x3_t @test_vld1_f16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float16x4x3_t, ptr %retval, align 8 # | ret %struct.float16x4x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x4_t @test_vld1_f16_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float16x4x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %0) # | store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float16x4x4_t, ptr %retval, align 8 # | ret %struct.float16x4x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x2_t @test_vld1_f32_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.float32x2x2_t, ptr %retval, align 8 # | ret %struct.float32x2x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x3_t @test_vld1_f32_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x3_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 24, i1 false) # | %1 = load %struct.float32x2x3_t, ptr %retval, align 8 # | ret %struct.float32x2x3_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float32x2x4_t @test_vld1_f32_x4(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.float32x2x4_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.float32x2x4_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %0) # | store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 32, i1 false) # | %1 = load %struct.float32x2x4_t, ptr %retval, align 8 # | ret %struct.float32x2x4_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x2_t @test_vld1_p16_x2(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x2_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16x4x2_t, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %vld1xN = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %0) # | store { <4 x i16>, <4 x i16> } %vld1xN, ptr %__ret, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %retval, ptr align 8 %__ret, i64 16, i1 false) # | %1 = load %struct.poly16x4x2_t, ptr %retval, align 8 # | ret %struct.poly16x4x2_t %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.poly16x4x3_t @test_vld1_p16_x3(ptr noundef %a) #0 { # | entry: # | %retval = alloca %struct.poly16x4x3_t, align 8 # | %a.addr = alloca ptr, align 8 # | %__ret = alloca %struct.poly16 # | ... # `---data was truncated (10240/109928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585239c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585239c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585239c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5832e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5832ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5832e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5832e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055852395ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055852395cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558523941b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585235f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585235f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5832e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5832e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5832e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585235f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vld.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c (405 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c (406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloc # | ... # `---data was truncated (10240/71123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055729683015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055729682d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055729683089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f64649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f646a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f64649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f64631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572967c5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005572967c5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005572967aab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055729645a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557296459dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f64632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f646330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f646330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557296459cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c (407 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a2de5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a2de570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a2de5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfee61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfee6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfee61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfee603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a2ddefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a2ddefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a2ddd4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a2da840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a2da83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfee604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfee6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfee6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a2da83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c (408 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnt1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ldnt1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnt1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnt1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %b # | ... # `---data was truncated (10240/22231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f15c4df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f15c4dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f15c4df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa178649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1786a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa178649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa178631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f15c474e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f15c474c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f15c459b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f15c1090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f15c108dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa178632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1786330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1786330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f15c108cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (409 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcreate2_b( %x0, %x1) #0 { # | entry: # | %x0.addr = alloca , align 2 # | %x1.addr = alloca , align 2 # | store %x0, ptr %x0.addr, align 2 # | store %x1, ptr %x1.addr, align 2 # | %0 = load , ptr %x0.addr, align 2 # | %1 = load , ptr %x1.addr, align 2 # | %2 = insertvalue { , } poison, %0, 0 # | %3 = insertvalue { , } %2, %1, 1 # | ret { , } %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555a1dd9515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a1dd920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a1dd9589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc0e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc0e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc0e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc0e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a1dd2ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a1dd2ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a1dd0fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a1d9bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a1d9bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efc0e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc0e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc0e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a1d9becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-cde-vfp.c (410 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-vfp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1_u32() #0 { # | entry: # | %0 = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 11) # | %1 = bitcast float %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1.f32(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx1a_u32(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx1a.f32(i32 1, float %1, i32 12) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx1a.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2_u32(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = call float @llvm.arm.cde.vcx2.f32(i32 0, float %1, i32 21) # | %3 = bitcast float %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2.f32(i32 immarg, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx2a_u32(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx2a.f32(i32 0, float %1, float %3, i32 22) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx2a.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3_u32(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %m.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = call float @llvm.arm.cde.vcx3.f32(i32 1, float %1, float %3, i32 3) # | %5 = bitcast float %4 to i32 # | ret i32 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3.f32(i32 immarg, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vcx3a_u32(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = bitcast i32 %0 to float # | %2 = load i32, ptr %n.addr, align 4 # | %3 = bitcast i32 %2 to float # | %4 = load i32, ptr %m.addr, align 4 # | %5 = bitcast i32 %4 to float # | %6 = call float @llvm.arm.cde.vcx3a.f32(i32 0, float %1, float %3, float %5, i32 5) # | %7 = bitcast float %6 to i32 # | ret i32 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.cde.vcx3a.f32(i32 immarg, float, float, float, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1d_u64() #0 { # | entry: # | %0 = call double @llvm.arm.cde.vcx1.f64(i32 0, i32 11) # | %1 = bitcast double %0 to i64 # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1.f64(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx1da_u64(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx1a.f64(i32 1, double %1, i32 12) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx1a.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2d_u64(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = call double @llvm.arm.cde.vcx2.f64(i32 0, double %1, i32 21) # | %3 = bitcast double %2 to i64 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2.f64(i32 immarg, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx2da_u64(i64 noundef %acc, i64 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx2a.f64(i32 0, double %1, double %3, i32 22) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx2a.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3d_u64(i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %n.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %m.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = call double @llvm.arm.cde.vcx3.f64(i32 1, double %1, double %3, i32 3) # | %5 = bitcast double %4 to i64 # | ret i64 %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3.f64(i32 immarg, double, double, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vcx3da_u64(i64 noundef %acc, i64 noundef %n, i64 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i64, align 8 # | %m.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | store i64 %n, ptr %n.addr, align 8 # | store i64 %m, ptr %m.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = bitcast i64 %0 to double # | %2 = load i64, ptr %n.addr, align 8 # | %3 = bitcast i64 %2 to double # | %4 = load i64, ptr %m.addr, align 8 # | %5 = bitcast i64 %4 to double # | %6 = call double @llvm.arm.cde.vcx3a.f64(i32 0, double %1, double %3, double %5, i32 5) # | %7 = bitcast double %6 to i64 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.arm.cde.vcx3a.f64(i32 immarg, double, double, double, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560173e5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560173e560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560173e5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4351a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4351aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4351a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4351a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560173deee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560173deec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560173dd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560173a830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560173a82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4351a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4351a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4351a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560173a82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vfp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c (411 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005588b9f7715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588b9f740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588b9f7789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb18c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb18c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb18c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb18c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588b9f0ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588b9f0cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588b9ef1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588b9ba10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588b9ba0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb18c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb18c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb18c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588b9ba0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c (412 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i16.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i16.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1h_scatter_u32base_s32( %pg, %bases, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = load , ptr %data.addr, align 16 # | %3 = trunc %2 to # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32( %3, %4, %1, i64 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.aarch64.sve.st1.scatter.scalar.offset.nxv4i16.nxv4i32(, , , i64) # # | ... # `---data was truncated (10240/43213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000556ad4dc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ad4dc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ad4dc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87e9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87e998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87e9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87e991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ad4d59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ad4d59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ad4d3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ad49ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ad49eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f87e991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87e991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87e991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ad49edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c (413 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/424041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587fe50f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587fe50c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587fe50f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e27733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e2778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e27733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e2771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587fe4a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587fe4a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587fe489b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587fe1390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587fe138dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e2771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e2771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e2771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587fe138cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/minv.c (414 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.sminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.sminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.sminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.sminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.sminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.sminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svminv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.uminv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.uminv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svminv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.uminv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.uminv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svminv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.uminv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uminv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svminv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uminv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uminv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005625dca6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625dca6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005625dca6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98f6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98f615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98f6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98f60ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625dca02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625dca02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625dc9e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625dc6970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625dc696dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98f60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98f60ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98f60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625dc696cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c (415 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c (416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056152400d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056152400a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056152400d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f993181bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99318725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f993181ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9931803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561523fa2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561523fa2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561523f87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561523c370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561523c36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9931804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99318050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99318050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561523c36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c (417 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv8i16(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv4i32(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cmpne.nxv2i64(, , ) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.cmpne.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv8i16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv4i32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmpne_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.cmpne.nxv2i64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_r # | ... # `---data was truncated (10240/34127) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005625a824015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625a823d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005625a824089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f183d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f183d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183d0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625a81d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625a81d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625a81bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625a7e6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625a7e69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f183d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625a7e69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/intrinsics.c (418 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmv_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %vmaxnmv_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %1) # | store float %vmaxnmv_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmaxnmvq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f32.i = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %1) # | store float %vmaxnmvq_f32.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmaxnmvq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca double, align 8 # | %ref.tmp.i = alloca double, align 8 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %vmaxnmvq_f64.i = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %1) # | store double %vmaxnmvq_f64.i, ptr %ref.tmp.i, align 8 # | %2 = load double, ptr %ref.tmp.i, align 8 # | store double %2, ptr %__ret.i, align 8 # | %3 = load double, ptr %__ret.i, align 8 # | ret double %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrunh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrunh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrunh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshruns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshruns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshruns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_s16 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_s16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_s32 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_s32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vqrshrnh_n_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca i8, align 1 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = insertelement <8 x i16> poison, i16 %1, i64 0 # | %vqrshrnh_n_u16 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %2, i32 8) # | %3 = extractelement <8 x i8> %vqrshrnh_n_u16, i64 0 # | store i8 %3, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret, align 1 # | %5 = load i8, ptr %__ret, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vqrshrns_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca i16, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = insertelement <4 x i32> poison, i32 %1, i64 0 # | %vqrshrns_n_u32 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %2, i32 16) # | %3 = extractelement <4 x i16> %vqrshrns_n_u32, i64 0 # | store i16 %3, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret, align 2 # | %5 = load i16, ptr %__ret, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqrshrun_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <8 x i16> # | %vqrshrun_n1 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %vqrshrun_n, i32 3) # | store <8 x i8> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrshrun_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %__s0, align 16 # | %vqrshrun_n = bitcast <16 x i8> %1 to <4 x i32> # | %vqrshrun_n1 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %vqrshrun_n, i32 9) # | store <4 x i16> %vqrshrun_n1, ptr %ref.tmp, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %2, ptr %__ret, align 8 # | %3 = load <4 x i16>, p # | ... # `---data was truncated (10240/770739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d94982e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d94982b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d94982e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c8a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c8a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c8a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c8a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9497c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9497c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9497a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9494580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d949457dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c8a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c8a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c8a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d949457cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c (419 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %vs2, bflo # | ... # `---data was truncated (10240/43940) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560b8db815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560b8db50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560b8db889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00fca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00fca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00fca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00fca03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560b8d4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560b8d4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560b8d32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560b89e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560b89e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f00fca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00fca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00fca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560b89e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-dot-product.c (420 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-dot-product.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <16 x i8> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | %2 = load <16 x i8>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x i32> # | %vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %vdot.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vdot1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_831 = alloca <2 x i32>, align 8 # | %__s0_831 = alloca <2 x i32>, align 8 # | %__s1_831 = alloca <8 x i8>, align 8 # | %__s2_831 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_831, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1_831, align 8 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_831, align 8 # | %3 = load <2 x i32>, ptr %__s0_831, align 8 # | %4 = load <8 x i8>, ptr %__s1_831, align 8 # | %5 = load <2 x i32>, ptr %__s2_831, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %vdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_831, align 8 # | %17 = load <2 x i32>, ptr %__ret_831, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %c.addr = alloca <8 x i8>, align 8 # | %__ret_827 = alloca <4 x i32>, align 16 # | %__s0_827 = alloca <4 x i32>, align 16 # | %__s1_827 = alloca <16 x i8>, align 16 # | %__s2_827 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp2 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | store <8 x i8> %c, ptr %c.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0_827, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1_827, align 16 # | %2 = load <8 x i8>, ptr %c.addr, align 8 # | store <8 x i8> %2, ptr %__s2_827, align 8 # | %3 = load <4 x i32>, ptr %__s0_827, align 16 # | %4 = load <16 x i8>, ptr %__s1_827, align 16 # | %5 = load <2 x i32>, ptr %__s2_827, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__ # | ... # `---data was truncated (10240/29862) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x000055c22172015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c22171d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c22172089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e4d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e4d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e4d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e4d803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2216b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2216b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c22169ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c22134a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c221349dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e4d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e4d8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e4d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c221349cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-dot-product.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c (421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056188d25415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056188d2510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056188d25489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7c011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056188d1e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056188d1e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056188d1ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056188ce7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056188ce7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc7c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7c011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056188ce7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c (422 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8dot2 -target-feature +fp8dot4 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <4 x half>, align 8 # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <8 x i8> %4 to <4 x half> # | %fdot21.i = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.v4f16.v8i8(<4 x half> %fdot2.i, <8 x i8> %5, <8 x i8> %6) # | store <4 x half> %fdot21.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_f16(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2.i = bitcast <16 x i8> %4 to <8 x half> # | %fdot21.i = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.v8f16.v16i8(<8 x half> %fdot2.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fdot21.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_lane_f16(<4 x half> noundef %vd, <8 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %8, i32 3) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %9 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %9, ptr %__ret, align 8 # | %10 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %10, ptr %tmp, align 8 # | %11 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8>, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half>, <8 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdot_laneq_f16(<4 x half> noundef %vd, <8 x i8> %vn, <16 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <4 x half>, align 8 # | %vn.addr = alloca <8 x i8>, align 8 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %__s2 = alloca <16 x i8>, align 16 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %vd, ptr %vd.addr, align 8 # | store <8 x i8> %vn, ptr %vn.addr, align 8 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <4 x half>, ptr %vd.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %vn.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | store <16 x i8> %2, ptr %__s2, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <8 x i8>, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s1, align 8 # | %6 = load <16 x i8>, ptr %__s2, align 16 # | %7 = load i64, ptr %__s4, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <8 x i8> %4 to <4 x half> # | %fdot2_lane1 = call <4 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v4f16.v8i8(<4 x half> %fdot2_lane, <8 x i8> %5, <16 x i8> %6, i32 7) # | store <4 x half> %fdot2_lane1, ptr %ref.tmp, align 8 # | %8 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %8, ptr %__ret, align 8 # | %9 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %9, ptr %tmp, align 8 # | %10 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_lane_f16(<8 x half> noundef %vd, <16 x i8> %vn, <8 x i8> %vm, i64 noundef %fpmr) #0 { # | entry: # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <8 x i8>, align 8 # | %fpmr.addr = alloca i64, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %__s2 = alloca <8 x i8>, align 8 # | %__s4 = alloca i64, align 8 # | %ref.tmp = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <8 x i8> %vm, ptr %vm.addr, align 8 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <8 x i8>, ptr %vm.addr, align 8 # | store <8 x i8> %2, ptr %__s2, align 8 # | %3 = load i64, ptr %fpmr.addr, align 8 # | store i64 %3, ptr %__s4, align 8 # | %4 = load <16 x i8>, ptr %__s0, align 16 # | %5 = load <16 x i8>, ptr %__s1, align 16 # | %6 = load <8 x i8>, ptr %__s2, align 8 # | %7 = load i64, ptr %__s4, align 8 # | %8 = call <16 x i8> @llvm.vector.insert.v16i8.v8i8(<16 x i8> poison, <8 x i8> %6, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fdot2_lane = bitcast <16 x i8> %4 to <8 x half> # | %fdot2_lane1 = call <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half> %fdot2_lane, <16 x i8> %5, <16 x i8> %8, i32 3) # | store <8 x half> %fdot2_lane1, ptr %ref.tmp, align 16 # | %9 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare <8 x half> @llvm.aarch64.neon.fp8.fdot2.lane.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdotq_laneq_f16(<8 x half> noundef %vd, <16 x i8> %vn, < # | ... # `---data was truncated (10240/24508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x000056363779415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005636377910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056363779489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6592d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6592d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6592d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6592d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563637729e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563637729c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056363770eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636373be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005636373bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6592d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6592d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6592d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636373bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c (423 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount"), , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_u8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_mf8_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svsel_s16_x2(target("aarch64.svcount") %pn, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %pn.addr = alloca target("aarch64.svcount"), align 2 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store target("aarch64.svcount") %pn, ptr %pn.addr, align 2 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load target("aarch64.svcount"), ptr %pn.addr, align 2 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | %11 = call { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %4, %6, %7, %9, %10) # | ret { , } %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount"), , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c (424 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | # | ... # `---data was truncated (10240/17236) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c797ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c797b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c797ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1b7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1b775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1b7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1b76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c7974fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c7974fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c79734b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c793e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c793e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1b76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1b76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1b76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c793e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c (425 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrinta_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frinta.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frinta.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrinta_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frinta.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintam_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintm.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.frintm.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svfrintm_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32( %5, %6, %7, %8) # | ret { , , , } %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.frintm.x4.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svfrintn_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.frintn.x2.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn me # | ... # `---data was truncated (10240/17932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005607c677815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005607c67750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005607c677889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43d6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43d658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43d6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43d651b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607c670de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607c670dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607c66f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607c63a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607c63a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f43d651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43d651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43d651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607c63a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c (426 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_bf16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmla.u.nxv8bf16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_m( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_z( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fmla.nxv8bf16( %4, %5, %2, %.splat) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmla_n_bf16_x( %pg, %op1, %op2, bfloat noundef %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store bfloat %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load bfloat, ptr %op3.addr, align 2 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %3, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmla.u.nxv8bf16( %4, %1, %2, %.splat) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055a3fc14e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3fc14b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a3fc14e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22f8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22f8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22f8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22f8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3fc0e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a3fc0e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a3fc0c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3fbd780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3fbd77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f22f8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22f8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22f8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3fbd77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c (427 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +faminmax -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv8f16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f32_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv4f32( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv4f32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamax_f64_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famax.x2.nxv2f64( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famax.x2.nxv2f64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svamin_f16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sme.famin.x2.nxv8f16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sme.famin.x2.nxv8f16(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/X86/avx-cmp-builtins.c (428 of 27911) ******************** TEST 'Clang :: CodeGen/X86/avx-cmp-builtins.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -flax-vector-conversions=none -ffreestanding /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c -triple=x86_64-- -target-feature +avx -disable-O0-optnone -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmp_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 13) # | ret <2 x double> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmp_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 13) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpgt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 1) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 2) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpngt_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 5) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_cmpnge_ss(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <4 x float>, align 16 # | %__b.addr.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__a.addr.i, align 16 # | store <4 x float> %1, ptr %__b.addr.i, align 16 # | %2 = load <4 x float>, ptr %__a.addr.i, align 16 # | %3 = load <4 x float>, ptr %__b.addr.i, align 16 # | %4 = load <4 x float>, ptr %__a.addr.i, align 16 # | %5 = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %3, <4 x float> %4, i8 6) # | %shuffle.i = shufflevector <4 x float> %2, <4 x float> %5, <4 x i32> # | ret <4 x float> %shuffle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpgt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 1) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 2) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpngt_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__a.addr.i, align 16 # | store <2 x double> %1, ptr %__b.addr.i, align 16 # | %2 = load <2 x double>, ptr %__b.addr.i, align 16 # | %3 = load <2 x double>, ptr %__a.addr.i, align 16 # | %4 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %3, i8 5) # | store <2 x double> %4, ptr %__c.i, align 16 # | %5 = load <2 x double>, ptr %__c.i, align 16 # | %vecext.i = extractelement <2 x double> %5, i32 0 # | %vecinit.i = insertelement <2 x double> poison, double %vecext.i, i32 0 # | %6 = load <2 x double>, ptr %__a.addr.i, align 16 # | %vecext1.i = extractelement <2 x double> %6, i32 1 # | %vecinit2.i = insertelement <2 x double> %vecinit.i, double %vecext1.i, i32 1 # | store <2 x double> %vecinit2.i, ptr %.compoundliteral.i, align 16 # | %7 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_cmpnge_sd(<2 x double> noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %__a.addr.i = alloca <2 x double>, align 16 # | %__b.addr.i = alloca <2 x double>, align 16 # | %__c.i = alloca <2 x double>, align 16 # | %.compoundlit # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a512dfa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a512df70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a512dfa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8455a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8455a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8455a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8455a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a512d8fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a512d8fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a512d74b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a512a240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a512a23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8455a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8455a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8455a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a512a23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/avx-cmp-builtins.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c (429 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fscale.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv2f64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fscale.nxv4f32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svscale_f64_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbo # | ... # `---data was truncated (10240/21216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c6c839b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6c83980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6c839b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8799b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8799b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8799b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8799b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6c8330e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c6c8330c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c6c8315b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6c7fc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c6c7fc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8799b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8799b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8799b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6c7fc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orv.c (430 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.orv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.orv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.orv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.orv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svorv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.orv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svorv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.orv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svorv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.orv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svorv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.orv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000056199fd4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056199fd490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056199fd4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc23e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc23e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc23e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc23e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056199fce1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056199fce1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056199fcc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056199f9760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056199f975dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc23e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc23e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc23e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056199f975cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c (431 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.splice.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsplice_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.splice.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.splice.nxv8f16(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c (432 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.ver.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_u8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_s8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za8_mf8_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_hor_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.hor.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_u8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_s8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svread_ver_za8_mf8_vg4(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , , , } @llvm.aarch64.sme.read.ver.vg4.nxv16i8(i32 0, i32 %0) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_bf16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8bf16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_f16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: read) # | declare { , } @llvm.aarch64.sme.read.hor.vg2.nxv8f16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_hor_za16_s16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.read.hor.vg2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svread_ver_za16_u16_vg2(i32 noundef %base) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = call { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c (433 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d38acc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d38acc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d38acc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f5f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f5f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f5f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f5f2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d38ac5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d38ac5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d38ac3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d38a8ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d38a8eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f5f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f5f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f5f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d38a8eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c (434 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmad.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmad.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmad_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmla.u.nxv8f16( %4, %3, %2, %1) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000560fbfef015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560fbfeed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560fbfef089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29db333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29db38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29db333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29db31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fbfe85e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560fbfe85c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560fbfe6ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560fbfb1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560fbfb19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f29db31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29db31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29db31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fbfb19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c (435 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556094f6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556094f630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556094f6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbea1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbea198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbea1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbea191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556094efbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556094efbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556094ee0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556094b900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556094b8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbea191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbea191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbea191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556094b8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c (436 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u8( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8i16( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4i32( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2i64( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b8( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.vector.reverse.nxv16i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv16i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b16( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b32( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_b64( %op) #0 { # | entry: # | %op.addr = alloca , align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %op.addr, align 2 # | %1 = call @llvm.aarch64.sve.rev.b64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rev.b64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrev_bf16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.vector.reverse.nxv8bf16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.reverse.nxv8bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c326bd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c326bd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c326bd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc416b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc416b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc416b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc416b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c326b6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c326b6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c326b4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c3267ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c3267fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc416b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc416b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc416b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3267fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c (437 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme2 -target-feature +sme -target-feature +sme-lutv2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u8_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s8_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s16_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u32_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s32_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_u64_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_s64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f16_2( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_bf16_3( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, %0, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f32_0( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, %0, i32 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_lane_zt_f64_1( %v) #0 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, %0, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: readwrite) # | declare void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv16i8(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s8( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv8i16(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s16( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv4i32(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s32( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_u64( %v) #2 { # | entry: # | %v.addr = alloca , align 16 # | store %v, ptr %v.addr, align 16 # | %0 = load , ptr %v.addr, align 16 # | call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, %0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.write.zt.nxv2i64(i32 immarg, ) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_write_zt_s64( %v) #2 { # | entry: # | % # | ... # `---data was truncated (10240/13584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556c9d72e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c9d72b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c9d72e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a3ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a3ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a3ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a3ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c9d6c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c9d6c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c9d6a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c9d3580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c9d357dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6a3ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a3ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a3ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c9d357cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c (438 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvtn.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtn.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvtn.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvtn.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u8_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_u16_u64_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.uqcvtn.x4.nxv2i64( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_qcvtn_s8_s32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = call @llvm.aarch64.sve.sqcvtn.x4.nxv4i32( %5, %6, %7, %8) # | ret %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_loc # | ... # `---data was truncated (10240/17734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556f86a5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556f86a520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556f86a5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0fef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0fef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0fef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0fef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f869eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556f869eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556f869cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556f8667f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556f8667edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0fef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0fef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0fef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f8667ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c (439 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b7f91a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558b7f9170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558b7f91a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92c1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92c10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92c1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92c1031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b7f8afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558b7f8afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558b7f894b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558b7f5440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558b7f543dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f92c1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92c10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92c10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b7f543cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c (440 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_s64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.udot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_s64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.sdot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u32( %op1, %op2, i8 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i8, align 1 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i8 %op3, ptr %op3.addr, align 1 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i8, ptr %op3.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv4i32( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_n_u64( %op1, %op2, i16 noundef %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca i16, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store i16 %op3, ptr %op3.addr, align 2 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load i16, ptr %op3.addr, align 2 # | %.splatinsert = insertelement poison, i16 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.udot.nxv2i64( %0, %1, %.splat) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.sdot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sdot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdot_lane_s32_1( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = # | ... # `---data was truncated (10240/15126) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005568c9d3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568c9d300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005568c9d3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0983533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f098358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0983533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f098351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568c9cc8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005568c9cc8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005568c9cadb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005568c995d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005568c995cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f098351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f098351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f098351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568c995ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c (441 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 15) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8i16( %0, i32 7) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 2) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4i32( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2i64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8f16( %0, i32 4) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8f16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv4f32( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv4f32(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_f64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv2f64( %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv2f64(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv8bf16( %0, i32 3) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.dup.laneq.nxv8bf16(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svdup_laneq_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.dup.laneq.nxv16i8( %0, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564c1c30815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c1c3050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c1c30889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41a1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41a1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41a1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41a1aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c1c29de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c1c29dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c1c282b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c1bf320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c1bf31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41a1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41a1aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41a1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c1bf31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c (442 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frinti.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frinti.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrinti_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frinti.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f2d1bd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f2d1bd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f2d1bd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cbc933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cbc98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cbc933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cbc91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2d1b6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f2d1b6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f2d1b4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f2d17ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f2d17fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6cbc91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cbc91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cbc91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2d17fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c (443 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mls.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mls.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmls_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.mls.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c (444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset # | ... # `---data was truncated (10240/287213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b05466215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b05465f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b05466289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f26e0d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26e0d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f26e0d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f26e0d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0545f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b0545f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b0545dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b05428c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b05428bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f26e0d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26e0d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26e0d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b05428bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c (445 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c7b9f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c7b9f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c7b9f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cbf905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cbf95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cbf905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cbf8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c7b98ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c7b98ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c7b973b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c7b6230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c7b622dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7cbf8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cbf8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cbf8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c7b622cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c (446 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacge_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563d3048315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d304800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d3048389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9411533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f941158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9411533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f941151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d30418e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d30418c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d303fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d300ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d300acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f941151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f941151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f941151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d300accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c (447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055991c2b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055991c2b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055991c2b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe19f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe19f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe19f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe19f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055991c24ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055991c24cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055991c231b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055991bee10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055991bee0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe19f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe19f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe19f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055991bee0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c (448 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c (449 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.fcvt.x2.nxv4f32( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvt.x2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.bfcvt.x2( %3, %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfcvt.x2(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_f32_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_u32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svcvt_s32_f32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcvt_f32_u32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, p # | ... # `---data was truncated (10240/39207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e1a3a8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e1a3a880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e1a3a8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1130933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f113098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1130933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f113091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1a3a20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e1a3a20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1a3a05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1a36b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1a36b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f113091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f113091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f113091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1a36b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c (450 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x2.nxv4f32(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { , , , } %6, %zm.coerce3, 3 # | store { , , , } %7, ptr %zm, align 16 # | %zm2 = load { , , , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store { , , , } %zm2, ptr %zm.addr, align 16 # | %8 = load i32, ptr %slice_base.addr, align 4 # | %9 = load { , , , }, ptr %zn.addr, align 16 # | %10 = extractvalue { , , , } %9, 0 # | %11 = extractvalue { , , , } %9, 1 # | %12 = extractvalue { , , , } %9, 2 # | %13 = extractvalue { , , , } %9, 3 # | %14 = load { , , , }, ptr %zm.addr, align 16 # | %15 = extractvalue { , , , } %14, 0 # | %16 = extractvalue { , , , } %14, 1 # | %17 = extractvalue { , , , } %14, 2 # | %18 = extractvalue { , , , } %14, 3 # | call void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32 %8, %10, %11, %12, %13, %15, %16, %17, %18) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.vg1x4.nxv4f32(i32, , , , , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single2_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmla.single.vg1x2.nxv4f32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla_single4_f32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c (451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c (452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = # | ... # `---data was truncated (10240/124514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d5273615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d527330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d5273689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc207c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc207ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc207c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc207c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d526cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d526cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d526b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d523600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d5235fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc207c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc207c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc207c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d5235fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c (453 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c (454 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = extractvalue { , , , } %4, 2 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_u16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.a # | ... # `---data was truncated (10240/28771) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f7e148115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7e147e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f7e148189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ac1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ac155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ac1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ac14ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7e1416e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f7e1416c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f7e13fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f7e10ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f7e10aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ac14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ac14ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ac14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7e10aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c (455 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbfmlalt_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlalt.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_lane_7_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlalt.lane.v2( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlalt_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfmlalt( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056398c1ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056398c1c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056398c1ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc59e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc59e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc59e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc59e631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056398c15fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056398c15fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056398c144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056398bdf40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056398bdf3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc59e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc59e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc59e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056398bdf3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c (456 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4984d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4984d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4984d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73c2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73c258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73c2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73c251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a49846be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a49846bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a498450b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4981000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4980ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f73c251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73c251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73c251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4980ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c (457 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmopa_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmopa.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_u32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svbmops_s32( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | call void @llvm.aarch64.sme.bmops.za32.nxv4i32(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560d92dce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d92dcb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d92dce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95a5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d92d63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d92d63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d92d48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d929f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d929f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d929f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c (458 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsub.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fsub.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsub_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fsub.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055cc57c3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc57c340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc57c3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14af21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14af2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14af21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14af203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc57bcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc57bccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc57bb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc578610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc57860dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14af204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14af2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14af2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc57860cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/builtins-arm64.c (459 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f0(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load ptr, ptr %b.addr, align 8 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @tp() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbitl(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.bitreverse.i64(i64) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rbit64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %rbit = call i64 @llvm.bitreverse.i64(i64 %0) # | ret i64 %rbit # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @hints() #0 { # | entry: # | call void @llvm.aarch64.hint(i32 0) # | call void @llvm.aarch64.hint(i32 1) # | call void @llvm.aarch64.hint(i32 2) # | call void @llvm.aarch64.hint(i32 3) # | call void @llvm.aarch64.hint(i32 4) # | call void @llvm.aarch64.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.aarch64.hint(i32) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @barriers() #0 { # | entry: # | call void @llvm.aarch64.dmb(i32 1) # | call void @llvm.aarch64.dsb(i32 2) # | call void @llvm.aarch64.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dmb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.dsb(i32) #5 # | # | ; Function Attrs: nofree nounwind willreturn # | declare void @llvm.aarch64.isb(i32) #5 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch(ptr null, i32 1, i32 2, i32 0, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 1, i32 1) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 0, i32 0, i32 0) # | call void @llvm.aarch64.prefetch(ptr null, i32 0, i32 3, i32 0, i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch(ptr readonly, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.range.prefetch(ptr readonly, i32 immarg, i32 immarg, i64) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @range_prefetch_x() #0 { # | entry: # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 0, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 1, i32 1, i64 0) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752305520640) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 576460752301326335) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -1152921504606846976) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -2305843009213693952) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 -6917529027641081856) # | call void @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @read_intent_prefetch() #0 { # | entry: # | call void @llvm.aarch64.prefetch.ir(ptr null) # | ret void # | } # | # | ; Function Attrs: nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.prefetch.ir(ptr readonly) #6 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @jcvt(double noundef %v) #7 { # | entry: # | %v.addr = alloca double, align 8 # | store double %v, ptr %v.addr, align 8 # | %0 = load double, ptr %v.addr, align 8 # | %1 = call i32 @llvm.aarch64.fjcvtzs(double %0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.fjcvtzs(double) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rsr() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = trunc i64 %0 to i32 # | ret i32 %1 # | } # | # | ; Function Attrs: nounwind # | declare i64 @llvm.read_volatile_register.i64(metadata) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @rsr64() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @rsrp() #0 { # | entry: # | %0 = call i64 @llvm.read_volatile_register.i64(metadata !7) # | %1 = inttoptr i64 %0 to ptr # | ret ptr %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %1 = zext i32 %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: nocallback nounwind # | declare void @llvm.write_register.i64(metadata, i64) #8 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsr64(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | call void @llvm.write_register.i64(metadata !7, i64 %0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wsrp(ptr noundef %v) #0 { # | entry: # | %v.addr = alloca ptr, align 8 # | store ptr %v, ptr %v.addr, align 8 # | %0 = load ptr, ptr %v.addr, align 8 # | %1 = ptrtoint ptr %0 to i64 # | call void @llvm.write_register.i64(metadata !7, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cls(i32 noundef %v) #0 { # | entry: # | %v.addr = alloca i32, align 4 # | store i32 %v, ptr %v.addr, align 4 # | %0 = load i32, ptr %v.addr, align 4 # | %cls = call i32 @llvm.aarch64.cls(i32 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsl(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.cls64(i64) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clsll(i64 noundef %v) #0 { # | entry: # | %v.addr = alloca i64, align 8 # | store i64 %v, ptr %v.addr, align 8 # | %0 = load i64, ptr %v.addr, align 8 # | %cls = call i32 @llvm.aarch64.cls64(i64 %0) # | ret i32 %cls # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndr(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndr() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndr() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rndrrs(ptr noundef %__addr) #9 { # | entry: # | %__addr.addr = alloca ptr, align 8 # | store ptr %__addr, ptr %__addr.addr, align 8 # | %0 = call { i64, i1 } @llvm.aarch64.rndrrs() # | %1 = extractvalue { i64, i1 } %0, 0 # | %2 = extractvalue { i64, i1 } %0, 1 # | %3 = load ptr, ptr %__addr.addr, align 8 # | store i64 %1, ptr %3, align 8 # | %4 = zext i1 %2 to i32 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { i64, i1 } @llvm.aarch64.rndrrs() #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @trap() #0 { # | entry: # | call void @llvm.aarch64.break(i32 42) # | ret void # | } # | # | ; Function Attrs: cold noreturn nounwind # | declare void @llvm.aarch64.break(i32 immarg) #10 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @atomic_store_with_hint(ptr noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca i64, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store atomic i64 %1, ptr %0 monotonic, align 8, !mem.cache_hint !8 # | %2 = load ptr, ptr %a.addr, align 8 # | %3 = load i64, ptr %b.addr, a # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:243:3: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 243 | __builtin_arm_atomic_store_with_hint(a, b, __ATOMIC_RELAXED, 5); // Invalid Hint # | | ^ ~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:305:3: warning: unrecognised hint type argument to atomic hint operation (0) [-Watomic-hint-type] # | 305 | __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_KEEP); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:306:3: warning: unrecognised hint type argument to atomic hint operation (1) [-Watomic-hint-type] # | 306 | __builtin_arm_atomic_fetch_sub_with_hint(a, b, __ATOMIC_RELAXED, HINT_STSHH_STRM); # | | ^ ~~~~~~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:307:3: warning: unrecognised hint type argument to atomic hint operation (2) [-Watomic-hint-type] # | 307 | __builtin_arm_atomic_fetch_and_with_hint(a, b, __ATOMIC_RELAXED, HINT_STCPH); # | | ^ ~~~~~~~~~~ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c:308:10: warning: unrecognised hint type argument to atomic hint operation (5) [-Watomic-hint-type] # | 308 | return __builtin_arm_atomic_fetch_add_with_hint(a, b, __ATOMIC_RELAXED, 5); # | | ^ ~ # | 5 warnings generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a32d43115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a32d42e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a32d43189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6af1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6af178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6af1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6af171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a32d3c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a32d3c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a32d3abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a32d05b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a32d05add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6af171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6af171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6af171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a32d05acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm64.c --check-prefix=CHECK --check-prefix=CHECK-LINUX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c (460 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c (461 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load < # | ... # `---data was truncated (10240/84810) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569dd71f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569dd71c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569dd71f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b5cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b5cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b5cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b5cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569dd6b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569dd6b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569dd699b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569dd3490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569dd348dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b5cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b5cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b5cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569dd348cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c (462 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv2i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv2i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfd.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfd_gather_u64base( %pg, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c (463 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, al # | ... # `---data was truncated (10240/72135) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb28c7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb28c710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb28c7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fded9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fded9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fded9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fded9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb28c09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb28c09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb28beeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb2889e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb2889ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fded9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fded9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fded9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb2889dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c (464 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv16i1.p0(, ptr, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv16i1.p0( %0, ptr %3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfb.gather.scalar.offset.nxv2i64(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfb_gather_s32offset( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/16554) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b9a02e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9a02e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9a02e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e70733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e7078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e70733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e7071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9a027ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9a027ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9a0263b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b99ff130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b99ff12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e7071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e7071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e7071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b99ff12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c (465 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmaxnm.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmaxnm_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmaxnm.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055ae8dec115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae8debe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae8dec189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8406933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f840698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8406933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f840691b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae8de56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae8de56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae8de3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae8daeb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae8daeadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f840691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f840691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f840691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae8daeacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c (466 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme-f16f16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvtl_f32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fcvtl.widen.x2.nxv4f32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme-f16f16" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055eabab8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eabab830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eabab8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe53bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe53bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe53bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe53bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eabab1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eabab1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eabab00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eaba7b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eaba7afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe53bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe53bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe53bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaba7afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c (467 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b96b57115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b96b56e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b96b57189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe34f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe34f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe34f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe34f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b96b506e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b96b506c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b96b4ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b96b19b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b96b19add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe34f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe34f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe34f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b96b19acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c (468 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincd.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincd.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincd.n32(i32 %0, i32 9, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincd.n64(i64 %0, i32 10, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincd_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincd.n32(i32 %0, i32 11, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincd_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincd.n64(i64 %0, i32 12, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqincd.nxv2i64(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_s64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqincd.nxv2i64( %0, i32 13, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqincd_pat_u64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqincd.nxv2i64( %0, i32 29, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a5c277c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a5c27790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a5c277c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fa3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fa3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fa3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fa3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5c2711e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a5c2711c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a5c26f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5c23a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a5c23a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fa3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fa3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fa3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5c23a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c (469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c (470 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s16( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s32( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_s64( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_u8( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 16 # | %tuple.addr = alloca { , , , }, align 16 # | %x.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 16 # | %tuple1 = load { , , , }, ptr %tuple, align 16 # | store { , , , } %tuple1, ptr %tuple.addr, align 16 # | store %x, ptr %x.addr, align 16 # | %4 = load { , , , }, ptr %tuple.addr, align 16 # | %5 = load , ptr %x.addr, align 16 # | ... # `---data was truncated (10240/34217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b8e00df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8e00dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8e00df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a14733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a1478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a14733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a1471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8e0074e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8e0074c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8e0059b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8dfd090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8dfd08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a1471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a1471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a1471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8dfd08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (471 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_0( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 0 # | ret { , } %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svset2_b_1( %tuple.coerce0, %tuple.coerce1, %x) #0 { # | entry: # | %tuple = alloca { , }, align 2 # | %tuple.addr = alloca { , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 2 # | %tuple1 = load { , }, ptr %tuple, align 2 # | store { , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %2 = load { , }, ptr %tuple.addr, align 2 # | %3 = load , ptr %x.addr, align 2 # | %4 = insertvalue { , } %2, %3, 1 # | ret { , } %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d1404c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d1404c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d1404c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff678533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff67858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff678533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff67851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d14045ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d14045ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d14043fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d1400ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d1400eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff67851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff67851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff67851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1400eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c (472 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64 -target-feature +sme-b16b16 -target-feature +sme-f64f64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_s8_s8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4a.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4s_2x2_za32_u8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | call void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 1, %5, %6, %8, %9) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umop4s.wide.2x2.nxv16i8(i32 immarg, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmop4a_2x2_za32_s8_u8( %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | % # | ... # `---data was truncated (10240/74176) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f87adc515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f87adc20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f87adc589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3a8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3a858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3a8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3a851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f87ad5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f87ad5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f87ad3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f87a9ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f87a9eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc3a851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3a851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3a851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f87a9eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c (473 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-bfscale -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_single_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.single.x2.nxv8bf16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_single_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | store { , , , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load { , , , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load , ptr %zm.addr, align 16 # | %10 = call { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16( %5, %6, %7, %8, %9) # | ret { , , , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , , , } @llvm.aarch64.sve.fmul.single.x4.nxv8bf16(, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svmul_bf16_x2( %zdn.coerce0, %zdn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load { , }, ptr %zdn.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = load { , }, ptr %zm.addr, align 16 # | %8 = extractvalue { , } %7, 0 # | %9 = extractvalue { , } %7, 1 # | %10 = call { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16( %5, %6, %8, %9) # | ret { , } %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.fmul.x2.nxv8bf16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svmul_bf16_x4( %zdn.coerce0, %zdn.coerce1, %zdn.coerce2, %zdn.coerce3, %zm.coerce0, %zm.coerce1, %zm.coerce2, %zm.coerce3) #0 { # | entry: # | %zdn = alloca { , , , }, align 16 # | %zm = alloca { , , , }, align 16 # | %zdn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zdn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zdn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zdn.coerce3, 3 # | store { , , , } %3, ptr %zdn, align 16 # | %zdn1 = load { , , , }, ptr %zdn, align 16 # | %4 = insertvalue { , , , } poison, %zm.coerce0, 0 # | %5 = insertvalue { , , , } %4, %zm.coerce1, 1 # | %6 = insertvalue { , , , } %5, %zm.coerce2, 2 # | %7 = insertvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c (474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565239eba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565239eb70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565239eba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41f3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41f378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41f3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41f371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565239e4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565239e4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565239e34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565239ae40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565239ae3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41f371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41f371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41f371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565239ae3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c (475 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.rdffr() # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrdffr_z( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call @llvm.aarch64.sve.rdffr.z( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.rdffr.z() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000563119c6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563119c660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563119c6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c60933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c6098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c60933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c6091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563119bfee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563119bfec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563119be3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005631198930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563119892dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3c6091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c6091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c6091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563119892cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c (476 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | call void @llvm.aarch64.sve.st4.nxv16i8.p0( %7, %8, %9, %10, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv16i8.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %4) # | call void @llvm.aarch64.sve.st4.nxv8i16.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv8i16.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %data.coerce3, 3 # | store { , , , } %3, ptr %data, align 16 # | %data1 = load { , , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , , } %data1, ptr %data.addr, align 16 # | %4 = load , ptr %pg.addr, align 2 # | %5 = load ptr, ptr %base.addr, align 8 # | %6 = load { , , , }, ptr %data.addr, align 16 # | %7 = extractvalue { , , , } %6, 0 # | %8 = extractvalue { , , , } %6, 1 # | %9 = extractvalue { , , , } %6, 2 # | %10 = extractvalue { , , , } %6, 3 # | %11 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %4) # | call void @llvm.aarch64.sve.st4.nxv4i32.p0( %7, %8, %9, %10, %11, ptr %5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st4.nxv4i32.p0(, , , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst4_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2, %data.coerce3) #0 { # | entry: # | %data = alloca { , , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , , }, align 16 # | %0 = insertvalue { , , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , , } %1, %data.coerce2, 2 # | %3 = insertvalue { , , , } %2, %da # | ... # `---data was truncated (10240/73307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c0c17a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0c17a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0c17a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f114cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f114cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f114cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f114cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0c173ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c0c173cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c0c1721b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0c13d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c0c13d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f114cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f114cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f114cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0c13d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c (477 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_bf16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8bf16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_f16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fvdot.lane.za32.vg1x2.nxv8f16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_u16_vg1x2(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.uvdot.lane.za32.vg1x2.nxv8i16(i32, , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svvdot_lane_za32_s8_vg1x4(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.svdot.lane.za32.vg1x4.nxv16i8(i32, , , , , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | ... # `---data was truncated (10240/24605) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564fba07f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fba07c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fba07f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66de705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66de75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66de705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66de6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fba014e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fba014c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fb9ff9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fb9ca90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fb9ca8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f66de6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66de6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66de6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fb9ca8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c (478 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c (479 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c6ddc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c6ddc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c6ddc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45fc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45fc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45fc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45fc431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c6dd5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c6dd5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c6dd40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c6d9f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c6d9efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f45fc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45fc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45fc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c6d9efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/bf16-getset.c (480 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/bf16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0, align 8 # | %1 = load <4 x bfloat>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x bfloat> %1, i32 1 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vduph_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca bfloat, align 2 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0, align 16 # | %1 = load <8 x bfloat>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x bfloat> %1, i32 7 # | store bfloat %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %2, ptr %__ret, align 2 # | %3 = load bfloat, ptr %__ret, align 2 # | store bfloat %3, ptr %tmp, align 2 # | %4 = load bfloat, ptr %tmp, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_48 = alloca <4 x bfloat>, align 8 # | %__s0_48 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_48, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_48, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_48, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_48, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret_46 = alloca <8 x bfloat>, align 16 # | %__s0_46 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_46, align 8 # | %1 = load <4 x bfloat>, ptr %__s0_46, align 8 # | store <4 x bfloat> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x bfloat> # | %lane = shufflevector <4 x bfloat> %3, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_46, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_46, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_52 = alloca <4 x bfloat>, align 8 # | %__s0_52 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | %tmp1 = alloca <4 x bfloat>, align 8 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_52, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_52, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | store <4 x bfloat> %6, ptr %__ret_52, align 8 # | %7 = load <4 x bfloat>, ptr %__ret_52, align 8 # | store <4 x bfloat> %7, ptr %tmp1, align 8 # | %8 = load <4 x bfloat>, ptr %tmp1, align 8 # | ret <4 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> noundef %v) #0 { # | entry: # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret_50 = alloca <8 x bfloat>, align 16 # | %__s0_50 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | %tmp1 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_50, align 16 # | %1 = load <8 x bfloat>, ptr %__s0_50, align 16 # | store <8 x bfloat> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x bfloat> # | %lane = shufflevector <8 x bfloat> %3, <8 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | store <8 x bfloat> %6, ptr %__ret_50, align 16 # | %7 = load <8 x bfloat>, ptr %__ret_50, align 16 # | store <8 x bfloat> %7, ptr %tmp1, align 16 # | %8 = load <8 x bfloat>, ptr %tmp1, align 16 # | ret <8 x bfloat> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vdup_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %.compoundliteral.i = alloca <4 x bfloat>, align 8 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <4 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <4 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <4 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <4 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | store <4 x bfloat> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %5 = load <4 x bfloat>, ptr %.compoundliteral.i, align 8 # | store <4 x bfloat> %5, ptr %__ret.i, align 8 # | %6 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vdupq_n_bf16(bfloat noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %.compoundliteral.i = alloca <8 x bfloat>, align 16 # | %v.addr = alloca bfloat, align 2 # | store bfloat %v, ptr %v.addr, align 2 # | %0 = load bfloat, ptr %v.addr, align 2 # | store bfloat %0, ptr %__p0.addr.i, align 2 # | %1 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit.i = insertelement <8 x bfloat> poison, bfloat %1, i32 0 # | %2 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit1.i = insertelement <8 x bfloat> %vecinit.i, bfloat %2, i32 1 # | %3 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit2.i = insertelement <8 x bfloat> %vecinit1.i, bfloat %3, i32 2 # | %4 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit3.i = insertelement <8 x bfloat> %vecinit2.i, bfloat %4, i32 3 # | %5 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit4.i = insertelement <8 x bfloat> %vecinit3.i, bfloat %5, i32 4 # | %6 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit5.i = insertelement <8 x bfloat> %vecinit4.i, bfloat %6, i32 5 # | %7 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit6.i = insertelement <8 x bfloat> %vecinit5.i, bfloat %7, i32 6 # | %8 = load bfloat, ptr %__p0.addr.i, align 2 # | %vecinit7.i = insertelement <8 x bfloat> %vecinit6.i, bfloat %8, i32 7 # | store <8 x bfloat> %vecinit7.i, ptr %.compoundliteral.i, align 16 # | %9 = load <8 x bfloat>, ptr %.compoundliteral.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/13833) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556ff8b4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ff8b440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ff8b4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ff8adce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ff8adcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ff8ac1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ff87710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ff8770dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f06d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ff8770cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/bf16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c (481 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, # | ... # `---data was truncated (10240/37388) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055674a99315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055674a9900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055674a99389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42d3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42d36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42d3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42d3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055674a928e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055674a928c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055674a90db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055674a5bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055674a5bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42d3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42d36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42d36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055674a5bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c (482 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.zip1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e8100b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8100b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8100b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f7c905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f7c95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f7c905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f7c8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e81004de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e81004dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e810032b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e80fce20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e80fce1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f7c8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f7c8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f7c8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e80fce1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/perm.c (483 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/perm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.mfloat8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.mfloat8x16x2_t = type { [2 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vzip1q_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vzip1_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vzip1q_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vzip1q_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %2, <2 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vzip1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vzip1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vzip1_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, # | ... # `---data was truncated (10240/231562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000563fd6a1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563fd6a110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563fd6a1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe023a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe023aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe023a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe023a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fd69a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563fd69a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563fd698eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563fd663e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563fd663ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe023a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe023a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe023a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fd663dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/perm.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c (484 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv16i8.p0( %0, ptr %1) # | ret { , , , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8i16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv4i32.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv2i64.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0( %2, ptr %1) # | ret { , , , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , , , } @llvm.aarch64.sve.ld4.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svld4_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.fr # | ... # `---data was truncated (10240/27970) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb2182e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb2182b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb2182e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9313a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9313a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9313a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9313a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb217c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb217c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb217a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb214580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb21457dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9313a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9313a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9313a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb21457cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c (485 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_s64( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u8( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u16( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | store %x4, ptr %x4.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = load , ptr %x4.addr, align 16 # | %4 = insertvalue { , , , } poison, %0, 0 # | %5 = insertvalue { , , , } %4, %1, 1 # | %6 = insertvalue { , , , } %5, %2, 2 # | %7 = insertvalue { , , , } %6, %3, 3 # | ret { , , , } %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svcreate4_u32( %x0, %x1, %x2, %x4) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | %x4.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c (486 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %2) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacgt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %1, %.splat) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055885411115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055885410e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055885411189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76b6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76b6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76b6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76b6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588540a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588540a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055885408bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558853d3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558853d3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f76b6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76b6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76b6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558853d3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c (487 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c (488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c (489 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_s64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single2_u64(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load i32, ptr %slice_base.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %2, %4, %5, %6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_s32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %4, %6, %7, %8, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: write) # | declare void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, , , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsub_write_single4_u32(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c (490 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv16i8.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %2) # | call void @llvm.aarch64.sve.st2.nxv8i16.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv8i16.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %2) # | call void @llvm.aarch64.sve.st2.nxv4i32.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv4i32.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | %7 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %2) # | call void @llvm.aarch64.sve.st2.nxv2i64.p0( %5, %6, %7, ptr %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st2.nxv2i64.p0(, , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } %data1, ptr %data.addr, align 16 # | %2 = load , ptr %pg.addr, align 2 # | %3 = load ptr, ptr %base.addr, align 8 # | %4 = load { , }, ptr %data.addr, align 16 # | %5 = extractvalue { , } %4, 0 # | %6 = extractvalue { , } %4, 1 # | call void @llvm.aarch64.sve.st2.nxv16i8.p0( %5, %6, %2, ptr %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst2_u16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1) #0 { # | entry: # | %data = alloca { , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %data.coerce0, 0 # | %1 = insertvalue { , } %0, %data.coerce1, 1 # | store { , } %1, ptr %data, align 16 # | %data1 = load { , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , } # | ... # `---data was truncated (10240/45653) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e66c53715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e66c5340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e66c53789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe731b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe731b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe731b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe731b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e66c4cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e66c4ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e66c4b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e66c1610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e66c160dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe731b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe731b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe731b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e66c160cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c (491 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c (492 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u8( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u32( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_u64( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.uclamp.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uclamp.nxv2i64(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d5d9a7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5d9a710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5d9a7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85ef733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85ef78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85ef733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85ef71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5d9a09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5d9a09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5d99eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5d969e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5d969ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85ef71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85ef71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85ef71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5d969dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/orn.c (493 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/orn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.orn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000561c542f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561c542f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561c542f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2d3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2d3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2d3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2d3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c5428ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561c5428ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561c54273b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561c53f230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561c53f22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2d3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2d3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2d3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c53f22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/orn.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c (494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/65723) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f80f3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f80f370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f80f3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2849933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f284998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2849933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f284991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f80ecfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f80ecfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f80eb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f80b640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f80b63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f284991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f284991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f284991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f80b63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c (495 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566afffb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566afff80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566afffb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f061be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f061bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f061be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f061be31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566aff90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566aff90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566aff75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566afc250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566afc24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f061be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f061be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f061be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566afc24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c (496 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d4b86415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d4b8610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d4b86489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5265849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52658a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5265849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5265831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d4b7f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d4b7f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d4b7deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d4b48e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d4b48ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5265832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52658330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52658330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d4b48dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c (497 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1_vnum_s8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/63749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e398baa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e398ba70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e398baa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd6b0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6b08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd6b0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd6b0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e398b3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e398b3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e398b24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3987d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3987d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd6b0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6b08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6b08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3987d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c (498 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @and_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %and = and %0, %1 # | ret %and # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @or_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %or = or %0, %1 # | ret %or # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @xor_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c (499 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.stnt1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svstnt1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.stnt1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.stnt1.nxv4f32.p0(, , ptr # | ... # `---data was truncated (10240/26796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005622c20eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005622c20e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005622c20eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b76533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b7658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b76533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b7651b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622c2080e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005622c2080c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005622c2065b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622c1d150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622c1d14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2b7651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b7651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b7651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622c1d14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c (500 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614fb6cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614fb6c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005614fb6cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30ca71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614fb661e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005614fb661c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005614fb646b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005614fb2f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005614fb2f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f30ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614fb2f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c (501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2d011a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2d01170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c2d011a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc310533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc31058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc310533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc31051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2d00afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2d00afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c2d0094b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2cfd440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c2cfd43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc31051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc31051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc31051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2cfd43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c (502 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cnth(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcnth_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cnth(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055fdb4c2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fdb4c200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fdb4c2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabb8f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabb8f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabb8f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabb8f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdb4bb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fdb4bb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fdb4b9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fdb484d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fdb484cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fabb8f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabb8f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabb8f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdb484ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c (503 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d105ddf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d105ddc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d105ddf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e1cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e1cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e1cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e1cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d105d74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d105d74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d105d59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d105a090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d105a08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e1cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e1cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e1cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d105a08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c (504 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brkb.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkb_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkb.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkb.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055956687f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055956687c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055956687f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63f7c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63f7ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63f7c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63f7c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559566814e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559566814c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595667f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595664a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595664a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63f7c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63f7c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63f7c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595664a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c (505 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme-f8f16 -target-feature +sme-f8f32 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za32_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x2(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load i32, ptr %slice.addr, align 4 # | %3 = load { , }, ptr %zn.addr, align 16 # | %4 = extractvalue { , } %3, 0 # | %5 = extractvalue { , } %3, 1 # | %6 = load , ptr %zm.addr, align 16 # | %7 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %2, %4, %5, %6, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svdot_lane_za16_f8_vg1x4(i32 noundef %slice, %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, %zm, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %slice.addr = alloca i32, align 4 # | %zn.addr = alloca { , , , }, align 16 # | %zm.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store i32 %slice, ptr %slice.addr, align 4 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load i32, ptr %slice.addr, align 4 # | %5 = load { , , , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , , , } %5, 0 # | %7 = extractvalue { , , , } %5, 1 # | %8 = extractvalue { , , , } %5, 2 # | %9 = extractvalue { , , , } %5, 3 # | %10 = load , ptr %zm.addr, align 16 # | %11 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %11) # | call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %4, %6, %7, %8, %9, %10, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read, target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32, , , , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_ra # | ... # `---data was truncated (10240/35066) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes mem2reg,instcombine,tailcallelim # | #0 0x0000562dfb26315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562dfb2600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562dfb26389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ba6105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ba615c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ba6105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ba60ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dfb1f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562dfb1f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562dfb1ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562dfae8d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562dfae8cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ba60eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ba60ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ba60ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dfae8ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c (506 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5b129a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5b12970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5b129a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f46133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f4618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f46133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f4611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5b122fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5b122fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5b1214b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5b0ec40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5b0ec3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f4611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f4611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f4611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5b0ec3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c (507 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_s32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64 %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv16i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b16(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv8i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b32(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv4i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_s64_b64(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca , align 2 # | store i64 %op, ptr %op.addr, align 8 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64 %0, %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecp.n64.nxv2i1(i64, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b8(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %0, %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b16(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b32(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecp_n_u32_b64(i32 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | %pg.addr = alloca , align 2 # | store i32 %op, ptr %op.addr, align 4 # | store %pg, ptr %pg.addr, align 2 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = load , ptr %pg.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %0, %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecp_n_u64_b8(i64 noundef %op, %pg) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c (508 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.brka.z.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.z.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrka_b_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 2 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %inactive, ptr %inactive.addr, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %inactive.addr, align 2 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 2 # | %3 = call @llvm.aarch64.sve.brka.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brka.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005578a0d6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005578a0d5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005578a0d6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91f7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91f7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91f7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91f7e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578a0cf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005578a0cf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005578a0cdcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005578a098c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005578a098bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f91f7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91f7e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91f7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578a098bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c (509 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilelt_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056349b6dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056349b6d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056349b6dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48d1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48d178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48d1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48d171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056349b671e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056349b671c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056349b656b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056349b3060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056349b305dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48d171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48d171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48d171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056349b305cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c (510 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntw(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntw_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntw(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000564bd416e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564bd416b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564bd416e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd06cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd06cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd06cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd06cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bd4103e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564bd4103c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564bd40e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564bd3d980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564bd3d97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd06cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd06cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd06cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bd3d97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c (511 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2q.sret.nxv8bf16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2q_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2q.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | d # | ... # `---data was truncated (10240/75038) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556d9012115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d9011e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d9012189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa11301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1130725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa11301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa113003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d900b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d900b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d9009bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d8fd4b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d8fd4add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa113004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1130050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1130050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d8fd4acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c (512 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlsl.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlsl.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmls4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564ef1c0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ef1c0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ef1c0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17def33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17def8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17def33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17def1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ef1ba4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ef1ba4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ef1b89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564ef18390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564ef1838dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f17def1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17def1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17def1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ef1838cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c (513 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c (514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector. # | ... # `---data was truncated (10240/78690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bce0e6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bce0e640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bce0e6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9036333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f903638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9036333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f903631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bce0dfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bce0dfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bce0de1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bce0a910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bce0a90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f903631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f903631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f903631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bce0a90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c (515 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 noundef # | ... # `---data was truncated (10240/29167) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619a7dfc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005619a7df90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619a7dfc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6823e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6823ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6823e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6823e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619a7d91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005619a7d91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005619a7d76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619a7a260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619a7a25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6823e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6823e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6823e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619a7a25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c (516 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.cntp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.cntp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056291b31115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056291b30e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056291b31189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb718d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb718d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb718d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb718d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056291b2a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056291b2a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056291b28bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056291af3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056291af3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb718d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb718d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb718d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056291af3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c (517 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtrn2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.trn2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.trn2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056146bbae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056146bbab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056146bbae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78c0905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78c095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78c0905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78c08ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056146bb43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056146bb43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056146bb28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056146b7d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056146b7d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f78c08eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78c08ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78c08ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056146b7d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c (518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_i16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m1_bf16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m2_bf16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m4_bf16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_u16m8_bf16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_i16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_i16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_i16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m8_i16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m1_u16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m2_u16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vreinterpret_v_bf16m4_u16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 # | ... # `---data was truncated (10240/11237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba3f2b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba3f2b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba3f2b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c5ad05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c5ad5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c5ad05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c5aced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba3f24ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba3f24cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba3f231b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba3eee10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba3eee0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c5aceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c5acef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c5acef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba3eee0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c (519 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u16_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u32_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_s64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sunpk.x2.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svunpk_u64_x2( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64( %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.uunpk.x2.nxv2i64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e08f70f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e08f70c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e08f70f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f11f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f11f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f11f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f11f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e08f6a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e08f6a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e08f689b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e08f3390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e08f338dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f11f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f11f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f11f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e08f338cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c (520 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue # | ... # `---data was truncated (10240/81764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c27a4ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c27a4fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c27a4ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70fd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c27a494e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c27a494c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c27a479b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c27a1290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c27a128dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70fd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c27a128cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c (521 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv8f16(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv4f32(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fnmls.nxv2f64(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f32_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv4f32( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f64_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.nxv2f64( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnmls_f16_x( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.fnmls.u.nxv8f16( %4, %1, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/26173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563cad1fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563cad1f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563cad1fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb372449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3724a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb372449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb372431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cad191e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563cad191c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563cad176b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563cace260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563cace25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb372432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3724330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3724330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cace25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c (522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/14493) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0d5ed015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0d5ecd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0d5ed089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff793449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7934a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff793449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff793431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0d5e65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c0d5e65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c0d5e4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0d5afa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c0d5af9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff793432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7934330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7934330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0d5af9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c (523 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv8f16(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_1( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_2( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 180) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_z_3( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv8f16( %4, %5, %2, %3, i32 270) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv4f32( %4, %5, %2, %3, i32 0) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv4f32(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.fcmla.nxv2f64( %4, %5, %2, %3, i32 90) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcmla.nxv2f64(, , , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcmla_f16_m( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c (524 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_bf16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt1_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtlt2_f16_mf8( %zn, i64 noundef %fpm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpm.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16( %0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16() #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp8,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055f5bab5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5bab5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5bab5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1049d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1049d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1049d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1049ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5baaf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5baaf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5baad7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5ba7870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5ba786dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1049ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1049cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1049cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5ba786cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c (525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/135345) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055becfbab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055becfba80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055becfbab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f109b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f109b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f109b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f109b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055becfb40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055becfb40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055becfb25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055becf7d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055becf7d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f109b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f109b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f109b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055becf7d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c (526 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640a721115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640a720e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640a721189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb29733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb2978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb29733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb2971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640a71a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005640a71a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005640a718bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640a6e3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640a6e3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdb2971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb2971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb2971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640a6e3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c (527 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f54bd0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f54bd0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f54bd0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f236cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f236cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f236cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f236cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f54bca3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f54bca3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f54bc88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f54b9380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f54b937dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f236cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f236cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f236cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f54b937cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c (528 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570c530f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570c530c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570c530f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43bdd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43bdd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43bdd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43bdd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570c52a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570c52a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570c5289b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570c4f390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570c4f38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f43bdd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43bdd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43bdd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570c4f38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c (529 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_x( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcvtnt.bf16f32.v2(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcvtnt_bf16_f32_m( %even, %pg, %op) #0 { # | entry: # | %even.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %even, ptr %even.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %even.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fcvtnt.bf16f32.v2( %0, %3, %2) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d6fb70215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6fb6ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d6fb70289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fe6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fe66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fe6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fe6631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6fb697e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d6fb697c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d6fb67cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6fb32c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6fb32bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8fe6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fe66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fe66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6fb32bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c (530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3049dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3049da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3049dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3d5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3d575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3d5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3d56ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e304972e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e304972c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e304957b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3046070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e304606dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3d56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3d56ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3d56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e304606cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c (531 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.7a -target-feature +f16mm -target-feature +f16f32mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <8 x half> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <8 x half> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_f16(<4 x float> noundef %acc, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %fmmla.i = bitcast <16 x i8> %3 to <4 x float> # | %fmmla1.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla2.i = bitcast <16 x i8> %5 to <8 x half> # | %fmmla3.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float> %fmmla.i, <8 x half> %fmmla1.i, <8 x half> %fmmla2.i) # | store <4 x float> %fmmla3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f16f32dot,+f16f32mm,+f16mm,+faminmax,+flagm,+fp-armv8,+fprcvt,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+sve2p3,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9.7a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005613184a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613184a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005613184a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb81c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb81c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb81c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb81c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056131843ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056131843ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561318423b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005613180d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005613180d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb81c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb81c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb81c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613180d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/minnmv.c (532 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/minnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svminnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fminnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fminnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svminnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fminnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fminnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svminnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fminnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fminnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000056153956c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615395690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056153956c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff06eb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff06eb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff06eb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff06eaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561539501e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561539501c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615394e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615391960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561539195dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff06eaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff06eaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff06eaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561539195cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/minnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c (533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/80648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557607d3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557607d3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557607d3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2ac649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2ac6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2ac649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2ac631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557607cd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557607cd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557607cb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005576079690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557607968dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe2ac632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2ac6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2ac6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557607968cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c (534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbc7d9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbc7d8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbc7d9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfbe449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfbe4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfbe449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfbe431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbc7d27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbc7d27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbc7d0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbc79bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbc79bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfbe432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfbe4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfbe4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbc79bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/maxv.c (535 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.smaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.smaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.smaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.smaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.smaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.smaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svmaxv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svmaxv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.umaxv.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.umaxv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svmaxv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.umaxv.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.umaxv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svmaxv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.umaxv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.umaxv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attribute # | ... # `---data was truncated (10240/10818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x00005633f5cff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633f5cfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633f5cff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9605333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f960538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9605333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f960531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633f5c94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633f5c94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633f5c79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633f59290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633f5928dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f960531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f960531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f960531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633f5928cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-fma.c (536 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store float %c, ptr %c.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load float, ptr %c.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | %mul.i = fmul <4 x float> %4, %9 # | %sub.i = fsub <4 x float> %3, %mul.i # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %c.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | %mul.i = fmul <2 x float> %4, %7 # | %sub.i = fsub <2 x float> %3, %mul.i # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %8 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_68 = alloca <2 x float>, align 8 # | %__s0_68 = alloca <2 x float>, align 8 # | %__s1_68 = alloca <2 x float>, align 8 # | %__s2_68 = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp1 = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0_68, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_68, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_68, align 8 # | %3 = load <2 x float>, ptr %__s0_68, align 8 # | %4 = load <2 x float>, ptr %__s1_68, align 8 # | %5 = load <2 x float>, ptr %__s2_68, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | %mul = fmul <2 x float> %4, %10 # | %add = fadd <2 x float> %3, %mul # | store <2 x float> %add, ptr %__ret_68, align 8 # | %11 = load <2 x float>, ptr %__ret_68, align 8 # | store <2 x float> %11, ptr %tmp1, align 8 # | %12 = load <2 x float>, ptr %tmp1, align 8 # | ret <2 x float> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %v.addr = alloca <2 x float>, align 8 # | %__ret_58 = alloca <4 x float>, align 16 # | %__s0_58 = alloca <4 x float>, align 16 # | %__s1_58 = alloca <4 x float>, align 16 # | %__s2_58 = alloca <2 x float>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | %tmp1 = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__s0_58, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_58, align 16 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2_58, align 8 # | %3 = load <4 x float>, ptr %__s0_58, align 16 # | %4 = load <4 x float>, ptr %__s1_58, align 16 # | %5 = load <2 x float>, ptr %__s2_58, align 8 # | store <2 x f # | ... # `---data was truncated (10240/44730) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055eb0bda615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb0bda30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb0bda689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28b981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28b98725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28b981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28b9803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb0bd3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb0bd3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb0bd20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb0b9d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb0b9cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28b9804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28b98050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28b98050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb0b9cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c (537 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i8.p0(, , ptr captures(none)) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = trunc %2 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %4, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv8i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv4i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = load , ptr %data.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = getelementptr , ptr %1, i64 %2 # | %6 = trunc %3 to # | call void @llvm.aarch64.sve.st1.nxv2i8.p0( %6, %4, ptr %5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1b_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum, %data) #0 { # | e # | ... # `---data was truncated (10240/32866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000564fa689415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fa68910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fa689489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1784a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1784aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1784a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1784a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fa6829e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fa6829c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fa680eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fa64be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fa64bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1784a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1784a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1784a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fa64bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c (538 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643517c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643517c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643517c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f378de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f378de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f378de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f378de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056435175ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056435175ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564351743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643513f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643513f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f378de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f378de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f378de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643513f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c (539 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.eor.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.eor.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.eor.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_sveor_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e38767915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3876760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e38767989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8a0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8a06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8a0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8a0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e38760ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e38760ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e3875f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3872a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3872a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8a0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8a06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8a06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3872a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c (540 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587c55cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587c55cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587c55cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f954c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f954c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f954c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f954c203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587c5564e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587c5564c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587c5549b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587c51f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587c51f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f954c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f954c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f954c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587c51f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c (541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b4a0da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b4a0d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b4a0da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf8dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf8dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf8dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf8dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b4a06fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b4a06fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b4a054b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b49d040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b49d03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf8dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf8dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf8dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b49d03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c (542 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv8i16(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4i32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti4_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 0, %0, i32 1) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti4.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000564a622db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a622d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a622db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e18905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e1895c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e18905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e188ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a62270e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a62270c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a62255b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a61f050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a61f04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e188eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e188ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e188ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a61f04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c (543 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintx.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintx.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintx_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintx.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005643ce8d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643ce8d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643ce8d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7365e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7365ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7365e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7365e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643ce86be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643ce86bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643ce850b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643ce5000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643ce4ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7365e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7365e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7365e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643ce4ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16.c (544 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vaddh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vaddh = fadd half %2, %3 # | store half %vaddh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vsubh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vsubh = fsub half %2, %3 # | store half %vsubh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmulh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmulh = fmul half %2, %3 # | store half %vmulh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vdivh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vdivh = fdiv half %2, %3 # | store half %vdivh, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmax = call half @llvm.aarch64.neon.fmax.f16(half %2, half %3) # | store half %vmax, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmax.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vmaxnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmaxnm = call half @llvm.aarch64.neon.fmaxnm.f16(half %2, half %3) # | store half %vmaxnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmaxnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vmin = call half @llvm.aarch64.neon.fmin.f16(half %2, half %3) # | store half %vmin, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fmin.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vminnmh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %__s0, align 2 # | %3 = load half, ptr %__s1, align 2 # | %vminnm = call half @llvm.aarch64.neon.fminnm.f16(half %2, half %3) # | store half %vminnm, ptr %ref.tmp, align 2 # | %4 = load half, ptr %ref.tmp, align 2 # | store half %4, ptr %__ret, align 2 # | %5 = load half, ptr %__ret, align 2 # | store half %5, ptr %tmp, align 2 # | %6 = load half, ptr %tmp, align 2 # | ret half %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.neon.fminnm.f16(half, half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabsh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vabs = call half @llvm.fabs.f16(half %1) # | store half %vabs, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.fabs.f16(half) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vabdh_f16(half noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = all # | ... # `---data was truncated (10240/27802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b0b91f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b0b91c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b0b91f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa723133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa72318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa723133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa72311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b0b8b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b0b8b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b0b899b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b0b5490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b0b548dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa72311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa72311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa72311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b0b548cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c (545 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055997e8a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055997e8a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055997e8a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31e1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31e118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31e1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31e111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055997e839e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055997e839c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055997e81eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055997e4ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055997e4cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f31e111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31e111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31e111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055997e4cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c (546 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2p2 -target-feature +f16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8f16.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f16mm,+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb3db2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb3db220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb3db2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ca2f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ca2f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ca2f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ca2f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb3dabae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb3dabac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb3da9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb3d74f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb3d74edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ca2f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ca2f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ca2f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb3d74ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c (547 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a35b0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a35aff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a35b0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb1cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb1cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb1cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb1cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a35a97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a35a97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a35a7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a3572c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a3572bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb1cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb1cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb1cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a3572bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c (548 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561da2c2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561da2c1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561da2c2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1aec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1aec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1aec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1aec11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561da2bb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561da2bb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561da2b9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561da284a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561da2849dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1aec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1aec11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1aec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561da2849cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c (549 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svreinterpret_svbool_svcnt(target("aarch64.svcount") %cnt) #0 { # | entry: # | %cnt.addr = alloca target("aarch64.svcount"), align 2 # | store target("aarch64.svcount") %cnt, ptr %cnt.addr, align 2 # | %0 = load target("aarch64.svcount"), ptr %cnt.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount") %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svcount(target("aarch64.svcount")) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local target("aarch64.svcount") @test_svreinterpret_svcnt_svbool( %pg) #0 { # | entry: # | %pg.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = call target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount( %0) # | ret target("aarch64.svcount") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("aarch64.svcount") @llvm.aarch64.sve.convert.to.svcount() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000558baaa1615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558baaa130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558baaa1689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f533c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f533c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f533c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f533c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558baa9abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558baa9abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558baa990b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558baa6400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558baa63fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f533c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f533c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f533c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558baa63fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c (550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/64349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cadbdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556cadbda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556cadbdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29c0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29c098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29c0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29c091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cadb72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556cadb72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556cadb57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556cad8070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556cad806dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f29c091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29c091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29c091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cad806cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c (551 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv4i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv8i8.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1ub_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c (552 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature -fullfp16 -target-feature +v8a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vbsl_f16(<4 x i16> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl.i = bitcast <8 x i8> %3 to <4 x i16> # | %vbsl1.i = bitcast <8 x i8> %4 to <4 x i16> # | %vbsl2.i = bitcast <8 x i8> %5 to <4 x i16> # | %vbsl3.i = and <4 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <4 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <4 x i16> %6, %vbsl2.i # | %vbsl5.i = or <4 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <4 x i16> %vbsl5.i to <4 x half> # | store <4 x half> %7, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vbslq_f16(<8 x i16> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbsl.i = bitcast <16 x i8> %3 to <8 x i16> # | %vbsl1.i = bitcast <16 x i8> %4 to <8 x i16> # | %vbsl2.i = bitcast <16 x i8> %5 to <8 x i16> # | %vbsl3.i = and <8 x i16> %vbsl.i, %vbsl1.i # | %6 = xor <8 x i16> %vbsl.i, splat (i16 -1) # | %vbsl4.i = and <8 x i16> %6, %vbsl2.i # | %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i # | %7 = bitcast <8 x i16> %vbsl5.i to <8 x half> # | store <8 x half> %7, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vzip.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vzip1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vzip.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vzip1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vzip1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x4x2_t, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %retval = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x half> # | %5 = bitcast <8 x i8> %3 to <4 x half> # | %vuzp.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp.i, ptr %retval.i, align 8 # | %6 = getelementptr inbounds <4 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <4 x half> %4, <4 x half> %5, <4 x i32> # | store <4 x half> %vuzp1.i, ptr %6, align 8 # | %7 = load %struct.float16x4x2_t, ptr %retval.i, align 8 # | %8 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x4x2_t %7, 0 # | store [2 x <4 x half>] %9, ptr %8, align 8 # | %10 = load %struct.float16x4x2_t, ptr %retval, align 8 # | ret %struct.float16x4x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %retval.i = alloca %struct.float16x8x2_t, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %retval = alloca %struct.float16x8x2_t, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x half> # | %5 = bitcast <16 x i8> %3 to <8 x half> # | %vuzp.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp.i, ptr %retval.i, align 16 # | %6 = getelementptr inbounds <8 x half>, ptr %retval.i, i32 1 # | %vuzp1.i = shufflevector <8 x half> %4, <8 x half> %5, <8 x i32> # | store <8 x half> %vuzp1.i, ptr %6, align 16 # | %7 = load %struct.float16x8x2_t, ptr %retval.i, align 16 # | %8 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %retval, i32 0, i32 0 # | %9 = extractvalue %struct.float16x8x2_t %7, 0 # | store [2 x <8 x half>] %9, ptr %8, align 16 # | %10 = load %struct.float16x8x2_t, ptr %retval, align 16 # | ret %struct.float16x8x2_t %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> noundef %a, <4 x half> noundef # | ... # `---data was truncated (10240/31986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557b9281f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b9281c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b9281f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1d4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1d438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1d4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1d431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b927b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b927b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b92799b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b924490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b92448dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1d431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1d431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1d431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b92448cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c (553 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056364bd3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056364bd310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056364bd3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc131f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc131f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc131f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc131f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056364bcc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056364bcc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056364bcaeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056364b95e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056364b95ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc131f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc131f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc131f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056364b95dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c (554 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d971b9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d971b900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d971b9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cd3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cd3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cd3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cd3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d971b28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d971b28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d971b0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9717bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9717bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5cd3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cd3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cd3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9717bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c (555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c (556 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_s64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_u64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f32() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_f64() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , } @test_svundef3_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562707fc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562707fc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562707fc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7a9231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562707f59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562707f59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562707f3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562707bee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562707beddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc7a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7a92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562707bedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c (557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556299f2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556299f240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556299f2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff03b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff03b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff03b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff03b631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556299ebce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556299ebcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556299ea1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556299b510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556299b50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff03b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff03b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff03b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556299b50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c (558 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to double # | %7 = bitcast <8 x i8> %4 to double # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %extract = extractelement <2 x double> %8, i32 0 # | %9 = call double @llvm.experimental.constrained.fma.f64(double %7, double %extract, double %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | %10 = bitcast double %9 to <1 x double> # | store <1 x double> %10, ptr %ref.tmp, align 8 # | %11 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %11, ptr %__ret, align 8 # | %12 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %12, ptr %tmp, align 8 # | %13 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %13 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <2 x double> @test_vfmaq_laneq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %v.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %v, ptr %v.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__s0, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1, align 16 # | %2 = load <2 x double>, ptr %v.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %lane = shufflevector <2 x double> %8, <2 x double> %8, <2 x i32> # | %9 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %lane, <2 x double> %7, <2 x double> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <2 x double> %9, ptr %ref.tmp, align 16 # | %10 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %10, ptr %__ret, align 16 # | %11 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %11, ptr %tmp, align 16 # | %12 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load float, ptr %__s0, align 4 # | %4 = load float, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %5, i32 1 # | %6 = call float @llvm.experimental.constrained.fma.f32(float %4, float %extract, float %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store float %6, ptr %ref.tmp, align 4 # | %7 = load float, ptr %ref.tmp, align 4 # | store float %7, ptr %__ret, align 4 # | %8 = load float, ptr %__ret, align 4 # | store float %8, ptr %tmp, align 4 # | %9 = load float, ptr %tmp, align 4 # | ret float %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <1 x double> @llvm.experimental.constrained.fma.v1f64(<1 x double>, <1 x double>, <1 x double>, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055eb9055e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb9055b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb9055e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfbfa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfbfa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfbfa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfbfa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb904f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb904f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb904d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb901880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb90187dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfbfa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfbfa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfbfa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb90187cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply-constrained.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c (559 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_u64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s8( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8i16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4i32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_s64( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv2i64( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f16( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.tbxq.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtbxq_f32( %passthru, %zn, %zm) #0 { # | entry: # | %passthru.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %passthru, ptr %passthru.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %passthru.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.tbxq.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm. # | ... # `---data was truncated (10240/14102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005633d1f4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633d1f3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633d1f4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd0ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd0aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd0ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd0ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633d1ed7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633d1ed7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633d1ebcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633d1b6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633d1b6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd0ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd0ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd0ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633d1b6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c (560 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_s64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u8( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u32( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_u64( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, %0, 0 # | %4 = insertvalue { , , } %3, %1, 1 # | %5 = insertvalue { , , } %4, %2, 2 # | ret { , , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , } @test_svcreate3_f16( %x0, %x1, %x2) #0 { # | entry: # | %x0.addr = alloca , align 16 # | %x1.addr = alloca , align 16 # | %x2.addr = alloca , align 16 # | store %x0, ptr %x0.addr, align 16 # | store %x1, ptr %x1.addr, align 16 # | store %x2, ptr %x2.addr, align 16 # | %0 = load , ptr %x0.addr, align 16 # | %1 = load , ptr %x1.addr, align 16 # | %2 = load , ptr %x2.addr, align 16 # | %3 = insertvalue { , , } poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c (561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c (562 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7b07bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7b07bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7b07bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3fa049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3fa0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3fa049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3fa031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7b0754e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7b0754c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7b0739b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7b03e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7b03e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa3fa032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3fa0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3fa0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7b03e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (563 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 0 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = extractvalue { , , , } %4, 3 # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056474a27115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056474a26e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056474a27189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e27b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e27b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e27b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e27b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056474a206e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056474a206c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056474a1ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564749e9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564749e9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e27b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e27b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e27b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564749e9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c (564 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_u16mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | ent # | ... # `---data was truncated (10240/31706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fc57b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562fc57b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562fc57b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8a171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fc574ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562fc574ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562fc5733b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562fc53e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562fc53e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8a171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fc53e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c (565 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.sabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.sabd.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sabd.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.uabd.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.uabd.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uabd.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabd_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c (566 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_s32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.usdot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_n_s32( %x, %y, i8 noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca i8, align 1 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store i8 %z, ptr %z.addr, align 1 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load i8, ptr %z.addr, align 1 # | %.splatinsert = insertelement poison, i8 %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.usdot.nxv4i32( %0, %.splat, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_0( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sudot.lane.nxv4i32(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_1( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_2( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsudot_lane_s32_3( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.sudot.lane.nxv4i32( %0, %1, %2, i32 3) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+i8mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558547dd415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558547dd10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558547dd489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd233e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd233ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd233e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd233e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558547d69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558547d69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558547d4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585479fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585479fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd233e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd233e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd233e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585479fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c (567 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd37cd515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd37cd20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd37cd589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f576e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f576e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f576e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f576e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd37c6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd37c6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd37c4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd378ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd378fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f576e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f576e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f576e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd378fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c (568 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x i32>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <4 x i32> %r, ptr %r.addr, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %r.addr, align 16 # | %1 = load <16 x i8>, ptr %a.addr, align 16 # | %2 = load <16 x i8>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | # | ... # `---data was truncated (10240/31781) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055751c86915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055751c8660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055751c86989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f518e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f518e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f518e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f518e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055751c7fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055751c7fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055751c7e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055751c4930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055751c492dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f518e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f518e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f518e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055751c492cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c (569 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzip1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.zip1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zip1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564b9389315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b938900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b9389389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1595533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f159558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1595533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f159551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b93828e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b93828c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b9380db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b934bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b934bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f159551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f159551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f159551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b934bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c (570 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_u16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_f16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8f16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za16_bf16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 1, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv8bf16(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_s32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_u32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4i32(i32 2, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za32_f32_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 3, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv4f32(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_s64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_u64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2i64(i32 4, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_hor_za64_f64_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 7, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.horiz.x2.nxv2f64(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_s8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_u8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za8_mf8_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv16i8(i32 0, i32 %0) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svreadz_ver_za16_s16_x2(i32 noundef %slice) #0 { # | entry: # | %slice.addr = alloca i32, align 4 # | store i32 %slice, ptr %slice.addr, align 4 # | %0 = load i32, ptr %slice.addr, align 4 # | %1 = call { , } @llvm.aarch64.sme.readz.vert.x2.nxv8i16(i32 0, i32 %0) # | ret { , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c (571 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/95445) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056451200e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056451200b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056451200e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff77f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff77f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff77f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff77f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564511fa3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564511fa3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564511f88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564511c380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564511c37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff77f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff77f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff77f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564511c37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c (572 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtssel_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftssel.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftssel.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055646f39115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055646f38e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055646f39189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc37733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc3778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc37733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc3771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055646f326e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055646f326c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055646f30bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055646efbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055646efbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc3771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc3771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc3771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055646efbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c (573 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svsetffr() #0 { # | entry: # | call void @llvm.aarch64.sve.setffr() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.sve.setffr() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556912e0615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556912e030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556912e0689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f40933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f4098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f40933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f4091b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556912d9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556912d9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556912d80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556912a300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556912a2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f4091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f4091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f4091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556912a2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/neon-vcmla.c (574 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes="mem2reg,instsimplify,sroa" | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64 -target-feature +neon -target-feature +v8.3a -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %vcmla_f16.i, <4 x half> %vcmla_f161.i, <4 x half> %vcmla_f162.i) # | %vcmla_f164.i = bitcast <4 x half> %vcmla_f163.i to <8 x i8> # | store <8 x i8> %vcmla_f164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %6, ptr %__ret.i, align 8 # | %7 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vcmla_f32(<2 x float> noundef %acc, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %acc, ptr %acc.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %acc.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_f32.i = bitcast <8 x i8> %3 to <2 x float> # | %vcmla_f321.i = bitcast <8 x i8> %4 to <2 x float> # | %vcmla_f322.i = bitcast <8 x i8> %5 to <2 x float> # | %vcmla_f323.i = call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %vcmla_f32.i, <2 x float> %vcmla_f321.i, <2 x float> %vcmla_f322.i) # | %vcmla_f324.i = bitcast <2 x float> %vcmla_f323.i to <8 x i8> # | store <8 x i8> %vcmla_f324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcmlaq_f16(<8 x half> noundef %acc, <8 x half> noundef %lhs, <8 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <8 x half>, align 16 # | %lhs.addr = alloca <8 x half>, align 16 # | %rhs.addr = alloca <8 x half>, align 16 # | store <8 x half> %acc, ptr %acc.addr, align 16 # | store <8 x half> %lhs, ptr %lhs.addr, align 16 # | store <8 x half> %rhs, ptr %rhs.addr, align 16 # | %0 = load <8 x half>, ptr %acc.addr, align 16 # | %1 = load <8 x half>, ptr %lhs.addr, align 16 # | %2 = load <8 x half>, ptr %rhs.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f16.i = bitcast <16 x i8> %3 to <8 x half> # | %vcmlaq_f161.i = bitcast <16 x i8> %4 to <8 x half> # | %vcmlaq_f162.i = bitcast <16 x i8> %5 to <8 x half> # | %vcmlaq_f163.i = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %vcmlaq_f16.i, <8 x half> %vcmlaq_f161.i, <8 x half> %vcmlaq_f162.i) # | %vcmlaq_f164.i = bitcast <8 x half> %vcmlaq_f163.i to <16 x i8> # | store <16 x i8> %vcmlaq_f164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %6, ptr %__ret.i, align 16 # | %7 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcmlaq_f32(<4 x float> noundef %acc, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <4 x float>, align 16 # | %lhs.addr = alloca <4 x float>, align 16 # | %rhs.addr = alloca <4 x float>, align 16 # | store <4 x float> %acc, ptr %acc.addr, align 16 # | store <4 x float> %lhs, ptr %lhs.addr, align 16 # | store <4 x float> %rhs, ptr %rhs.addr, align 16 # | %0 = load <4 x float>, ptr %acc.addr, align 16 # | %1 = load <4 x float>, ptr %lhs.addr, align 16 # | %2 = load <4 x float>, ptr %rhs.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f32.i = bitcast <16 x i8> %3 to <4 x float> # | %vcmlaq_f321.i = bitcast <16 x i8> %4 to <4 x float> # | %vcmlaq_f322.i = bitcast <16 x i8> %5 to <4 x float> # | %vcmlaq_f323.i = call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %vcmlaq_f32.i, <4 x float> %vcmlaq_f321.i, <4 x float> %vcmlaq_f322.i) # | %vcmlaq_f324.i = bitcast <4 x float> %vcmlaq_f323.i to <16 x i8> # | store <16 x i8> %vcmlaq_f324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vcmlaq_f64(<2 x double> noundef %acc, <2 x double> noundef %lhs, <2 x double> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %acc.addr = alloca <2 x double>, align 16 # | %lhs.addr = alloca <2 x double>, align 16 # | %rhs.addr = alloca <2 x double>, align 16 # | store <2 x double> %acc, ptr %acc.addr, align 16 # | store <2 x double> %lhs, ptr %lhs.addr, align 16 # | store <2 x double> %rhs, ptr %rhs.addr, align 16 # | %0 = load <2 x double>, ptr %acc.addr, align 16 # | %1 = load <2 x double>, ptr %lhs.addr, align 16 # | %2 = load <2 x double>, ptr %rhs.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vcmlaq_f64.i = bitcast <16 x i8> %3 to <2 x double> # | %vcmlaq_f641.i = bitcast <16 x i8> %4 to <2 x double> # | %vcmlaq_f642.i = bitcast <16 x i8> %5 to <2 x double> # | %vcmlaq_f643.i = call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %vcmlaq_f64.i, <2 x double> %vcmlaq_f641.i, <2 x double> %vcmlaq_f642.i) # | %vcmlaq_f644.i = bitcast <2 x double> %vcmlaq_f643.i to <16 x i8> # | store <16 x i8> %vcmlaq_f644.i, ptr %ref.tmp.i, align 16 # | %6 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %6, ptr %__ret.i, align 16 # | %7 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcmla_rot90_f16(<4 x half> noundef %acc, <4 x half> noundef %lhs, <4 x half> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %acc.addr = alloca <4 x half>, align 8 # | %lhs.addr = alloca <4 x half>, align 8 # | %rhs.addr = alloca <4 x half>, align 8 # | store <4 x half> %acc, ptr %acc.addr, align 8 # | store <4 x half> %lhs, ptr %lhs.addr, align 8 # | store <4 x half> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x half>, ptr %acc.addr, align 8 # | %1 = load <4 x half>, ptr %lhs.addr, align 8 # | %2 = load <4 x half>, ptr %rhs.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vcmla_rot90_f16.i = bitcast <8 x i8> %3 to <4 x half> # | %vcmla_rot90_f161.i = bitcast <8 x i8> %4 to <4 x half> # | %vcmla_rot90_f162.i = bitcast <8 x i8> %5 to <4 x half> # | %vcmla_rot90_f163.i = call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v # | ... # `---data was truncated (10240/166298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instsimplify,sroa # | #0 0x0000560fdc81b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560fdc8180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560fdc81b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf84305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf8435c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf84305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf842ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fdc7b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560fdc7b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560fdc795b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560fdc4450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560fdc444dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf842eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf842ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf842ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fdc444cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c (575 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smulh.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smulh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umulh.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umulh.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umulh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmulh_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c (576 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willre # | ... # `---data was truncated (10240/273697) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056408a70615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056408a7030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056408a70689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f97c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f97ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f97c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f97c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056408a69be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056408a69bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056408a680b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056408a3300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056408a32fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f97c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f97c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f97c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056408a32fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-vls-compare-ops.c (577 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_bool( noundef %0, noundef %1) #0 { # | entry: # | %retval = alloca <8 x i8>, align 2 # | %a.addr = alloca <8 x i8>, align 2 # | %b.addr = alloca <8 x i8>, align 2 # | %a.coerce = bitcast %0 to # | %a = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %a.coerce, i64 0) # | %b.coerce = bitcast %1 to # | %b = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8( %b.coerce, i64 0) # | store <8 x i8> %a, ptr %a.addr, align 2 # | store <8 x i8> %b, ptr %b.addr, align 2 # | %2 = load <8 x i8>, ptr %a.addr, align 2 # | %3 = load <8 x i8>, ptr %b.addr, align 2 # | %cmp = icmp eq <8 x i8> %2, %3 # | %sext = sext <8 x i1> %cmp to <8 x i8> # | store <8 x i8> %sext, ptr %retval, align 2 # | %4 = load <8 x i8>, ptr %retval, align 2 # | %cast.scalable = call @llvm.vector.insert.nxv2i8.v8i8( poison, <8 x i8> %4, i64 0) # | %5 = bitcast %cast.scalable to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i8.v8i8(, <8 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i32> # | store <16 x i32> %sext, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %cmp = icmp eq <8 x i64> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i64> # | store <8 x i64> %sext, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %cmp = icmp eq <64 x i8> %0, %1 # | %sext = sext <64 x i1> %cmp to <64 x i8> # | store <64 x i8> %sext, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %cmp = icmp eq <32 x i16> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i16> # | store <32 x i16> %sext, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %cmp = icmp eq <16 x i32> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x # | ... # `---data was truncated (10240/78785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005591f377015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591f376d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591f377089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0efb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0efb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0efb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0efb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591f3705e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005591f3705c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005591f36eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005591f339a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005591f3399dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc0efb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0efb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0efb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591f3399cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c (578 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b935ab815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b935ab50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b935ab889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d2d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d2d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d2d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d2d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b935a4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b935a4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b935a32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9356e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9356e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d2d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d2d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d2d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9356e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c (579 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a8429115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a8428e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a8429189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae89d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae89d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae89d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae89d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a84226e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a84226c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a8420bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a83ebb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a83ebadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae89d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae89d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae89d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a83ebacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c (580 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv16i8(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8i16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4i32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 0, %0, i32 3) # | ret { , , , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , , , } @llvm.aarch64.sme.luti2.lane.zt.x4.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000560af14e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560af14e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560af14e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82fa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82fa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82fa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82fa431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560af147ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560af147cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560af1461b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560af11110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560af1110dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f82fa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82fa4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82fa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560af1110cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c (581 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6c5ac015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6c5abd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d6c5ac089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5283249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52832a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5283249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5283231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6c5a55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d6c5a55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d6c5a3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6c56ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6c56e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5283232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52832330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52832330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6c56e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c (582 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056156886c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615688690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056156886c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc23d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc23d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc23d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc23d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561568801e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561568801c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615687e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615684960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561568495dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc23d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc23d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc23d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561568495cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c (583 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c (584 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %v # | ... # `---data was truncated (10240/86747) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f36e0ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f36e0e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f36e0ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5164649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51646a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5164649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5164631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f36e081e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f36e081c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f36e066b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f36dd160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f36dd15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5164632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51646330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51646330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f36dd15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c (585 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c (586 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ce46bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ce46bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ce46bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfb4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfb46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfb4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfb4631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ce4654e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ce4654c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ce4639b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ce42e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ce42e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfb4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfb46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfb46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ce42e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c (587 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.orr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.orr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.orr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svorr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/52880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556940cce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556940ccb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556940cce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f066a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f066a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f066a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f066a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556940c63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556940c63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556940c48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569408f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569408f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f066a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f066a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f066a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569408f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c (588 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fsqrt.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.fsqrt.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsqrt_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.fsqrt.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055ff1cac615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff1cac30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff1cac689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa66e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa66e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa66e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa66e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff1ca5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff1ca5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff1ca40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff1c6f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff1c6efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa66e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa66e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa66e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff1c6efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c (589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9c905b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9c90580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9c905b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ae0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ae038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ae0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ae031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9c8ff0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9c8ff0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9c8fd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9c8c850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9c8c84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ae031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ae031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ae031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9c8c84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c (590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c (591 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c (592 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmopa_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umopa.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_s16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmops_u16( %pn, %pm, %zn, %zm) #0 { # | entry: # | %pn.addr = alloca , align 2 # | %pm.addr = alloca , align 2 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %pn, ptr %pn.addr, align 2 # | store %pm, ptr %pm.addr, align 2 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %pn.addr, align 2 # | %1 = load , ptr %pm.addr, align 2 # | %2 = load , ptr %zn.addr, align 16 # | %3 = load , ptr %zm.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | call void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 3, %4, %5, %2, %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umops.za32.nxv8i16(i32 immarg, , , , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d6d591515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6d59120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d6d591589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a52733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a5278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a52733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a5271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6d58aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d6d58aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d6d588fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6d553f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6d553edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8a5271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a5271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a5271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6d553ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c (593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c (594 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c11f2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c11f240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c11f2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3fcc333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3fcc38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3fcc333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3fcc31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c11ebce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c11ebcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c11ea1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c11b510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c11b50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3fcc31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3fcc31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3fcc31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c11b50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c (595 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005610774be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005610774bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005610774be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f850041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85004725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f850041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8500403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561077453e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561077453c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561077438b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005610770e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005610770e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8500404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85004050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85004050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005610770e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c (596 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595f4f3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595f4f380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595f4f3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d57933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d5798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d57933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d5791b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595f4ed0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595f4ed0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595f4eb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595f4b650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595f4b64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d5791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d5791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d5791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595f4b64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c (597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559520aae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559520aab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559520aae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bdd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bdd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bdd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bdd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559520a43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559520a43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559520a28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595206d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595206d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bdd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bdd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bdd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595206d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c (598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f7192d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555f7192a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555f7192d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc537133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc53718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc537133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc53711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f718c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555f718c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555f718a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555f715570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555f71556dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc53711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc53711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc53711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f71556cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c (599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb1880615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb188030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb1880689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d63533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d6358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d63533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d6351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb1879be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb1879bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb18780b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb184300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb1842fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d6351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d6351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d6351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb1842fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c (600 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c (601 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqincb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqincb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqincb.n32(i32 %0, i32 5, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqincb.n64(i64 %0, i32 6, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqincb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqincb.n32(i32 %0, i32 7, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqincb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqincb.n64(i64 %0, i32 8, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a84976015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a84975d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a84976089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62e6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62e68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62e6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62e6831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8496f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8496f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8496dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a84938a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a849389dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62e6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62e68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62e68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a849389cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c (602 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq2_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq2.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055fb63a0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb63a040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb63a0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa98a105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa98a15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa98a105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa98a0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb6399ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb6399cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb63981b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb636310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb63630dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa98a0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa98a0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa98a0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb63630cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c (603 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561623a3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561623a320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561623a3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1e3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1e32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1e3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1e3231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616239cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005616239cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005616239afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056162365f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056162365edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd1e3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1e32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1e32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056162365ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c (604 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecb.n32(i32 %0, i32 0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecb.n64(i64 %0, i32 1, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecb_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %0, i32 2, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecb_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %0, i32 3, i32 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555b3aaba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b3aab70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b3aaba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa631049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6310a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa631049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa631031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b3aa4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b3aa4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b3aa34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b3a6e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b3a6e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa631032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6310330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6310330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b3a6e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c (605 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/51751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f48fc0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f48fbfd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f48fc0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc39e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc39e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc39e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc39e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48fb95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f48fb95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f48fb7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f48f82a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f48f829dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc39e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc39e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc39e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f48f829cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c (606 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,102 # | ... # `---data was truncated (10240/10769) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ea1fd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ea1fd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ea1fd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe83ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe83aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe83ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe83ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ea1f68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ea1f68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ea1f4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ea1bfd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ea1bfcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe83ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe83ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe83ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ea1bfccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c (607 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, al # | ... # `---data was truncated (10240/223137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8457b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8457b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8457b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fa7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fa74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fa7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fa7431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e845748e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e845748c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e84572db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8453dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8453dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1fa7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fa74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fa74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8453dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c (608 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/83088) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056496967e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056496967b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056496967e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01c441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01c44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01c441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01c4403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564969613e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564969613c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005649695f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649692a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649692a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01c4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01c44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01c44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649692a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c (609 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv16i8.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8i16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4i32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_s64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv2i64.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u8( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | call void @llvm.aarch64.sve.st1.nxv16i8.p0( %2, %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8i16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4i32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_u64( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | call void @llvm.aarch64.sve.st1.nxv2i64.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f16( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | call void @llvm.aarch64.sve.st1.nxv8f16.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv8f16.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst1_f32( %pg, ptr noundef %base, %data) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %data, ptr %data.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %data.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.st1.nxv4f32.p0( %2, %3, ptr %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st1.nxv4f32.p0(, , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/75656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055fa6b5cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa6b5c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa6b5cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b66449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b664a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b66449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b66431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa6b560e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa6b560c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa6b545b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa6b1f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa6b1f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b66432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b664330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b664330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa6b1f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c (610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | ... # `---data was truncated (10240/12958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f79165315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7916500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f79165389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa18fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa18fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa18fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa18fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7915e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f7915e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f7915cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f79127d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f79127cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa18fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa18fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa18fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f79127ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c (612 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %v # | ... # `---data was truncated (10240/142327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d79ecb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d79ec80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d79ecb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11dca1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11dca725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11dca1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11dca03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d79e60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d79e60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d79e45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d79af50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d79af4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11dca04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11dca050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11dca050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d79af4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/AArch64/sve/nand.c (613 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnand_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nand.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nand.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000563acb17515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563acb1720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563acb17589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fa2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fa278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fa2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fa271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563acb10ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563acb10ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563acb0efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563acad9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563acad9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0fa271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fa271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fa271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563acad9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nand.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c (614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/136489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621e3ded15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621e3dea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005621e3ded89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6859a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6859aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6859a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6859a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621e3d82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621e3d82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621e3d67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621e3a170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005621e3a16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6859a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6859a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6859a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621e3a16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0 FAIL: Clang :: CodeGen/arm-neon-vget.c (615 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -target-abi apcs-gnu -target-cpu cortex-a8 -mfloat-abi soft -target-feature +soft-float-abi -ffreestanding -disable-O0-optnone -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x i32> @low_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %1, <4 x i32> %2, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <1 x i64> @low_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <2 x i64> %1, <2 x i64> %2, <1 x i32> zeroinitializer # | store <1 x i64> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @low_p8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @low_p16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x float> @low_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x float> %1, <4 x float> %2, <2 x i32> # | store <2 x float> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @high_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %1, <16 x i8> %2, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %1, <8 x i16> %2, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i16> @high_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr # | ... # `---data was truncated (10240/15571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddb951515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ddb95120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ddb951589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb13733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb1378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb13733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb1371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddb94aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ddb94aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ddb948fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ddb913f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ddb913edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb1371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb1371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb1371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddb913ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c (616 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c (617 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d0894a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d089470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d0894a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30ef049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30ef0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30ef049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30ef031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d088dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d088dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d088c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d085740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d08573dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f30ef032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30ef0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30ef0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d08573cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c (618 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555705de315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555705de00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555705de389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad22705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad2275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad22705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad226ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555705d78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555705d78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555705d5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555705a0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555705a0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad226eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad226ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad226ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555705a0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c (619 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c (620 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.cntb(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_1() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_2() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_3() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_4() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 4) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_5() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 5) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_6() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_7() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_8() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 8) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_9() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 9) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_10() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 10) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_11() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 11) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_12() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 12) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_13() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 13) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_14() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 29) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_15() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 30) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svcntb_pat_16() #0 { # | entry: # | %0 = call i64 @llvm.aarch64.sve.cntb(i32 31) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x00005578ef55215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005578ef54f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005578ef55289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3565c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3565ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3565c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3565c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578ef4e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005578ef4e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005578ef4ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005578ef17c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005578ef17bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3565c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3565c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3565c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578ef17bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c (621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dc0aca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564dc0ac70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564dc0aca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a5ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a5ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a5ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a5ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dc0a5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564dc0a5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564dc0a44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564dc06f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564dc06f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a5ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a5ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a5ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dc06f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c (622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575e341d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575e341a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575e341d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5444133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f544418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5444133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f544411b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575e33b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575e33b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575e3397b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575e30470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575e3046dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f544411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f544411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f544411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575e3046cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (623 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32x.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32x.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32x_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32x.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frint32z.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frint32z.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrint32z_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frint32z.nxv2f64( undef, %2, %1) # | # | ... # `---data was truncated (10240/23662) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005648f96af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648f96ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648f96af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabe6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabe6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabe6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabe6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648f9644e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648f9644c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648f9629b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648f92d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648f92d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fabe6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabe6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabe6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648f92d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c (624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsif.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba8848715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba884840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba8848789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fb3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fb3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fb3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fb3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba8841ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba8841cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba88401b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba880b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba880b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1fb3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fb3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fb3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba880b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c (625 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.subr.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.subr.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.subr.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsubr_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c (626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=O0 # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @foo() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @bar() #0 { # | entry: # | %v_tuple = alloca target("riscv.vector.tuple", , 2), align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @baz(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | ret target("riscv.vector.tuple", , 2) %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local target("riscv.vector.tuple", , 2) @quux(target("riscv.vector.tuple", , 2) %v_tuple) #0 { # | entry: # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | %0 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %call = call target("riscv.vector.tuple", , 2) @qux(target("riscv.vector.tuple", , 2) %0) # | ret target("riscv.vector.tuple", , 2) %call # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zicsr,+zve32x,+zvl32b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c05a23e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c05a23b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c05a23e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e59249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e592a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e59249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e59231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c05a1d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c05a1d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c05a1b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c059e680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c059e67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e59232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e592330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e592330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c059e67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c --check-prefix=AFTER_MEM2REG # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c (627 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv8i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i8.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u16( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv8i8.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sb_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i8.p0( %3, ptr %4) # | %6 = sext ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c (628 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/70863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdd0ffb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fdd0ff80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fdd0ffb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1c3231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdd0f90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fdd0f90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fdd0f75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fdd0c250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fdd0c24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1c32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdd0c24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c (629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfeb07d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dfeb07a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dfeb07d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7035c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7035ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7035c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7035c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfeb012e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dfeb012c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dfeaff7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dfeaca70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dfeaca6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7035c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7035c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7035c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfeaca6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c (630 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, %vs1, # | ... # `---data was truncated (10240/62087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601aed7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005601aed6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005601aed7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3470333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f347038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3470333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f347031b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601aed07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005601aed07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005601aececb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005601ae99c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005601ae99bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f347031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f347031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f347031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601ae99bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c (631 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | call void @llvm.aarch64.sve.st3.nxv16i8.p0( %6, %7, %8, %3, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv16i8.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s16( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %3) # | call void @llvm.aarch64.sve.st3.nxv8i16.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv8i16.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s32( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %3) # | call void @llvm.aarch64.sve.st3.nxv4i32.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv4i32.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_s64( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = alloca { , , }, align 16 # | %0 = insertvalue { , , } poison, %data.coerce0, 0 # | %1 = insertvalue { , , } %0, %data.coerce1, 1 # | %2 = insertvalue { , , } %1, %data.coerce2, 2 # | store { , , } %2, ptr %data, align 16 # | %data1 = load { , , }, ptr %data, align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store { , , } %data1, ptr %data.addr, align 16 # | %3 = load , ptr %pg.addr, align 2 # | %4 = load ptr, ptr %base.addr, align 8 # | %5 = load { , , }, ptr %data.addr, align 16 # | %6 = extractvalue { , , } %5, 0 # | %7 = extractvalue { , , } %5, 1 # | %8 = extractvalue { , , } %5, 2 # | %9 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %3) # | call void @llvm.aarch64.sve.st3.nxv2i64.p0( %6, %7, %8, %9, ptr %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.st3.nxv2i64.p0(, , , , ptr captures(none)) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svst3_u8( %pg, ptr noundef %base, %data.coerce0, %data.coerce1, %data.coerce2) #0 { # | entry: # | %data = alloca { , , }, align 16 # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %data.addr = al # | ... # `---data was truncated (10240/58378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056547f97215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056547f96f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056547f97289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa211a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa211aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa211a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa211a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056547f907e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056547f907c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056547f8ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056547f59c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056547f59bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa211a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa211a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa211a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056547f59bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c (632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560769a4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560769a480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560769a4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd72c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd72c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd72c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd72c831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607699e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607699e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607699c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607696750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560769674dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd72c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd72c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd72c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560769674cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c (633 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-b16mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bf16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv8bf16.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055da386d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da386d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da386d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41d2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41d2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41d2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41d2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da3866ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da3866ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da38653b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da383030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da38302dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41d2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41d2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41d2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da38302cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c (634 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintp.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintp.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintp_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintp.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558590b1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558590b140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558590b1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f74a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f74a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f74a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f74a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558590aace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558590aacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558590a91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585907410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558590740dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5f74a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f74a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f74a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558590740cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c (635 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.cnot.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.cnot.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.cnot.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.cnot.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.cnot.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcnot_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/addv.c (636 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/addv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.saddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.saddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.saddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i64 @llvm.aarch64.sve.uaddv.nxv16i8( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv4i32( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svaddv_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.uaddv.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uaddv.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svaddv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.faddv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.faddv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svaddv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.faddv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.faddv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svaddv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.faddv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.faddv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | a # | ... # `---data was truncated (10240/10826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,instcombine,tailcallelim -S # | #0 0x0000564c9c27215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c9c26f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c9c27289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f816d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f816d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f816d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f816d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c9c207e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c9c207c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c9c1ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c9be9c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c9be9bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f816d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f816d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f816d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c9be9bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/addv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c (637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c (638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmac # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da09b6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da09b5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da09b6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe04c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe04c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe04c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe04c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da09af7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da09af7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da09adcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da0978c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da0978bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe04c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe04c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe04c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da0978bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c (639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d0107615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d010730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d0107689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ff5f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ff5f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ff5f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ff5eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d0100be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d0100bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d00ff0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d00ca00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d00c9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ff5eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ff5eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ff5eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d00c9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c (640 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_svzero_zt() #0 { # | entry: # | call void @llvm.aarch64.sme.zero.zt(i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: write) # | declare void @llvm.aarch64.sme.zero.zt(i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "aarch64_out_zt0" "aarch64_pstate_sm_compatible" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: write) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055609abf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055609abee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055609abf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2e3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2e398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2e3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2e391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055609ab86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055609ab86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055609ab6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055609a81b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055609a81add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2e391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2e391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2e391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055609a81acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c (641 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.zipq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svzipq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.zipq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056516bacd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056516baca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056516bacd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b2d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b2d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b2d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b2d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056516ba62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056516ba62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056516ba47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056516b6f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056516b6f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b2d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b2d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b2d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056516b6f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c (642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558665e3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558665e2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558665e3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc40905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc4095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc40905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc408ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558665dc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558665dc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558665dacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558665a5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558665a5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcc408eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc408ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc408ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558665a5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c (643 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmul.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmul.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmul.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000562584c6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562584c600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562584c6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f6951b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562584bf8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562584bf8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562584bddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056258488d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056258488cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f6951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056258488ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (644 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557faff415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557faff10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557faff489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb01e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb01e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb01e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb01e831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557faf89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557faf89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557faf6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557fac1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557fac1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb01e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb01e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb01e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557fac1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c (645 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.mul.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.mul.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.mul.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmul_s8_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, pt # | ... # `---data was truncated (10240/77120) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056265c62c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056265c6290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056265c62c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb7ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb7eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb7ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb7ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056265c5c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056265c5c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056265c5a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056265c2560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056265c255dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb7ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb7ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb7ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056265c255cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c (646 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626151b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005626151ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005626151b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd90dc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd90dca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd90dc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd90dc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562615145e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562615145c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056261512ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562614dda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562614dd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd90dc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd90dc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd90dc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562614dd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c (647 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsll.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/427567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b39424f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b39424c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b39424f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5fe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5fe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5fe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5fe51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3941e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3941e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3941c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b393e790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b393e78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5fe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5fe51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5fe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b393e78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c (648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652732de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005652732db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005652732de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71d8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71d818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71d8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71d811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565273273e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565273273c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565273258b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565272f080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565272f07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f71d811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71d811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71d811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565272f07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c (649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e7af715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005646e7af40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005646e7af789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2769133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f276918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2769133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f276911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e7a8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005646e7a8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005646e7a71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646e77210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005646e7720dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f276911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f276911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f276911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e7720cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c (650 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ld1rq.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1rq.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1rq.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1rq_bf16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/11267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005603f6b3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603f6b2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603f6b3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9357533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f935758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9357533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f935751b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603f6ac7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005603f6ac7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603f6aacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005603f675c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005603f675bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f935751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f935751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f935751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603f675bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c (651 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_s16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrn_u16_u32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.uqrshrn.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.uqrshrn.x2.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqrshrun_u16_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call @llvm.aarch64.sve.sqrshrun.x2.nxv4i32( %3, %4, i32 16) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.sqrshrun.x2.nxv4i32(, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055cd1505b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd150580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd1505b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff73d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff73d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff73d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff73d4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd14ff0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd14ff0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd14fd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd14c850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd14c84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff73d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff73d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff73d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd14c84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/rounding-v8.5.c (652 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding-v8.5.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +v8.5a -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32x_f321.i = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %vrnd32x_f32.i) # | %vrnd32x_f322.i = bitcast <2 x float> %vrnd32x_f321.i to <8 x i8> # | store <8 x i8> %vrnd32x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %vrnd32xq_f32.i) # | %vrnd32xq_f322.i = bitcast <4 x float> %vrnd32xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd32z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd32z_f321.i = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %vrnd32z_f32.i) # | %vrnd32z_f322.i = bitcast <2 x float> %vrnd32z_f321.i to <8 x i8> # | store <8 x i8> %vrnd32z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd32zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd32zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %vrnd32zq_f32.i) # | %vrnd32zq_f322.i = bitcast <4 x float> %vrnd32zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd32zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64x_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64x_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64x_f321.i = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %vrnd64x_f32.i) # | %vrnd64x_f322.i = bitcast <2 x float> %vrnd64x_f321.i to <8 x i8> # | store <8 x i8> %vrnd64x_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64xq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64xq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64xq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %vrnd64xq_f32.i) # | %vrnd64xq_f322.i = bitcast <4 x float> %vrnd64xq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64xq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd64z_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd64z_f32.i = bitcast <8 x i8> %1 to <2 x float> # | %vrnd64z_f321.i = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %vrnd64z_f32.i) # | %vrnd64z_f322.i = bitcast <2 x float> %vrnd64z_f321.i to <8 x i8> # | store <8 x i8> %vrnd64z_f322.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrnd64zq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd64zq_f32.i = bitcast <16 x i8> %1 to <4 x float> # | %vrnd64zq_f321.i = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %vrnd64zq_f32.i) # | %vrnd64zq_f322.i = bitcast <4 x float> %vrnd64zq_f321.i to <16 x i8> # | store <16 x i8> %vrnd64zq_f322.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32x_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32x_f64.i = bitcast <8 x i8> %1 to <1 x double> # | %vrnd32x_f641.i = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %vrnd32x_f64.i) # | %vrnd32x_f642.i = bitcast <1 x double> %vrnd32x_f641.i to <8 x i8> # | store <8 x i8> %vrnd32x_f642.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrnd32xq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnd32xq_f64.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnd32xq_f641.i = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %vrnd32xq_f64.i) # | %vrnd32xq_f642.i = bitcast <2 x double> %vrnd32xq_f641.i to <16 x i8> # | store <16 x i8> %vrnd32xq_f642.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd32z_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrnd32z_f64.i = bitcast <8 x i8> %1 # | ... # `---data was truncated (10240/18543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bfc141915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bfc14160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bfc141989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d75a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d75aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d75a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d75a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfc13aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bfc13aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bfc1393b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bfc10430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bfc1042dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d75a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d75a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d75a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfc1042cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding-v8.5.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c (653 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556af826615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556af82630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556af826689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb01e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb01ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb01e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb01e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556af81fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556af81fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556af81e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556af7e900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556af7e8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb01e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb01e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb01e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556af7e8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c (654 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596bbbaf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596bbbac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596bbbaf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa00b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa00b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa00b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa00b031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596bbb44e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596bbb44c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596bbb29b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596bb7d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596bb7d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa00b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa00b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa00b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596bb7d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c (655 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e9ac0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e9ac020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e9ac0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbab9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbab978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbab9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbab971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e9ab9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e9ab9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e9ab7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e9a82f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e9a82edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbab971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbab971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbab971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e9a82ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-bf16-convert-intrinsics.c (656 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-convert-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +bf16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_bf16(<4 x bfloat> noundef %a) #0 { # | entry: # | %__p0_824.addr.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0_824.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0_824.addr.i, align 8 # | store <4 x i16> %1, ptr %__s0.i, align 8 # | %2 = load <8 x i8>, ptr %__s0.i, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x i16> # | %4 = zext <4 x i16> %3 to <4 x i32> # | %vshll_n.i = shl <4 x i32> %4, splat (i32 16) # | store <4 x i32> %vshll_n.i, ptr %ref.tmp1.i, align 16 # | %5 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %5, ptr %__ret.i, align 16 # | %6 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %6, ptr %tmp.i, align 16 # | %7 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %7, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret_824.i, align 16 # | %9 = load <4 x float>, ptr %__ret_824.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_low_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvtq_high_f32_bf16(<8 x bfloat> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x bfloat>, align 16 # | %__ret.i2 = alloca <4 x bfloat>, align 8 # | %__p0_824.addr.i.i = alloca <4 x bfloat>, align 8 # | %__ret_824.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <4 x i32>, align 16 # | %__ret.i.i = alloca <4 x i32>, align 16 # | %__s0.i.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i.i = alloca <16 x i8>, align 16 # | %tmp.i.i = alloca <4 x i32>, align 16 # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x bfloat>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x bfloat> %2, <8 x bfloat> %3, <4 x i32> # | store <4 x bfloat> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x bfloat>, ptr %__ret.i2, align 8 # | store <4 x bfloat> %4, ptr %__p0_824.addr.i.i, align 8 # | %5 = load <4 x i16>, ptr %__p0_824.addr.i.i, align 8 # | store <4 x i16> %5, ptr %__s0.i.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = zext <4 x i16> %7 to <4 x i32> # | %vshll_n.i.i = shl <4 x i32> %8, splat (i32 16) # | store <4 x i32> %vshll_n.i.i, ptr %ref.tmp1.i.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i.i, align 16 # | store <4 x i32> %9, ptr %__ret.i.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i.i, align 16 # | store <4 x i32> %10, ptr %tmp.i.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i.i, align 16 # | %12 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %12, ptr %__ret_824.i.i, align 16 # | %13 = load <4 x float>, ptr %__ret_824.i.i, align 16 # | store <4 x float> %13, ptr %__ret.i, align 16 # | %14 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcvt_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | store <4 x bfloat> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp.i, align 8 # | store <4 x bfloat> %4, ptr %__ret.i, align 8 # | %5 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_low_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x bfloat> # | %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> # | store <8 x bfloat> %4, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvtq_high_bf16_f32(<8 x bfloat> noundef %inactive, <4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x bfloat>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %inactive.addr = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <8 x bfloat> %inactive, ptr %inactive.addr, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <8 x bfloat>, ptr %inactive.addr, align 16 # | %1 = load <4 x float>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x bfloat> # | %5 = shufflevector <8 x bfloat> %4, <8 x bfloat> poison, <4 x i32> # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = fptrunc <4 x float> %6 to <4 x bfloat> # | %8 = shufflevector <4 x bfloat> %5, <4 x bfloat> %7, <8 x i32> # | store <8 x bfloat> %8, ptr %ref.tmp.i, align 16 # | %9 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %9, ptr %__ret.i, align 16 # | %10 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_vcvth_bf16_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca bfloat, align 2 # | %ref.tmp.i = alloca bfloat, align 2 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | store bfloat %2, ptr %ref.tmp.i, align 2 # | %3 = load bfloat, ptr %ref.tmp.i, align 2 # | store bfloat %3, ptr %__ret.i, align 2 # | %4 = load bfloat, ptr %__ret.i, align 2 # | ret bfloat %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtah_f32_bf16(bfloat noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca bfloat, align 2 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca i32, align 4 # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load # | ... # `---data was truncated (10240/10974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055c9bf01415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9bf0110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9bf01489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5841d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5841d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5841d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5841d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9befa9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9befa9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9bef8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9bec3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9bec3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5841d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5841d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5841d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9bec3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK,CHECK-A64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-convert-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c (657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ecedb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ecedb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ecedb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d38a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d38aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d38a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d38a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558eced4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558eced4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558eced32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ece9e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ece9e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d38a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d38a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d38a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ece9e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c (658 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_f16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8f16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_bf16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.fmlal.vg2x2.nxv8bf16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_u16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.umlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla2_s16(i32 noundef %slice_base, %zn.coerce0, %zn.coerce1, %zm.coerce0, %zm.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zm = alloca { , }, align 16 # | %slice_base.addr = alloca i32, align 4 # | %zn.addr = alloca { , }, align 16 # | %zm.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | %2 = insertvalue { , } poison, %zm.coerce0, 0 # | %3 = insertvalue { , } %2, %zm.coerce1, 1 # | store { , } %3, ptr %zm, align 16 # | %zm2 = load { , }, ptr %zm, align 16 # | store i32 %slice_base, ptr %slice_base.addr, align 4 # | store { , } %zn1, ptr %zn.addr, align 16 # | store { , } %zm2, ptr %zm.addr, align 16 # | %4 = load i32, ptr %slice_base.addr, align 4 # | %5 = load { , }, ptr %zn.addr, align 16 # | %6 = extractvalue { , } %5, 0 # | %7 = extractvalue { , } %5, 1 # | %8 = load { , }, ptr %zm.addr, align 16 # | %9 = extractvalue { , } %8, 0 # | %10 = extractvalue { , } %8, 1 # | call void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32 %4, %6, %7, %9, %10) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem1: readwrite) # | declare void @llvm.aarch64.sme.smlal.vg2x2.nxv8i16(i32, , , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svmla4 # | ... # `---data was truncated (10240/73614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055d650b4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d650b400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d650b4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6939133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f693918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6939133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f693911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d650ad8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d650ad8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d650abdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d65076d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d65076cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f693911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f693911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f693911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d65076ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c (659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d9301415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d930110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d9301489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f797b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f797b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f797b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f797b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d92fa9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d92fa9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d92f8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d92c3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d92c3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f797b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f797b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f797b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d92c3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c (660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2b8e3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2b8e380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2b8e3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2dc733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2dc78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2dc733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2dc71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2b8dd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2b8dd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2b8db5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2b8a650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2b8a64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc2dc71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2dc71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2dc71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2b8a64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c (661 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e07038a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0703870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e07038a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fded0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fded055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fded0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fded04ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e07031fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e07031fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e070304b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e06ffb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e06ffb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fded04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fded04ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fded04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e06ffb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c (662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b87396c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8739690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b87396c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fababb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fababb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fababb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fababb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b873901e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b873901c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8738e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8735960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b873595dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fababb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fababb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fababb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b873595cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c (663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c (664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcabb2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fcabb290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fcabb2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fead2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fead255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fead2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fead24ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcabac1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fcabac1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fcabaa6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fcab7560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fcab755dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fead24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fead24ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fead24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcab755cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c (665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c (666 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facge.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svacle_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facge.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556ed2c1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ed2c180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ed2c1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc443133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc44318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc443133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc44311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ed2bb0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ed2bb0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ed2b95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ed28450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ed2844dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc44311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc44311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc44311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ed2844cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c (667 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9b14bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9b14b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9b14bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa853c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa853c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa853c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa853c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9b1450e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9b1450c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9b1435b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9b10e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e9b10e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa853c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa853c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa853c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9b10e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c (668 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv8f16(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_z_1( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %4, %2, i32 270) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv4f32(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %4, %2, i32 90) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fcadd.nxv2f64(, , , i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv4f32( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f64_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv2f64( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fcadd.nxv8f16( %3, %1, %2, i32 90) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcadd_f32_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.ad # | ... # `---data was truncated (10240/12234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562aa0c0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562aa0c010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562aa0c0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8226f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8226f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8226f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8226f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aa0b99e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562aa0b99c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562aa0b7eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562aa082e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562aa082ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8226f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8226f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8226f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aa082dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (669 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_0( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 0 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_1( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 1 # | ret { , , , } %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svset4_b_3( %tuple.coerce0, %tuple.coerce1, %tuple.coerce2, %tuple.coerce3, %x) #0 { # | entry: # | %tuple = alloca { , , , }, align 2 # | %tuple.addr = alloca { , , , }, align 2 # | %x.addr = alloca , align 2 # | %0 = insertvalue { , , , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , , , } %0, %tuple.coerce1, 1 # | %2 = insertvalue { , , , } %1, %tuple.coerce2, 2 # | %3 = insertvalue { , , , } %2, %tuple.coerce3, 3 # | store { , , , } %3, ptr %tuple, align 2 # | %tuple1 = load { , , , }, ptr %tuple, align 2 # | store { , , , } %tuple1, ptr %tuple.addr, align 2 # | store %x, ptr %x.addr, align 2 # | %4 = load { , , , }, ptr %tuple.addr, align 2 # | %5 = load , ptr %x.addr, align 2 # | %6 = insertvalue { , , , } %4, %5, 3 # | ret { , , , } %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e41472115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e41471e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e41472189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7182249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71822a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7182249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7182231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4146b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e4146b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e41469bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e41434b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e41434add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7182232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71822330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71822330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e41434acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c (670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c1d9c2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c1d9c220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c1d9c2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2519733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f251978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2519733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f251971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c1d9bbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c1d9bbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c1d9b9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c1d984f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c1d984edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f251971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f251971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f251971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c1d984ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c (671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f976ef415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f976ef10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f976ef489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f718c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f718c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f718c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f718c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f976e89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f976e89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f976e6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f976b1e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f976b1ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f718c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f718c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f718c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f976b1dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c (672 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a22f68115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a22f67e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a22f68189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6df3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6df378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6df3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6df371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22f616e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a22f616c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a22f5fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a22f2ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a22f2aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6df371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6df371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6df371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a22f2aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c (673 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abf213b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055abf21380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055abf213b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff537649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5376a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff537649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff537631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abf20d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055abf20d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055abf20b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055abf1d650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055abf1d64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff537632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5376330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5376330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abf1d64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c (674 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrw.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrw_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrw.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000564d9886015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d9885d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d9886089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2016f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2016f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2016f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2016f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d987f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d987f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d987dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d9848a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d98489dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2016f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2016f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2016f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d98489cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-misc.c (675 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vcgez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = icmp sge <8 x i8> %1, zeroinitializer # | %vcgez.i = sext <8 x i1> %2 to <8 x i8> # | store <8 x i8> %vcgez.i, ptr %ref.tmp.i, align 8 # | %3 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %3, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %3 = icmp sge <4 x i16> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %3 = icmp sge <2 x i32> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x i64> # | %3 = icmp sge <1 x i64> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcgezq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = icmp sge <16 x i8> %1, zeroinitializer # | %vcgez.i = sext <16 x i1> %2 to <16 x i8> # | store <16 x i8> %vcgez.i, ptr %ref.tmp.i, align 16 # | %3 = load <16 x i8>, ptr %ref.tmp.i, align 16 # | store <16 x i8> %3, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x i16> # | %3 = icmp sge <8 x i16> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x i32> # | %3 = icmp sge <4 x i32> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x i64> # | %3 = icmp sge <2 x i64> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcgez_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x float> # | %3 = fcmp oge <2 x float> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i32> # | store <2 x i32> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %4, ptr %__ret.i, align 8 # | %5 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcgez_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <1 x double> # | %3 = fcmp oge <1 x double> %2, zeroinitializer # | %vcgez.i = sext <1 x i1> %3 to <1 x i64> # | store <1 x i64> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcgezq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fcmp oge <4 x float> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i32> # | store <4 x i32> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %4, ptr %__ret.i, align 16 # | %5 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcgezq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <2 x double> # | %3 = fcmp oge <2 x double> %2, zeroinitializer # | %vcgez.i = sext <2 x i1> %3 to <2 x i64> # | store <2 x i64> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vclez_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, ali # | ... # `---data was truncated (10240/217310) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055958b04f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055958b04c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055958b04f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3350733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f335078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3350733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f335071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055958afe4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055958afe4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055958afc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055958ac790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055958ac78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f335071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f335071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f335071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055958ac78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c (676 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_mf8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv16i8(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8i16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8f16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_bf16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv8bf16(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 immarg, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4i32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svluti2_lane_zt_f32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 0, %0, i32 7) # | ret { , } %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(target_mem0: read) # | declare { , } @llvm.aarch64.sme.luti2.lane.zt.x2.nxv4f32(i32 immarg, , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_in_zt0" "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(target_mem0: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055dcf6dd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dcf6dd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dcf6dd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c9b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c9b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c9b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c9b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcf6d6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dcf6d6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dcf6d51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dcf6a010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dcf6a00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c9b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c9b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c9b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcf6a00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c (677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055887826515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588782620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055887826589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc46f61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc46f6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc46f61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc46f603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588781fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588781fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588781dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558877e8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558877e8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc46f604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc46f6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc46f6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558877e8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c (678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc119c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc119c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc119c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff56ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff56ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc1195ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc1195ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc11943b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc115f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc115f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff56ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc115f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c (679 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c (680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/150649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624ed72715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624ed7240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624ed72789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0203c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0203ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0203c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0203c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624ed6bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624ed6bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624ed6a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624ed3510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624ed350dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0203c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0203c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0203c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624ed350cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c (681 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056441cc7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056441cc760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056441cc7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1dbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1dbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1dbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1dbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056441cc0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056441cc0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056441cbf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056441c8a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056441c8a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1dbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1dbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1dbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056441c8a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c (682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c (683 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nx # | ... # `---data was truncated (10240/75125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055790cdcd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055790cdca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055790cdcd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64dca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64dcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64dca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64dca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055790cd62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055790cd62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055790cd47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055790c9f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055790c9f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64dca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64dca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64dca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055790c9f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c (684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a523b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a523ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a523b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f279a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f279a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f279a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f279a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a52346e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a52346c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a5232bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a51fdb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a51fdadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f279a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f279a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f279a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a51fdacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c (685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d02e2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d02e270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d02e2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f377aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f377aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f377aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f377aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d02dbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d02dbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d02da4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d02a540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d02a53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f377aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f377aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f377aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d02a53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c (686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c (687 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv8f16( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv8f16(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv4f32(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_f64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %2, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.facgt.nxv2f64(, , ) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f32( %pg, %op1, float noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca float, align 4 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store float %op2, ptr %op2.addr, align 4 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %.splatinsert = insertelement poison, float %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv4f32( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %4) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svaclt_n_f64( %pg, %op1, double noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca double, align 8 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store double %op2, ptr %op2.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load double, ptr %op2.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %.splatinsert = insertelement poison, double %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.facgt.nxv2f64( %3, %.splat, %1) # | %5 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %4) # | ret %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005644e194c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644e19490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644e194c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4f1e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4f1e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4f1e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4f1e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644e18e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644e18e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644e18c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644e15760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644e1575dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff4f1e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4f1e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4f1e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644e1575cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c (688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | ... # `---data was truncated (10240/30866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c62b5f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c62b5f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c62b5f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdaba305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdaba35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdaba305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdaba2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c62b58de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c62b58dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c62b572b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c62b2220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c62b221dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdaba2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdaba2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdaba2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c62b221cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c (689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056245cbf715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056245cbf40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056245cbf789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c67b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c67b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c67b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c67b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056245cb8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056245cb8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056245cb71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056245c8210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056245c820dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c67b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c67b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c67b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056245c820cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c (690 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055657398f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055657398c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055657398f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f728cb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f728cb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f728cb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f728caed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556573924e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556573924c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556573909b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005565735b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005565735b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f728caeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f728caef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f728caef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565735b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c (691 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fbae2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563fbae260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563fbae2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe579449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5794a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe579449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe579431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fbadbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563fbadbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563fbada3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563fbaa530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563fbaa52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe579432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5794330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5794330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fbaa52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c (692 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055986945f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055986945c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055986945f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55c4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55c4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55c4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55c4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598693f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598693f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598693d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598690890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559869088dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f55c4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55c4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55c4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559869088cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c (693 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.firstp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svfirstp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.firstp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.firstp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055692efb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055692efb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055692efb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6aafb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6aafb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6aafb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6aafb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055692ef4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055692ef4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055692ef30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055692ebe00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055692ebdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6aafb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6aafb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6aafb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055692ebdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c (694 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32, i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32, i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 1, i32 0, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaq_u32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 1, i32 0, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 0, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlaldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 0, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 0, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 0, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldaxvaq_s16(i64 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = load <8 x i16>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v8i16(i32 0, i32 1, i32 1, i32 %3, i32 %2, <8 x i16> %4, <8 x i16> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vmlsldavaxq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = load <4 x i32>, ptr %c.addr, align 8 # | %6 = call { i32, i32 } @llvm.arm.mve.vmlldava.v4i32(i32 0, i32 1, i32 1, i32 %3, i32 %2, <4 x i32> %4, <4 x i32> %5) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vrmlaldavhaq_s32(i64 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, al # | ... # `---data was truncated (10240/58468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000557f4d8d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557f4d8d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557f4d8d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae75049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae75049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae75031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f4d869e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557f4d869c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557f4d84eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557f4d4fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557f4d4fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae75032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae750330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f4d4fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mfp8.c (695 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mfp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -emit-llvm -triple aarch64-arm-none-eabi -target-feature -fp8 -target-feature +neon -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_ret_mfloat8x16_t(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_ret_mfloat8x8_t(<8 x i8> %v) #0 { # | entry: # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @func1n(<1 x i8> %mfp8) #0 { # | entry: # | %mfp8.addr = alloca <1 x i8>, align 1 # | %f1n = alloca [10 x <1 x i8>], align 1 # | store <1 x i8> %mfp8, ptr %mfp8.addr, align 1 # | %0 = load <1 x i8>, ptr %mfp8.addr, align 1 # | %arrayidx = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | store <1 x i8> %0, ptr %arrayidx, align 1 # | %arrayidx1 = getelementptr inbounds [10 x <1 x i8>], ptr %f1n, i64 0, i64 2 # | %1 = load <1 x i8>, ptr %arrayidx1, align 1 # | ret <1 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i8> @test_extract_element(<16 x i8> %x, i32 noundef %i) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | ret <1 x i8> %mfp8ext # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_insert_element(<16 x i8> %x, i32 noundef %i, <1 x i8> %v) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | %v.addr = alloca <1 x i8>, align 1 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | store <1 x i8> %v, ptr %v.addr, align 1 # | %0 = load <1 x i8>, ptr %v.addr, align 1 # | %1 = load i32, ptr %i.addr, align 4 # | %2 = load <16 x i8>, ptr %x.addr, align 16 # | %3 = bitcast <1 x i8> %0 to i8 # | %vecins = insertelement <16 x i8> %2, i8 %3, i32 %1 # | store <16 x i8> %vecins, ptr %x.addr, align 16 # | %4 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp8" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S --passes=mem2reg # | #0 0x00005620002a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620002a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005620002a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd19f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd19f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd19f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd19f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056200023be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056200023bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562000220b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561fffed00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561fffecfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd19f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd19f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd19f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561fffecfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mfp8.c --check-prefixes=CHECK-C # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c (696 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb491a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb491a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb491a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f050cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f050cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f050cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f050cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb49138e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb49138c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb4911db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb48dcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb48dccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f050cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f050cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f050cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb48dcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c (697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c (698 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = al # | ... # `---data was truncated (10240/97675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056078681f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056078681c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056078681f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa908933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa90898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa908933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa90891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607867b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607867b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560786799b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607864490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560786448dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa90891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa90891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa90891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560786448cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c (699 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzpq1.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzpq1_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzpq1.nxv16i8( %0, %1) # | ret % # | ... # `---data was truncated (10240/10910) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055e5aa5ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5aa5a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5aa5ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16bf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16bf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16bf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16bf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5aa540e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5aa540c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5aa525b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5aa1d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5aa1d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f16bf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16bf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16bf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5aa1d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c (700 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/79071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056337862615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633786230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056337862689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faef4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faef4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faef4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faef4eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633785bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633785bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633785a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633782500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056337824fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faef4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faef4eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faef4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056337824fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c (701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3 # | ... # `---data was truncated (10240/14330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fab666115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fab665e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fab666189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8f5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8f598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8f5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8f591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fab65f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fab65f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fab65dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fab628b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fab628add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe8f591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8f591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8f591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fab628acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c (702 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da54c8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da54c8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da54c8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41cb333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41cb38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41cb333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41cb31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da54c22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da54c22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da54c07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da548b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da548b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41cb31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41cb31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41cb31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da548b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-fp16fml.c (703 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-fp16fml.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_low3.i = call <2 x float> @llvm.aarch64.neon.fmlal.v2f32.v4f16(<2 x float> %vfmlal_low.i, <4 x half> %vfmlal_low1.i, <4 x half> %vfmlal_low2.i) # | store <2 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_low_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_low.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_low1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_low2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_low3.i = call <2 x float> @llvm.aarch64.neon.fmlsl.v2f32.v4f16(<2 x float> %vfmlsl_low.i, <4 x half> %vfmlsl_low1.i, <4 x half> %vfmlsl_low2.i) # | store <2 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlal_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlal_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlal_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlal_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlal_high3.i = call <2 x float> @llvm.aarch64.neon.fmlal2.v2f32.v4f16(<2 x float> %vfmlal_high.i, <4 x half> %vfmlal_high1.i, <4 x half> %vfmlal_high2.i) # | store <2 x float> %vfmlal_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfmlsl_high_f16(<2 x float> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vfmlsl_high.i = bitcast <8 x i8> %3 to <2 x float> # | %vfmlsl_high1.i = bitcast <8 x i8> %4 to <4 x half> # | %vfmlsl_high2.i = bitcast <8 x i8> %5 to <4 x half> # | %vfmlsl_high3.i = call <2 x float> @llvm.aarch64.neon.fmlsl2.v2f32.v4f16(<2 x float> %vfmlsl_high.i, <4 x half> %vfmlsl_high1.i, <4 x half> %vfmlsl_high2.i) # | store <2 x float> %vfmlsl_high3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlal_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlal_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlal_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlal_low3.i = call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %vfmlal_low.i, <8 x half> %vfmlal_low1.i, <8 x half> %vfmlal_low2.i) # | store <4 x float> %vfmlal_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlslq_low_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vfmlsl_low.i = bitcast <16 x i8> %3 to <4 x float> # | %vfmlsl_low1.i = bitcast <16 x i8> %4 to <8 x half> # | %vfmlsl_low2.i = bitcast <16 x i8> %5 to <8 x half> # | %vfmlsl_low3.i = call <4 x float> @llvm.aarch64.neon.fmlsl.v4f32.v8f16(<4 x float> %vfmlsl_low.i, <8 x half> %vfmlsl_low1.i, <8 x half> %vfmlsl_low2.i) # | store <4 x float> %vfmlsl_low3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmlalq_high_f16(<4 x float> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = allo # | ... # `---data was truncated (10240/162735) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005606f6c8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005606f6c830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005606f6c8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6895049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68950a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6895049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6895031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606f6c1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005606f6c1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005606f6c00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005606f68b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005606f68afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6895032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68950330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68950330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606f68afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-fp16fml.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c (704 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638c38c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638c38c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005638c38c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05dbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05dbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05dbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05dbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638c3859e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638c3859c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638c383eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638c34ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638c34eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f05dbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05dbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05dbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638c34edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c (705 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalb(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vmlalt(<8 x half> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %vd.addr = alloca <8 x half>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <8 x half> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x half>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlal.i = bitcast <16 x i8> %4 to <8 x half> # | %vmlal1.i = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %vmlal.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %vmlal1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlallbt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltb(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %vmlall.i = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %vmlall.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlalltt(<4 x float> noundef %vd, <16 x i8> %vn, <16 x i8> %vm, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %vd.addr = alloca <4 x float>, align 16 # | %vn.addr = alloca <16 x i8>, align 16 # | %vm.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <4 x float> %vd, ptr %vd.addr, align 16 # | store <16 x i8> %vn, ptr %vn.addr, align 16 # | store <16 x i8> %vm, ptr %vm.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <4 x float>, ptr %vd.addr, align 16 # | %1 = load <16 x i8>, ptr %vn.addr, align 16 # | %2 = load <16 x i8>, ptr %vm.addr, align 16 # | %3 = load i64, ptr %fpm.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 # | ... # `---data was truncated (10240/35980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000558d042b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d042b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d042b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb263b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb263b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb263b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb263aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d0424ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d0424cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d04231b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d03ee10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d03ee0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb263aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb263aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb263aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d03ee0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c (706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c (707 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f175f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f175ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f175f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2297849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2297849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2297831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f17585e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f17585c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f1756ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f1721a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f17219dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2297832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22978330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f17219cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c (708 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558734d7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558734d720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558734d7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bde933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bde98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bde933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bde91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558734d0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558734d0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558734cefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055873499f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055873499edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4bde91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bde91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bde91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055873499ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c (709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055875638315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587563800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055875638389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf4e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf4e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf4e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf4e831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558756318e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558756318c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587562fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558755fad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558755facdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf4e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf4e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf4e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558755faccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c (710 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c (711 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_any( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.any.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_first( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.first.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.first.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i1 @test_svptest_last( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i1 @llvm.aarch64.sve.ptest.last.nxv16i1( %0, %1) # | ret i1 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i1 @llvm.aarch64.sve.ptest.last.nxv16i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555a2163815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a216350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a2163889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb57649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb576a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb57649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb57631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a215cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a215cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a215b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a212620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a21261dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdb57632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb576330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb576330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a21261cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c (712 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c (713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fab42215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562fab41f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562fab42289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23b2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23b24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23b2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23b2431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fab3b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562fab3b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562fab39cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562fab04c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562fab04bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23b2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23b24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23b24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fab04bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c (714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c (715 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ad396915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559ad39660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559ad396989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7bb505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7bb55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7bb505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7bb4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ad38fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559ad38fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559ad38e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559ad35930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559ad3592dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa7bb4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7bb4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7bb4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ad3592cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c (716 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c (717 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055654325515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005565432520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055654325589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b91733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b9178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b91733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b9171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565431eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005565431eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005565431cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556542e7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556542e7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b9171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b9171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b9171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556542e7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c (718 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.abs.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.abs.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.abs.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.abs.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.abs.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svabs_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005573845ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573845ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005573845ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e0e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e0e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e0e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e0e231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557384582e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557384582c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557384567b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573842170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557384216dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e0e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e0e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e0e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557384216cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c (719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591020ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591020ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591020ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01eab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01eab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01eab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01eab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559102082e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559102082c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559102067b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559101d170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559101d16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01eab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01eab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01eab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559101d16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c (720 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a94b6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a94b5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a94b6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1272b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1272b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1272b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1272aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a94af6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a94af6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a94adbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a9478b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a9478add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1272aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1272aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1272aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a9478acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c (721 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d73b6fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d73b6fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d73b6fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff04e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff04e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff04e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff04e203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d73b692e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d73b692c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d73b677b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d73b3270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d73b326dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff04e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff04e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff04e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d73b326cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c (722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c (723 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643e16d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643e16ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643e16d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fedd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fedd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fedd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fedd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643e1666e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643e1666c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643e164bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643e12fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643e12fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fedd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fedd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fedd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643e12facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c (724 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call i64 @llvm.aarch64.sve.lastp.nxv16i1( %0, %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv8i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv8i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv4i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv4i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastp_b64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call i64 @llvm.aarch64.sve.lastp.nxv2i1( %2, %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastp.nxv2i1(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b17fd4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b17fd490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b17fd4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb768733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb76878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb768733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb76871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b17fce1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b17fce1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b17fcc6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b17f9760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b17f975dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb76871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb76871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb76871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b17f975cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c (725 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.neg.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.neg.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.neg.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s8_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.neg.nxv16i8( undef, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.neg.nxv8i16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svneg_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 # | ... # `---data was truncated (10240/20016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055841e27f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055841e27c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055841e27f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29e0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29e00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29e0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29e0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055841e214e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055841e214c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055841e1f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055841dea90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055841dea8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f29e0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29e00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29e00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055841dea8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c (726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b0907a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b090770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b0907a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd3a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd3a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd3a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd3a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b0900fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b0900fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b08ff4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b08ca40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b08ca3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd3a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd3a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd3a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b08ca3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c (727 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116957) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cea36415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557cea3610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557cea36489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d9f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d9f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d9f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d9f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cea2f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557cea2f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557cea2deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557ce9f8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557ce9f8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d9f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d9f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d9f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ce9f8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c (728 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c (729 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_s64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u8( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.sel.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8i16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u32( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv4i32( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_u64( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv2i64( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svsel_f16( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.sel.nxv8f16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sel.nxv8f16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/15264) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x0000563219f5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563219f4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563219f5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f723be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f723bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f723be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f723be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563219ee7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563219ee7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563219eccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563219b7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563219b7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f723be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f723be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f723be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563219b7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu (730 of 27911) ******************** TEST 'Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple spirv64-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=CHECK-SPIRV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -emit-llvm -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu -disable-O0-optnone -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | %struct.S = type { ptr, ptr } # | %struct.T = type { [2 x ptr] } # | %struct.SS = type { ptr } # | # | @__hip_cuid_ = addrspace(1) global i8 0 # | @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel1Pi(ptr addrspace(1) noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel2Ri(ptr addrspace(1) noundef nonnull align 4 dereferenceable(4) %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8, !nonnull !3, !align !4 # | %1 = load i32, ptr %0, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel3PU3AS2iPU3AS1i(ptr addrspace(2) noundef %x, ptr addrspace(1) noundef %y) #0 { # | entry: # | %x.addr = alloca ptr addrspace(2), align 8, addrspace(5) # | %y.addr = alloca ptr addrspace(1), align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | %y.addr.ascast = addrspacecast ptr addrspace(5) %y.addr to ptr # | store ptr addrspace(2) %x, ptr %x.addr.ascast, align 8 # | store ptr addrspace(1) %y, ptr %y.addr.ascast, align 8 # | %0 = load ptr addrspace(2), ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr addrspace(2) %0, i64 0 # | %1 = load i32, ptr addrspace(2) %arrayidx, align 4 # | %2 = load ptr addrspace(1), ptr %y.addr.ascast, align 8 # | %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %2, i64 0 # | store i32 %1, ptr addrspace(1) %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline nounwind # | define dso_local void @_Z4funcPi(ptr noundef %x) #1 { # | entry: # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr %x, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel41S(ptr addrspace(4) noundef byref(%struct.S) align 8 %0) #0 { # | entry: # | %s = alloca %struct.S, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %s, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %s.ascast = addrspacecast ptr addrspace(5) %s to ptr # | %x = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %y = getelementptr inbounds nuw %struct.S, ptr %s.ascast, i32 0, i32 1 # | %3 = load ptr, ptr %y, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %4, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) noalias writeonly captures(none), ptr addrspace(4) noalias readonly captures(none), i64, i1 immarg) #2 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel5P1S(ptr addrspace(1) noundef %s.coerce) #0 { # | entry: # | %s = alloca ptr, align 8, addrspace(5) # | %s.addr = alloca ptr, align 8, addrspace(5) # | %s.addr.ascast = addrspacecast ptr addrspace(5) %s.addr to ptr # | store ptr addrspace(1) %s.coerce, ptr addrspace(5) %s, align 8 # | %s1 = load ptr, ptr addrspace(5) %s, align 8 # | store ptr %s1, ptr %s.addr.ascast, align 8 # | %0 = load ptr, ptr %s.addr.ascast, align 8 # | %x = getelementptr inbounds nuw %struct.S, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %x, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %1, i64 0 # | %2 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | %3 = load ptr, ptr %s.addr.ascast, align 8 # | %y = getelementptr inbounds nuw %struct.S, ptr %3, i32 0, i32 1 # | %4 = load ptr, ptr %y, align 8 # | %arrayidx2 = getelementptr inbounds float, ptr %4, i64 0 # | %5 = load float, ptr %arrayidx2, align 4 # | %add = fadd contract float %5, 1.000000e+00 # | store float %add, ptr %arrayidx2, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel61T(ptr addrspace(4) noundef byref(%struct.T) align 8 %0) #0 { # | entry: # | %t = alloca %struct.T, align 8, addrspace(5) # | call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) align 8 %t, ptr addrspace(4) align 8 %0, i64 16, i1 false) # | %t.ascast = addrspacecast ptr addrspace(5) %t to ptr # | %x = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x ptr], ptr %x, i64 0, i64 0 # | %1 = load ptr, ptr %arrayidx, align 8 # | %arrayidx1 = getelementptr inbounds float, ptr %1, i64 0 # | %2 = load float, ptr %arrayidx1, align 4 # | %add = fadd contract float %2, 1.000000e+00 # | store float %add, ptr %arrayidx1, align 4 # | %x2 = getelementptr inbounds nuw %struct.T, ptr %t.ascast, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x ptr], ptr %x2, i64 0, i64 1 # | %3 = load ptr, ptr %arrayidx3, align 8 # | %arrayidx4 = getelementptr inbounds float, ptr %3, i64 0 # | %4 = load float, ptr %arrayidx4, align 4 # | %add5 = fadd contract float %4, 2.000000e+00 # | store float %add5, ptr %arrayidx4, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel7Pi(ptr addrspace(1) noalias noundef %x.coerce) #0 { # | entry: # | %x = alloca ptr, align 8, addrspace(5) # | %x.addr = alloca ptr, align 8, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store ptr addrspace(1) %x.coerce, ptr addrspace(5) %x, align 8 # | %x1 = load ptr, ptr addrspace(5) %x, align 8 # | store ptr %x1, ptr %x.addr.ascast, align 8 # | %0 = load ptr, ptr %x.addr.ascast, align 8 # | %arrayidx = getelementptr inbounds i32, ptr %0, i64 0 # | %1 = load i32, ptr %arrayidx, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %arrayidx, align 4 # | ret void # | } # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind # | define dso_local amdgpu_kernel void @_Z7kernel82SS(ptr addrspace(1) %a.coerce) #0 { # | entry: # | %a = alloca %struct.SS, align 8, addrspace(5) # | %coerce.dive = getelementptr inbounds nuw %struct.SS, ptr addrspace(5) %a, i32 0, i32 0 # | store ptr addrspace(1) %a.coerce, ptr addrspace(5) %coerce.dive, align 8 # | %a.ascast = addrspacecast ptr addrspace(5) %a to ptr # | %x = getelementptr inbounds nuw %struct.SS, ptr %a.ascast, i32 0, i32 0 # | %0 = load ptr, ptr %x, align 8 # | %1 = load float, ptr %0, align 4 # | %add = fadd contract float %1, 3.000000e+00 # | store float %add, ptr %0, align 4 # | ret void # | } # | # | attributes #0 = { convergent mustprogress noinline norecurse nounwind "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { convergent mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !1 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !2 = !{!"clang version 24.0.0"} # | !3 = !{} # | !4 = !{i64 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x00005654d8d3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005654d8d2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005654d8d3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9d9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9d998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9d9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9d991b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654d8cc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005654d8cc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005654d8cacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654d895c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005654d895bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff9d991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9d991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9d991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654d895bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu --check-prefixes=OPT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c (731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/67482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1a478c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1a47890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1a478c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2c9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2c9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2c9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2c9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1a4721e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1a4721c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1a4706b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1a43b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1a43b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb2c9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2c9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2c9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1a43b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c (732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb980de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb980db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb980de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1467133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f146718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1467133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f146711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb98073e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb98073c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb98058b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb97d080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb97d07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f146711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f146711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f146711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb97d07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c (733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d73d2a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d73d29d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d73d2a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cdd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cdd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cdd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cdd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d73d235e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d73d235c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d73d21ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d73ceca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d73cec9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8cdd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cdd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cdd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d73cec9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c (734 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563df843815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563df84350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563df843889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b3a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b3a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b3a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b3a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563df83cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563df83cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563df83b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563df80620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563df8061dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b3a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b3a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b3a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563df8061cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c (735 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32( %0, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64_m( %zn, %pn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %pn.addr = alloca , align 2 # | store %zn, ptr %zn.addr, align 16 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %pn.addr, align 2 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %3 = call @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64( %0, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %2 = call @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64_z( %pn) #0 { # | entry: # | %pn.addr = alloca , align 2 # | store %pn, ptr %pn.addr, align 2 # | %0 = load , ptr %pn.addr, align 2 # | %1 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | ... # `---data was truncated (10240/11780) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055739c7c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055739c7c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055739c7c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f551cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f551cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f551cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f551cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055739c75ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055739c75ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055739c743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055739c3f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055739c3f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f551cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f551cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f551cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055739c3f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c (736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e25f5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563e25f580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563e25f5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbca905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbca95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbca905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbca8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e25ef0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563e25ef0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563e25ed5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563e25b850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563e25b84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffbca8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbca8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbca8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e25b84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c (737 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.smin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_s64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.smin.nxv2i64( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.smin.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u8_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = select %0, %1, zeroinitializer # | %4 = call @llvm.aarch64.sve.umin.nxv16i8( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv8i16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u32_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.umin.nxv4i32( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.umin.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_u64_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = select %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_min.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c (738 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2p2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8i16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_mf8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.compact.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8f16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svcompact_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.compact.nxv8bf16( %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.compact.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2p2" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000555da38c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555da38c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555da38c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f454db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f454db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f454db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f454db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555da385de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555da385dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555da3842b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555da34f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555da34f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f454db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f454db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f454db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555da34f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c (739 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c (740 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/97240) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c0a2d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c0a2d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c0a2d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febda41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febda4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febda41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febda403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c0a26ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c0a26ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c0a24fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c09eff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c09efedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007febda404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febda4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febda4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c09efecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c (741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a2d48a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557a2d4870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557a2d48a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b3c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b3c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b3c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b3c031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a2d41fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557a2d41fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557a2d404b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557a2d0b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557a2d0b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b3c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b3c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b3c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a2d0b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c (742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c (743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | sto # | ... # `---data was truncated (10240/102864) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd25b8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd25b8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd25b8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc663f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc663f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc663f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc663f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd25b23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd25b23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd25b08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd257b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd257b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc663f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc663f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc663f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd257b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c (744 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux-gnu -target-feature +neon -target-feature +v8.1a -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_laneq_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_790 = alloca <4 x i16>, align 8 # | %__s0_790 = alloca <4 x i16>, align 8 # | %__s1_790 = alloca <4 x i16>, align 8 # | %__s2_790 = alloca <8 x i16>, align 16 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_790, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_790, align 8 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_790, align 16 # | %3 = load <4 x i16>, ptr %__s0_790, align 8 # | %4 = load <4 x i16>, ptr %__s1_790, align 8 # | %5 = load <8 x i16>, ptr %__s2_790, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.aarch64.neon.sqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_790, align 8 # | %16 = load <4 x i16>, ptr %__ret_790, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_laneq_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_788 = alloca <2 x i32>, align 8 # | %__s0_788 = alloca <2 x i32>, align 8 # | %__s1_788 = alloca <2 x i32>, align 8 # | %__s2_788 = alloca <4 x i32>, align 16 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp1 = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0_788, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1_788, align 8 # | %2 = load <4 x i32>, ptr %v.addr, align 16 # | store <4 x i32> %2, ptr %__s2_788, align 16 # | %3 = load <2 x i32>, ptr %__s0_788, align 8 # | %4 = load <2 x i32>, ptr %__s1_788, align 8 # | %5 = load <4 x i32>, ptr %__s2_788, align 16 # | store <4 x i32> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <4 x i32> # | %lane = shufflevector <4 x i32> %7, <4 x i32> %7, <2 x i32> # | store <2 x i32> %lane, ptr %ref.tmp, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <2 x i32> %4, ptr %__p1.addr.i, align 8 # | store <2 x i32> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %11 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %12 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %13 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.aarch64.neon.sqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %14 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %14, ptr %__ret.i, align 8 # | %15 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %15, ptr %__ret_788, align 8 # | %16 = load <2 x i32>, ptr %__ret_788, align 8 # | store <2 x i32> %16, ptr %tmp1, align 8 # | %17 = load <2 x i32>, ptr %tmp1, align 8 # | ret <2 x i32> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_laneq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %v.addr = alloca <8 x i16>, align 16 # | %__ret_786 = alloca <8 x i16>, align 16 # | %__s0_786 = alloca <8 x i16>, align 16 # | %__s1_786 = alloca <8 x i16>, align 16 # | %__s2_786 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | %tmp1 = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %v, ptr %v.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0_786, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1_786, align 16 # | %2 = load <8 x i16>, ptr %v.addr, align 16 # | store <8 x i16> %2, ptr %__s2_786, align 16 # | %3 = load <8 x i16>, ptr %__s0_786, align 16 # | %4 = load <8 x i16>, ptr %__s1_786, align 16 # | %5 = load <8 x i16>, ptr %__s2_786, align 16 # | store <8 x i16> %5, ptr %__s0, align 16 # | %6 = load <16 x i8>, ptr %__s0, align 16 # | %7 = bitcast <16 x i8> %6 to <8 x i16> # | %lane = shufflevector <8 x i16> %7, <8 x i16> %7, <8 x i32> # | store <8 x i16> %lane, ptr %ref.tmp, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %8, ptr %__ret, align 16 # | %9 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %9, ptr %tmp, align 16 # | %10 = load <8 x i16>, ptr %tmp, align 16 # | store <8 x i16> %3, ptr %__p0.addr.i, align 16 # | store <8 x i16> %4, ptr %__p1.addr.i, align 16 # | store <8 x i16> %10, ptr %__p2.addr.i, align 16 # | %11 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %12 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %13 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %11 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %12 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %13 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.aarch64.neon.sqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %14 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %14, ptr %__ret.i, align 16 # | %15 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %15, ptr %__ret_786, align 16 # | %16 = load <8 x i16>, ptr %__ret_786, align 16 # | store <8 x i16> %16, ptr %tmp1, align 16 # | %17 = load <8 x i16>, ptr %tmp1, align 16 # | ret <8 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_laneq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %v.addr = alloca <4 x i32>, align 16 # | %__ret_784 = alloca <4 x i32>, align 16 # | %__s0_784 = alloca <4 x i32>, align 16 # | %__s1_784 = alloca <4 x i32>, align 16 # | %__s2_784 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | %tmp1 = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %v, ptr %v.addr, align 16 # | %0 = load <4 # | ... # `---data was truncated (10240/50621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x000055f8636cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8636c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f8636cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa935649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9356a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa935649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa935631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f863660e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f863660c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f863645b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f8632f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f8632f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa935632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9356330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9356330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8632f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.1a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c (745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b1620d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b1620a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b1620d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d38733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d3878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d38733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d3871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b161a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b161a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b16187b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b15e370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b15e36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d3871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d3871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d3871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b15e36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c (746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7672c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7672bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7672c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a47a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a47aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a47a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a47a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e767255e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e767255c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e76723ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e766eea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e766ee9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4a47a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a47a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a47a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e766ee9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c (747 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b74b6f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b74b6f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b74b6f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad3101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad310725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad3101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad31003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b74b689e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b74b689c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b74b66eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b74b31e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b74b31ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad31004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad310050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad310050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b74b31dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c (748 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test # | ... # `---data was truncated (10240/156773) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055731613715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573161340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055731613789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dc5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7dc5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dc5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dc5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573160cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005573160ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005573160b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557315d610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557315d60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7dc5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dc5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dc5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557315d60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c (749 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv16i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv8i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv4i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_u32(i32 noundef %op1, i32 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i32, align 4 # | %op2.addr = alloca i32, align 4 # | store i32 %op1, ptr %op1.addr, align 4 # | store i32 %op2, ptr %op2.addr, align 4 # | %0 = load i32, ptr %op1.addr, align 4 # | %1 = load i32, ptr %op2.addr, align 4 # | %2 = call @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %0, i32 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilels.nxv2i1.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv16i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv8i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv4i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %0, i64 %1) # | %3 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.whilele.nxv2i1.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svwhilele_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/13340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005640fbbda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640fbbd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640fbbda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b09533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b0958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b09533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b0951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640fbb6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005640fbb6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005640fbb54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640fb8040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640fb803dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b0951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b0951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b0951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640fb803cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c (750 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | % # | ... # `---data was truncated (10240/47698) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f88433815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8843350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f88433889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3896249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3896249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3896231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8842cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f8842cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f8842b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f883f620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f883f61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3896232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38962330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f883f61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c (751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ea29d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ea29d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ea29d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f308a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f308a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f308a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f308a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ea296ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ea296ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ea294fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ea25ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ea25fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f308a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f308a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f308a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ea25fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c (752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c (753 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e535fb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e535fb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e535fb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae12049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae120a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae12049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae12031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e535f48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e535f48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e535f2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e535bdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e535bdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae12032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae120330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae120330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e535bdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c (754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %cmp = icmp eq <32 x i8> %0, %1 # | %sext = sext <32 x i1> %cmp to <32 x i8> # | store <32 x i8> %sext, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %cmp = icmp eq <16 x i16> %0, %1 # | %sext = sext <16 x i1> %cmp to <16 x i16> # | store <16 x i16> %sext, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %cmp = icmp eq <8 x i32> %0, %1 # | %sext = sext <8 x i1> %cmp to <8 x i32> # | store <8 x i32> %sext, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %cmp = icmp eq <4 x i64> %0, %1 # | %sext = sext <4 x i1> %cmp to <4 x i64> # | store <4 x i64> %sext, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @eq_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> # | ... # `---data was truncated (10240/63117) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005557c141a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557c14170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557c141a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe060b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe060b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe060b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe060aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557c13afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557c13afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557c1394b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557c10440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557c1043dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe060aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe060aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe060aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557c1043cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/poly64.c (755 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/poly64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -flax-vector-conversions=none -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %cmp.i = icmp eq <1 x i64> %2, %3 # | %sext.i = sext <1 x i1> %cmp.i to <1 x i64> # | store <1 x i64> %sext.i, ptr %ref.tmp.i, align 8 # | %4 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %4, ptr %__ret.i, align 8 # | %5 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %cmp.i = icmp eq <2 x i64> %2, %3 # | %sext.i = sext <2 x i1> %cmp.i to <2 x i64> # | store <2 x i64> %sext.i, ptr %ref.tmp.i, align 16 # | %4 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %4, ptr %__ret.i, align 16 # | %5 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %6 = and <1 x i64> %4, %5 # | %7 = icmp ne <1 x i64> %6, zeroinitializer # | %vtst.i = sext <1 x i1> %7 to <1 x i64> # | store <1 x i64> %vtst.i, ptr %ref.tmp.i, align 8 # | %8 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %8, ptr %__ret.i, align 8 # | %9 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %6 = and <2 x i64> %4, %5 # | %7 = icmp ne <2 x i64> %6, zeroinitializer # | %vtst.i = sext <2 x i1> %7 to <2 x i64> # | store <2 x i64> %vtst.i, ptr %ref.tmp.i, align 16 # | %8 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %8, ptr %__ret.i, align 16 # | %9 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_913 = alloca <1 x i64>, align 8 # | %__s0_913 = alloca <1 x i64>, align 8 # | %__s2_913 = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp3 = alloca <1 x i64>, align 8 # | %tmp4 = alloca <1 x i64>, align 8 # | %tmp5 = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0_913, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_913, align 8 # | %2 = load <1 x i64>, ptr %__s2_913, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <1 x i64>, ptr %__s0_913, align 8 # | store <1 x i64> %7, ptr %__s1, align 8 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <1 x i64>, ptr %__s1, align 8 # | %vset_lane = insertelement <1 x i64> %9, i64 %8, i32 0 # | store <1 x i64> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <1 x i64>, ptr %ref.tmp3, align 8 # | store <1 x i64> %10, ptr %__ret, align 8 # | %11 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %11, ptr %tmp4, align 8 # | %12 = load <1 x i64>, ptr %tmp4, align 8 # | store <1 x i64> %12, ptr %__ret_913, align 8 # | %13 = load <1 x i64>, ptr %__ret_913, align 8 # | store <1 x i64> %13, ptr %tmp5, align 8 # | %14 = load <1 x i64>, ptr %tmp5, align 8 # | ret <1 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret_909 = alloca <2 x i64>, align 16 # | %__s0_909 = alloca <2 x i64>, align 16 # | %__s2_909 = alloca <1 x i64>, align 8 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_909, align 16 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s2_909, align 8 # | %2 = load <1 x i64>, ptr %__s2_909, align 8 # | store <1 x i64> %2, ptr %__s02, align 8 # | %3 = load <1 x i64>, ptr %__s02, align 8 # | %vget_lane = extractelement <1 x i64> %3, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = load i64, ptr %__ret1, align 8 # | store i64 %5, ptr %tmp, align 8 # | %6 = load i64, ptr %tmp, align 8 # | store i64 %6, ptr %__s0, align 8 # | %7 = load <2 x i64>, ptr %__s0_909, align 16 # | store <2 x i64> %7, ptr %__s1, align 16 # | %8 = load i64, ptr %__s0, align 8 # | %9 = load <2 x i64>, ptr %__s1, align 16 # | %vset_lane = insertelement <2 x i64> %9, i64 %8, i32 1 # | store <2 x i64> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <2 x i64>, ptr %ref.tmp3, align 16 # | store <2 x i64> %10, ptr %__ret, align 16 # | %11 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %11, ptr %tmp4, align 16 # | %12 = load <2 x i64>, ptr %tmp4, align 16 # | store <2 x i64> %12, ptr %__ret_909, align 16 # | %13 = load <2 x i64>, ptr %__ret_909, align 16 # | store <2 x i64> %13, ptr %tmp5, align 16 # | %14 = load <2 x i64>, ptr %tmp5, align 16 # | ret <2 x i64> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret_915 = alloca <2 x i64>, align 16 # | %__s0_915 = alloca <2 x i64>, align 16 # | %__s2_915 = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca i64, align 8 # | %__ret1 = alloca i64, align 8 # | %__s02 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp3 = alloca <2 x i64>, align 16 # | %tmp4 = alloca <2 x i64>, align 16 # | %tmp5 = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0_915, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s2_915, align 16 # | %2 = load <2 x i64>, ptr %__s2_915, align 16 # | store <2 x i64> %2, ptr %__s02, align 16 # | %3 = load <2 x i64>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <2 x i64> %3, i32 1 # | store i64 %vgetq_lane, ptr %ref.tmp, align 8 # | %4 = load i64, ptr %ref.tmp, align 8 # | store i64 %4, ptr %__ret1, align 8 # | %5 = # | ... # `---data was truncated (10240/22456) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056365a80115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056365a7fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056365a80189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7dca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7dcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7dca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7dca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056365a796e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056365a796c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056365a77bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056365a42b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056365a42add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe7dca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7dca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7dca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056365a42acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c (756 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.rbit.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u8_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.rbit.nxv16i8( zeroinitializer, %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv8i16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.rbit.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s8_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.rbit.nxv16i8( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.rbit.nxv8i16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrbit_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c (757 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d549fd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d549fd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d549fd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf69849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf698a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf69849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf69831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d549f6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d549f6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d549f51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d549c010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d549c00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf69832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf698330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf698330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d549c00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c (758 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593293b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005593293b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005593293b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe83ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe83cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe83ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe83ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055932934ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055932934ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559329333b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559328fe30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559328fe2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe83ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe83ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe83ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559328fe2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c (759 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570fca8215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570fca7f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570fca8289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd02b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd02b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd02b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd02b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570fca17e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570fca17c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570fc9fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570fc6ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570fc6abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd02b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd02b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd02b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570fc6abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c (760 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkn_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkn.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkn.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055bc9e28715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc9e2840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc9e28789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb72ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb72ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb72ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb72ba03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc9e21ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc9e21cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc9e201b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc9deb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc9deb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb72ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb72ba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb72ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc9deb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/nor.c (761 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/nor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svnor_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.nor.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.nor.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055ea46e2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea46e230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea46e2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19ef31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea46dbbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea46dbbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea46da0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea46a500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea46a4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f19ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea46a4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/nor.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c (762 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb2fb1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb2fb1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb2fb1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae61649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae616a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae61649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae61631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb2fab4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb2fab4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb2fa99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb2f7490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb2f748dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae61632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae616330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae616330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb2f748cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c (763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c (764 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc8810715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc881040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc8810789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bd161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bd16725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bd161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bd1603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc8809ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc8809cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc88081b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc87d310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc87d30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7bd1604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bd16050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bd16050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc87d30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c (765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/11958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056084df7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056084df7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056084df7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea7a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea7a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea7a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea7a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056084df14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056084df14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056084def9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056084dba90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056084dba8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea7a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea7a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea7a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056084dba8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c (766 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslb_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslb.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslb.lane(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfmlslt_lane( %zda, %zn, %zm) #0 { # | entry: # | %zda.addr = alloca , align 16 # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zda, ptr %zda.addr, align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zda.addr, align 16 # | %1 = load , ptr %zn.addr, align 16 # | %2 = load , ptr %zm.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfmlslt.lane( %0, %1, %2, i32 7) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfmlslt.lane(, , , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000561ce4e9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ce4e980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ce4e9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2864f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2864f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2864f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2864f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ce4e30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ce4e30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ce4e15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ce4ac50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ce4ac4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2864f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2864f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2864f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ce4ac4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c (767 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c (768 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055928076715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005592807640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055928076789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa4e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa4e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa4e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa4e031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005592806fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005592806fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005592806e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592803910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559280390dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa4e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa4e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa4e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559280390cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c (769 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d82b1b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d82b1ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d82b1b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a52733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a5278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a52733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a5271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d82b145e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d82b145c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d82b12ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d82adda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d82add9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a5271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a5271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a5271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d82add9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c (770 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c (771 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c (772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/135337) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4765c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4765c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4765c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd835c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd835ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd835c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd835c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f47655ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f47655ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f47653fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4761ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4761eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd835c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd835c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd835c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4761eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c (773 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d756bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d756ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d756bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49f9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49f9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49f9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49f9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d75652e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d75652c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d75637b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d752e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d752e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f49f9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49f9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49f9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d752e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c (774 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtzero.t.i64(i64 immarg, i64, i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e8w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e16w4(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 4, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e32w2(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 5, i64 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtzero_t_e64w1(i64 noundef %tm, i64 noundef %tn) #0 { # | entry: # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tm.addr, align 8 # | %1 = load i64, ptr %tn.addr, align 8 # | call void @llvm.riscv.sf.vtzero.t.i64(i64 0, i64 %0, i64 %1, i64 6, i64 1) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564aae42715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564aae4240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564aae42789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3108533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f310858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3108533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f310851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564aae3bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564aae3bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564aae3a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564aae0510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564aae050dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f310851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f310851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f310851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564aae050cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c (775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7468df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7468dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7468df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d82649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d82649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d82631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d746874e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d746874c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d746859b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7465090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d746508dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d82632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d826330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d746508cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c (776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bca279a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bca27970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bca279a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9675b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9675b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9675b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9675b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bca272fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bca272fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bca2714b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bca23c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bca23c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9675b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9675b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9675b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bca23c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c (777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640d208b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640d20880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640d208b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfb1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfb16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfb1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfb1631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640d2020e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005640d2020c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005640d2005b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640d1cb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640d1cb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfb1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfb16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfb16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640d1cb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c (778 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1_tu( %maskedoff, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2_tu( %maskedoff, %src, i64 noundef %offset, i64 no # | ... # `---data was truncated (10240/287205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9b152f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9b152c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9b152f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0567c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0567ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0567c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0567c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9b14c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9b14c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9b14a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9b11590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9b1158dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0567c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0567c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0567c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9b1158cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c (779 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = ca # | ... # `---data was truncated (10240/67474) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cafc8f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cafc8ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cafc8f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f827a41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f827a4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f827a41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f827a403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cafc887e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cafc887c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cafc86cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cafc51c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cafc51bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f827a404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f827a4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f827a4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cafc51bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c (780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c (781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %ba # | ... # `---data was truncated (10240/24100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056383dc2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056383dc220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056383dc2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0712933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f071298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0712933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f071291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056383dbbae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056383dbbac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056383db9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056383d84f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056383d84edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f071291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f071291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f071291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056383d84ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c (782 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c (783 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmin.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmin.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmin_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmin.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055b7ef91a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7ef9170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7ef91a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd1621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd162725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd1621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd16203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7ef8afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b7ef8afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b7ef894b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7ef5440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b7ef543dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd16204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd162050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd162050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7ef543cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c (784 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580c4a9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580c4a9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580c4a9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feaca249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feaca2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feaca249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feaca231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580c4a32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580c4a32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580c4a17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580c46c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580c46c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feaca232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feaca2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feaca2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580c46c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c (785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c (786 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab0d4a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ab0d4a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ab0d4a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63a4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63a478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63a4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63a471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab0d439e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ab0d439c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ab0d41eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ab0d0ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ab0d0cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63a471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63a471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63a471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab0d0cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c (787 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | s # | ... # `---data was truncated (10240/69534) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b05e3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b05e2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b05e3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9f1133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9f118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9f1133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9f111b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b05dc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b05dc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b05dacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b05a5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b05a5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9f111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9f111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9f111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b05a5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c (788 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fadd.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fadd.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadd_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fadd.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055de6fdf715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055de6fdf40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055de6fdf789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f325df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f325df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f325df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f325df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de6fd8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055de6fd8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055de6fd71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055de6fa210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055de6fa20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f325df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f325df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f325df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de6fa20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c (789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566ee71515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566ee7120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566ee71589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dadf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dadf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dadf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dadf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566ee6aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566ee6aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566ee68fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566ee33f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566ee33edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0dadf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dadf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dadf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566ee33ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c (790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/94149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc72af915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc72af60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc72af989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0801e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0801e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0801e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0801e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc72a8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc72a8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc72a73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc727230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc72722dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0801e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0801e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0801e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc72722cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c (791 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +f8f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32mf8( %acc, %a, %b, i64 noundef %fpmr) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %4 = call @llvm.aarch64.sve.fp8.fmmla.nxv4f32( %0, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.fmmla.nxv4f32(, , ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f8f32mm,+sve,+sve2" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f4c76d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4c76d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4c76d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc526d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc526d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc526d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc526d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4c766ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f4c766ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f4c7653b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4c73030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4c7302dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc526d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc526d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc526d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4c7302cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c (792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c (793 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c (794 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c (795 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uxtw.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.sxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.uxtw.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.sxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextw_u64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.uxtw.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055af6a2c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055af6a2c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055af6a2c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4698733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f469878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4698733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f469871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af6a25ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055af6a25ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055af6a243b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af69ef30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af69ef2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f469871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f469871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f469871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af69ef2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c (796 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c (797 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_mf8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.ldnf1.nxv16i8.p0( %0, ptr %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8i16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv8f16.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4f32.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2f64.p0( %2, ptr %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2f64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1_vnum_mf8( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | # | ... # `---data was truncated (10240/22483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055eb8a4af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb8a4ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb8a4af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91dc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91dc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91dc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91dc831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb8a444e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb8a444c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb8a429b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb8a0d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb8a0d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f91dc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91dc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91dc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb8a0d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c (798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | # | ... # `---data was truncated (10240/100521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e986ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e986e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e986ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c7d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c7d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c7d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c7d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e9867fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e9867fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e98664b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e983140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e98313dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c7d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c7d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c7d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e98313cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c (799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572e2e1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005572e2e120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005572e2e1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f534a21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f534a2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f534a21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f534a203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572e2daae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005572e2daac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005572e2d8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005572e2a3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005572e2a3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f534a204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f534a2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f534a2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572e2a3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c (800 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv8f16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv4f32(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frintn.nxv2f64(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv8f16( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv4f32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.frintn.nxv2f64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f16_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv8f16( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv4f32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrintn_f64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.frintn.nxv2f64( undef, %2, %1) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055d590c0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d590c000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d590c0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d3d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d3d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d3d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d3d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d590b98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d590b98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d590b7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d59082d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d59082cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d3d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d3d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d3d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d59082ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c (801 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, # | ... # `---data was truncated (10240/159327) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559b4f39515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b4f3920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b4f39589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dcd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dcd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dcd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dcd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b4f32ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b4f32ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b4f30fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b4efbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b4efbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0dcd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dcd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dcd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b4efbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovl.c (802 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = sext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> # | %2 = zext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> # | %2 = zext <4 x i16> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 1, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vmovl.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, i32 0, i32 1, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovltq_m_u8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vmovl.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, i32 1, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmovltq_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.ad # | ... # `---data was truncated (10240/16274) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a34f8c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a34f8c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a34f8c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf5cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf5cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf5cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf5cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a34f85ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a34f85ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a34f843b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a34f4f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a34f4f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf5cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf5cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf5cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a34f4f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c (803 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c (804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557239f4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557239f400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557239f4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb998049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb998049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb998031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557239ed8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557239ed8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557239ebdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557239b6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557239b6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb998032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9980330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557239b6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c (805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055759acdf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055759acdc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055759acdf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa26c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa26c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa26c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa26c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055759ac74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055759ac74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055759ac59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055759a9090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055759a908dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa26c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa26c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa26c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055759a908cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c (806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d214f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d214f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d214f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05e1333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05e138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05e1333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05e131b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d21488e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d21488c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d2146db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d2111d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d2111cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f05e131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05e131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05e131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d2111ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c (807 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c (808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %carryin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Functi # | ... # `---data was truncated (10240/116949) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056501faa415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056501faa10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056501faa489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0cbf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0cbf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0cbf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0cbf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056501fa39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056501fa39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056501fa1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056501f6ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056501f6cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0cbf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0cbf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0cbf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056501f6cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c (809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/widen.c (810 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/widen.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = sext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = sext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = sext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vmovl.i = zext <8 x i8> %1 to <8 x i16> # | store <8 x i16> %vmovl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x i16> # | %vmovl.i = zext <4 x i16> %2 to <4 x i32> # | store <4 x i32> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %3, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <2 x i32> # | %vmovl.i = zext <2 x i32> %2 to <2 x i64> # | store <2 x i64> %vmovl.i, ptr %ref.tmp.i, align 16 # | %3 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %3, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vmovl_high_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i1 = alloca <8 x i8>, align 8 # | %__p0_561.addr.i = alloca <16 x i8>, align 16 # | %__ret_561.i = alloca <8 x i16>, align 16 # | %__a1_561.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %__s0.i = alloca <8 x i8>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0_561.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0_561.addr.i, align 16 # | store <16 x i8> %1, ptr %__p0.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <16 x i8> %2, <16 x i8> %3, <8 x i32> # | store <8 x i8> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <8 x i8>, ptr %__ret.i1, align 8 # | store <8 x i8> %4, ptr %__a1_561.i, align 8 # | %5 = load <8 x i8>, ptr %__a1_561.i, align 8 # | store <8 x i8> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = sext <8 x i8> %6 to <8 x i16> # | store <8 x i16> %7, ptr %ref.tmp1.i, align 16 # | %8 = load <8 x i16>, ptr %ref.tmp1.i, align 16 # | store <8 x i16> %8, ptr %__ret.i, align 16 # | %9 = load <8 x i16>, ptr %__ret.i, align 16 # | store <8 x i16> %9, ptr %tmp.i, align 16 # | %10 = load <8 x i16>, ptr %tmp.i, align 16 # | store <8 x i16> %10, ptr %ref.tmp.i, align 16 # | %11 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %11, ptr %__ret_561.i, align 16 # | %12 = load <8 x i16>, ptr %__ret_561.i, align 16 # | ret <8 x i16> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmovl_high_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i1 = alloca <4 x i16>, align 8 # | %__p0_567.addr.i = alloca <8 x i16>, align 16 # | %__ret_567.i = alloca <4 x i32>, align 16 # | %__a1_567.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %__s0.i = alloca <4 x i16>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0_567.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0_567.addr.i, align 16 # | store <8 x i16> %1, ptr %__p0.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <8 x i16> %2, <8 x i16> %3, <4 x i32> # | store <4 x i16> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <4 x i16>, ptr %__ret.i1, align 8 # | store <4 x i16> %4, ptr %__a1_567.i, align 8 # | %5 = load <4 x i16>, ptr %__a1_567.i, align 8 # | store <4 x i16> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %8 = sext <4 x i16> %7 to <4 x i32> # | store <4 x i32> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <4 x i32>, ptr %ref.tmp1.i, align 16 # | store <4 x i32> %9, ptr %__ret.i, align 16 # | %10 = load <4 x i32>, ptr %__ret.i, align 16 # | store <4 x i32> %10, ptr %tmp.i, align 16 # | %11 = load <4 x i32>, ptr %tmp.i, align 16 # | store <4 x i32> %11, ptr %ref.tmp.i, align 16 # | %12 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %12, ptr %__ret_567.i, align 16 # | %13 = load <4 x i32>, ptr %__ret_567.i, align 16 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vmovl_high_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i1 = alloca <2 x i32>, align 8 # | %__p0_564.addr.i = alloca <4 x i32>, align 16 # | %__ret_564.i = alloca <2 x i64>, align 16 # | %__a1_564.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %__s0.i = alloca <2 x i32>, align 8 # | %ref.tmp1.i = alloca <16 x i8>, align 16 # | %tmp.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0_564.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0_564.addr.i, align 16 # | store <4 x i32> %1, ptr %__p0.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %shuffle.i = shufflevector <4 x i32> %2, <4 x i32> %3, <2 x i32> # | store <2 x i32> %shuffle.i, ptr %__ret.i1, align 8 # | %4 = load <2 x i32>, ptr %__ret.i1, align 8 # | store <2 x i32> %4, ptr %__a1_564.i, align 8 # | %5 = load <2 x i32>, ptr %__a1_564.i, align 8 # | store <2 x i32> %5, ptr %__s0.i, align 8 # | %6 = load <8 x i8>, ptr %__s0.i, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %8 = sext <2 x i32> %7 to <2 x i64> # | store <2 x i64> %8, ptr %ref.tmp1.i, align 16 # | %9 = load <2 x i64>, ptr %ref.tmp1.i, align 16 # | store <2 x i64> %9, ptr %__ret.i, align 16 # | %10 = load <2 x i64>, ptr %__ret.i, align 16 # | store <2 x i64> %10, ptr %tmp.i, align 16 # | %11 = load <2 x i64>, ptr %tmp.i, align 16 # | store <2 x i64> %11, ptr %ref.tmp.i, align 16 # | %12 = load <2 # | ... # `---data was truncated (10240/16529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f85e1fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f85e1f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f85e1fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce5e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce5e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce5e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce5e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f85e190e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f85e190c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f85e175b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f85de250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f85de24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce5e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce5e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce5e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f85de24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/widen.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c (811 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556de500415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556de50010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556de500489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65b1f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65b1f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65b1f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65b1eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556de4f99e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556de4f99c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556de4f7eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556de4c2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556de4c2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f65b1eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65b1eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65b1eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556de4c2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c (812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | # | ... # `---data was truncated (10240/132462) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647870be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005647870bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005647870be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d36505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d3655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d36505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d364ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564787053e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564787053c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564787038b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564786ce80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564786ce7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4d364eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d364ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d364ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564786ce7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c (813 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6fc52915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6fc5260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6fc52989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcac2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcac2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcac2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcac2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6fc4bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6fc4bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6fc4a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6fc1530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6fc152dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcac2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcac2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcac2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6fc152cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c (814 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldff1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldff1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ldff1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldff # | ... # `---data was truncated (10240/18920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005583d5f7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583d5f6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005583d5f7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c6fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c6fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c6fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c6faed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583d5f06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583d5f06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583d5eebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583d5b9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005583d5b9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c6faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c6faef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c6faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583d5b9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c (815 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ad0eb015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ad0ead0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ad0eb089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8129f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8129f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8129f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8129f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ad0e45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ad0e45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ad0e2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ad0ada0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ad0ad9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8129f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8129f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8129f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ad0ad9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c (816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcd865415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fcd86510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fcd865489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f588b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f588b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f588b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f588b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcd85e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fcd85e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fcd85ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fcd827e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fcd827ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f588b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f588b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f588b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcd827dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c (817 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f64mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp2_bf16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp2q.nxv8bf16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp2q.nxv8bf16(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f64mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055f9ff38f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f9ff38c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f9ff38f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80e2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80e258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80e2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80e251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9ff324e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f9ff324c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f9ff309b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f9fefb90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f9fefb8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80e251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80e251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80e251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9fefb8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c (818 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 9, i32 0, i32 0, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 3, i32 0, i32 0, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 10, i32 0, i32 0, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 13, i32 0, i32 0, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrnbq_m_n_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 7, i32 0, i32 0, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrnbq_m_n_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 15, i32 0, i32 0, i32 1, i32 1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrntq_m_n_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 6, i32 0, i32 0, i32 0, i32 0, i32 1, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrntq_m_n_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 # | ... # `---data was truncated (10240/73182) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa1c0f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa1c0ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa1c0f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b2e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b2e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b2e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b2e6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa1c085e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa1c085c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa1c06ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa1bd1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa1bd19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b2e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b2e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b2e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa1bd19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c (819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c (820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/116267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614c85f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614c85f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005614c85f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2ad333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2ad38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2ad333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2ad31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614c858ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005614c858ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005614c856fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005614c821f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005614c821edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2ad31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2ad31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2ad31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614c821ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c (821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590dfaf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590dfaf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590dfaf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4eefd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4eefd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4eefd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4eefced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590dfa89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590dfa89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590dfa6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590df71e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005590df71ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4eefceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4eefcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4eefcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590df71dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c (822 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/20082) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c17acb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c17ac80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c17acb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c29705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c2975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c29705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c296ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c17a60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c17a60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c17a45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c176f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c176f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c296eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c296ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c296ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c176f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c (823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_u32m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eea28215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561eea27f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561eea28289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff692649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff692649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff692631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eea217e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561eea217c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561eea1fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ee9eac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ee9eabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff692632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6926330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ee9eabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c (824 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9bd52315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9bd5200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9bd52389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa480733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa48078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa480733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa48071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9bd4b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9bd4b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9bd49db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9bd14d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9bd14cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa48071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa48071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa48071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9bd14ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c (825 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ... # `---data was truncated (10240/69831) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590b704d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590b704a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590b704d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3efe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3efe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3efe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3efe831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590b6fe2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590b6fe2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590b6fc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590b6c770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005590b6c76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3efe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3efe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3efe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590b6c76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c (826 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a38b01415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a38b0110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a38b01489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b81733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b8178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b81733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b8171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a38afa9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a38afa9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a38af8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a38ac3e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a38ac3ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b8171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b8171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b8171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38ac3dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c (827 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b2fdcc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b2fdc90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b2fdcc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f6741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f674725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f6741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f67403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b2fd61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b2fd61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b2fd46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b2f9f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b2f9f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f67404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f674050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f674050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b2f9f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c (828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590d9b6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590d9b650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590d9b6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff800b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff800b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff800b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff800b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590d9afde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590d9afdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590d9ae2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590d97920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005590d9791dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff800b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff800b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff800b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590d9791cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c (829 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8f16.nxv4f16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16f16.nxv4f16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16f16.nxv4f16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16f16.nxv4f16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m1_f16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32f16.nxv4f16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32f16.nxv4f16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32f16.nxv4f16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32f16.nxv4f16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32f16.nxv4f16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32f16.nxv4f16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32f16.nxv4f16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16f16.nxv8f16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m2_f16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32f16.nxv8f16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32f16.nxv8f16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32f16.nxv8f16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f16m4_f16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32f16.nxv16f16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcreate_v_f32m1_f32m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 4 # | %v1.addr = alloca , align 4 # | store %v0, ptr %v0.addr, align 4 # | store %v1, ptr %v1.addr, align 4 # | %0 = load , ptr %v0.addr, align 4 # | %1 = load , ptr %v1.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( poison, %0, i64 0) # | %3 = call @llvm. # | ... # `---data was truncated (10240/593252) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5c9b9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5c9b980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5c9b9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ef5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ef518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ef5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ef511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5c9b30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5c9b30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5c9b15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5c97c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5c97c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ef511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ef511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ef511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5c97c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c (830 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve-f16f32mm -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_f32f16( %acc, %a, %b) #0 { # | entry: # | %acc.addr = alloca , align 16 # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %acc, ptr %acc.addr, align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %acc.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %2 = load , ptr %b.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv8f16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-f16f32mm" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005631386b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005631386ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005631386b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc220849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2208a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc220849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc220831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563138646e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563138646c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056313862bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005631382db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005631382dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc220832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2208330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2208330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005631382dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/sve/rsqrte.c (831 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrte.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f16( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv8f16( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv4f32( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrte_f64( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.frsqrte.x.nxv2f64( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrte.x.nxv2f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000564ea49a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ea49a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ea49a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f318ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f318aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f318ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f318ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ea493ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ea493ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ea4923b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564ea45d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564ea45d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f318ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f318ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f318ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ea45d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrte.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c (832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c (833 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i8m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_i8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_i8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_i8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_i8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_i8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_i8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_i8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_i16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf4_f16mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16mf2_f16mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m1_f16m1( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m2_f16m2( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m4_f16m4( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bitcast %0 to # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u16m8_f16m8( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = bi # | ... # `---data was truncated (10240/136481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562210f5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562210f4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562210f5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21d6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21d66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21d6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21d6631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562210ee7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562210ee7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562210eccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562210b7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562210b7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21d6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21d66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21d66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562210b7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiply.c (834 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiply.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %c.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca <1 x double>, align 8 # | %__p2.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %c.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store <1 x double> %1, ptr %__p1.addr.i, align 8 # | store <1 x double> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <1 x double> # | %7 = bitcast <8 x i8> %4 to <1 x double> # | %8 = bitcast <8 x i8> %5 to <1 x double> # | %9 = call <1 x double> @llvm.fma.v1f64(<1 x double> %7, <1 x double> %8, <1 x double> %6) # | store <1 x double> %9, ptr %ref.tmp.i, align 8 # | %10 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %10, ptr %__ret.i, align 8 # | %11 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | %b.addr = alloca <4 x float>, align 16 # | %c.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | store <4 x float> %b, ptr %b.addr, align 16 # | store <4 x float> %c, ptr %c.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | %2 = load <4 x float>, ptr %c.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 16 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %10, ptr %__ret.i, align 16 # | %11 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vfmaq_f64(<2 x double> noundef %a, <2 x double> noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__p2.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | %b.addr = alloca <2 x double>, align 16 # | %c.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | store <2 x double> %b, ptr %b.addr, align 16 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | store <2 x double> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <2 x double> # | %7 = bitcast <16 x i8> %4 to <2 x double> # | %8 = bitcast <16 x i8> %5 to <2 x double> # | %9 = call <2 x double> @llvm.fma.v2f64(<2 x double> %7, <2 x double> %8, <2 x double> %6) # | store <2 x double> %9, ptr %ref.tmp.i, align 16 # | %10 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %10, ptr %__ret.i, align 16 # | %11 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 { # | entry: # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %v.addr = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <2 x float>, align 8 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store <2 x float> %v, ptr %v.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1, align 8 # | %2 = load <2 x float>, ptr %v.addr, align 8 # | store <2 x float> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x float> # | %lane = shufflevector <2 x float> %6, <2 x float> %6, <2 x i32> # | %fmla = bitcast <8 x i8> %4 to <2 x float> # | %fmla1 = bitcast <8 x i8> %3 to <2 x float> # | %fmla2 = call <2 x float> @llvm.fma.v2f32(<2 x float> %fmla, <2 x float> %lane, <2 x float> %fmla1) # | store <2 x float> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Functio # | ... # `---data was truncated (10240/80179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056302562a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630256270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056302562a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63e9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63e98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63e9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63e9831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630255bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005630255bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005630255a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005630252540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563025253dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63e9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63e98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63e98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563025253cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiply.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c (835 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e636fdd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e636fda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e636fdd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9c2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9c258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9c2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9c251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e636f72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e636f72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e636f57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e636c070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e636c06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9c251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9c251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9c251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e636c06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0. FAIL: Clang :: CodeGen/AArch64/neon-misc-constrained.c (836 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-misc-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndaq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrnda.i = bitcast <16 x i8> %1 to <2 x double> # | %vrnda1.i = call <2 x double> @llvm.round.v2f64(<2 x double> %vrnda.i) # | store <2 x double> %vrnda1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndpq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndp.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndp1.i = call <2 x double> @llvm.ceil.v2f64(<2 x double> %vrndp.i) # | store <2 x double> %vrndp1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsqrtq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %vsqrt.i = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %2) # | store <4 x float> %vsqrt.i, ptr %ref.tmp.i, align 16 # | %3 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %3, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <4 x float> # | %3 = fptrunc <4 x float> %2 to <4 x half> # | store <4 x half> %3, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt_high_f16_f32(<4 x half> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__ret.i3 = alloca <8 x half>, align 16 # | %__p0.addr.i.i = alloca <4 x float>, align 16 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x float>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 16 # | %4 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %5 = bitcast <16 x i8> %4 to <4 x float> # | %6 = fptrunc <4 x float> %5 to <4 x half> # | store <4 x half> %6, ptr %ref.tmp.i.i, align 8 # | %7 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %7, ptr %__ret.i.i, align 8 # | %8 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %2, ptr %__p0.addr.i1, align 8 # | store <4 x half> %8, ptr %__p1.addr.i2, align 8 # | %9 = load <4 x half>, ptr %__p0.addr.i1, align 8 # | %10 = load <4 x half>, ptr %__p1.addr.i2, align 8 # | %shuffle.i = shufflevector <4 x half> %9, <4 x half> %10, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i3, align 16 # | %11 = load <8 x half>, ptr %__ret.i3, align 16 # | store <8 x half> %11, ptr %__ret.i, align 16 # | %12 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_f32_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fpext <4 x half> %2 to <4 x float> # | store <4 x float> %3, ptr %ref.tmp.i, align 16 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %4, ptr %__ret.i, align 16 # | %5 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcvt_high_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__ret.i2 = alloca <4 x half>, align 8 # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x float>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p0.addr.i1, align 16 # | %2 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <8 x half> %2, <8 x half> %3, <4 x i32> # | store <4 x half> %shuffle.i, ptr %__ret.i2, align 8 # | %4 = load <4 x half>, ptr %__ret.i2, align 8 # | store <4 x half> %4, ptr %__p0.addr.i.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %7 = fpext <4 x half> %6 to <4 x float> # | store <4 x float> %7, ptr %ref.tmp.i.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i.i, align 16 # | store <4 x float> %8, ptr %__ret.i.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i.i, align 16 # | store <4 x float> %9, ptr %__ret.i, align 16 # | %10 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %10 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.round.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055dbc935815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbc93550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbc935889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1e0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1e00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1e0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1e0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbc92ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbc92edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbc92d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbc8f820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbc8f81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1e0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1e00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1e00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbc8f81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-misc-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c (837 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svbrkpb_b_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.brkpb.z.nxv16i1( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.brkpb.z.nxv16i1(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055888543315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588854300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055888543389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5c8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5c8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5c8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5c8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588853c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588853c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588853adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055888505d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055888505cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc5c8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5c8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5c8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055888505ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c (838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560029a9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560029a900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560029a9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8967e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8967ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8967e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8967e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560029a28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560029a28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560029a0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600296bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600296bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8967e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8967e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8967e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600296bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c (839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb3bac915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb3bac60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb3bac989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d25a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d25aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d25a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d25a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb3ba5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb3ba5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb3ba43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb3b6f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb3b6f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2d25a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d25a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d25a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb3b6f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c (840 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c (841 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd # | ... # `---data was truncated (10240/215044) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfaa63715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dfaa6340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dfaa63789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19f7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19f7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19f7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19f7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfaa5cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dfaa5ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dfaa5b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dfaa2610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dfaa260dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f19f7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19f7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19f7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfaa260cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c (842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64 # | ... # `---data was truncated (10240/29259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e53c62a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e53c6270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e53c62a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01def33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01def8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01def33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01def1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e53c5bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e53c5bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e53c5a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e53c2540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e53c253dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01def1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01def1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01def1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e53c253cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c (843 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a3908315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a390800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a3908389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd604d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd604d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd604d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd604ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a39018e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a39018c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a38ffdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a38cad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a38cacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd604ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd604cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd604cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a38caccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c (844 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c (845 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055778ee9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055778ee910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055778ee9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d7a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d7a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d7a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d7a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055778ee29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055778ee29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055778ee0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055778eabe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055778eabddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9d7a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d7a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d7a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055778eabdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c (846 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056389d69015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056389d68d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056389d69089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb948e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb948ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb948e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb948e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056389d625e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056389d625c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056389d60ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056389d2ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056389d2b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb948e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb948e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb948e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056389d2b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c (847 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a89c71515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a89c7120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a89c71589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb424649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4246a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb424649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb424631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a89c6aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a89c6aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a89c68fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a89c33f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a89c33edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb424632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4246330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4246330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a89c33ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c (848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558df30e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558df30df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558df30e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f4db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f4db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f4db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f4db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558df3077e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558df3077c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558df305cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558df2d0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558df2d0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f4db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f4db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f4db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558df2d0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c (849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/77054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb61c2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb61c240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb61c2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a48e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a48ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a48e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a48e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb61bbce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb61bbcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb61ba1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb618510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb61850dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6a48e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a48e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a48e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb61850cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c (850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i # | ... # `---data was truncated (10240/51295) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ddd2de515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ddd2de20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ddd2de589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7922a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7922a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7922a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7922a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ddd2d7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ddd2d7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ddd2d5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ddd2a0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ddd2a0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7922a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7922a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7922a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddd2a0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c (851 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559fd26a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005559fd2670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005559fd26a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa82b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa82b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa82b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa82b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559fd1ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005559fd1ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005559fd1e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005559fce940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005559fce93dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa82b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa82b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa82b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559fce93cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c (852 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056215585415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621558510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056215585489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8a0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8a078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8a0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8a071b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621557e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621557e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621557ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056215547e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056215547ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8a071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8a071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8a071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056215547dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c (853 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/225655) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fb5fe115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556fb5fde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556fb5fe189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa235d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa235d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa235d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa235d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fb5f76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556fb5f76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556fb5f5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556fb5c0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556fb5c0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa235d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa235d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa235d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fb5c0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c (854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fca0b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fca0b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fca0b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f209e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f209e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f209e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f209e431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fca049e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fca049c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fca02eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fc9cde0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fc9cdddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f209e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f209e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f209e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fc9cddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c (855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596b888015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596b887d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596b888089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dd0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dd0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dd0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dd0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596b8815e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596b8815c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596b87fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596b84aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596b84a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4dd0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dd0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dd0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596b84a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c (856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056345e46315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056345e4600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056345e46389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb16f305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb16f35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb16f305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb16f2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056345e3f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056345e3f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056345e3ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056345e08d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056345e08cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb16f2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb16f2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb16f2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056345e08ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c (857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562929da615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562929da30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562929da689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d23b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d23b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d23b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d23b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562929d3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562929d3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562929d20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629299d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629299cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d23b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d23b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d23b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629299cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c (858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b5dc9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b5dc930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b5dc9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbbab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbbab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbbab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbbaaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b5dc2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b5dc2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b5dc10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b5d8c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b5d8bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbbaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbbaaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbbaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b5d8bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c (859 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s8_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s16_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s32_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svclamp_single_s64_x2( %op1.coerce0, %op1.coerce1, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , }, align 16 # | %op1.addr = alloca { , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , } %0, %op1.coerce1, 1 # | store { , } %1, ptr %op1, align 16 # | %op11 = load { , }, ptr %op1, align 16 # | store { , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %2 = load { , }, ptr %op1.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %op2.addr, align 16 # | %6 = load , ptr %op3.addr, align 16 # | %7 = call { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64( %3, %4, %5, %6) # | ret { , } %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.sclamp.single.x2.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , , , } @test_svclamp_single_s8_x4( %op1.coerce0, %op1.coerce1, %op1.coerce2, %op1.coerce3, %op2, %op3) #0 { # | entry: # | %op1 = alloca { , , , }, align 16 # | %op1.addr = alloca { , , , }, align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | %0 = insertvalue { , , , } poison, %op1.coerce0, 0 # | %1 = insertvalue { , , , } %0, %op1.coerce1, 1 # | %2 = insertvalue { , , , } %1, %op1.coerce2, 2 # | %3 = insertvalue { , , , } %2, %op1.coerce3, 3 # | store { , , , } %3, ptr %op1, align 16 # | %op11 = load { , , , }, ptr %op1, align 16 # | store { , , , } %op11, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %4 = load { , , , }, ptr %op1.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c (860 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2bd20415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d2bd2010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d2bd20489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f962c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f962c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f962c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f962c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2bd199e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d2bd199c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d2bd17eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d2bce2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d2bce2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f962c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f962c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f962c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2bce2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c (861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/183423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586bbb5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005586bbb530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005586bbb5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f026b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f026b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f026b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f026b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586bbaebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005586bbaebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005586bbad0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005586bb7800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005586bb77fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f026b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f026b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f026b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586bb77fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/load-store.c (862 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/load-store.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_f16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x half>, ptr %0, align 2 # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_f32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x float>, ptr %0, align 4 # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_u32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 4 # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vld1q_z_f16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr align 2 %0, <8 x i1> %3, <8 x half> zeroinitializer) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x half> @llvm.masked.load.v8f16.p0(ptr captures(none), <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vld1q_z_f32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 %0, <4 x i1> %3, <4 x float> zeroinitializer) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x float> @llvm.masked.load.v4f32.p0(ptr captures(none), <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_s8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr captures(none), <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_s16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr captures(none), <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_s32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr captures(none), <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vld1q_z_u8(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %0, <16 x i1> %3, <16 x i8> zeroinitializer) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vld1q_z_u16(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr align 2 %0, <8 x i1> %3, <8 x i16> zeroinitializer) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vld1q_z_u32(ptr noundef %base, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr align 4 %0, <4 x i1> %3, <4 x i32> zeroinitializer) # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_s8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_s16(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i8>, ptr %0, align 1 # | %2 = sext <8 x i8> %1 to <8 x i16> # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_s32(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i8>, ptr %0, align 1 # | %2 = sext <4 x i8> %1 to <4 x i32> # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_u8(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %0, align 1 # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_u16(ptr noundef %base) #0 { # | entry: # | %base.addr = a # | ... # `---data was truncated (10240/50873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c35385315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3538500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c35385389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20c0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20c058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20c0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20c051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3537e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c3537e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c3537cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c35347d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c35347cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f20c051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20c051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20c051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c35347ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/load-store.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c (863 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/68065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d4ecb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d4ecb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d4ecb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1876e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1876ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1876e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1876e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d4ec4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d4ec4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d4ec33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d4e8e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d4e8e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1876e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1876e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1876e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d4e8e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c (864 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8( %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16( %0, i32 1) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32( %0, i32 3) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(, i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_lane_s64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64( %0, i32 7) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s8( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv16i8( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s16( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv8i16( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_s32( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv4i32( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svpmov_u64( %zn) #0 { # | entry: # | %zn.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = call @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64( %0) # | %2 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.pmov.to.pred.lane.zero.nxv2i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c (865 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local half @subscript_float16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x half>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x half> %0, i64 %1 # | ret half %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x half> @llvm.vector.extract.v32f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x float>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <16 x float> @llvm.vector.extract.v16f32.nxv4f32( %a.coerce, i64 0) # | store <16 x float> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x float>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x float> @llvm.vector.extract.v16f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x double>, align 16 # | %b.addr = alloca i64, align 8 # | %a = call <8 x double> @llvm.vector.extract.v8f64.nxv2f64( %a.coerce, i64 0) # | store <8 x double> %a, ptr %a.addr, align 16 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x double>, ptr %a.addr, align 16 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x double> @llvm.vector.extract.v8f64.nxv2f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055a68df4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a68df410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a68df4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f5f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f5f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f5f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f5f203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a68ded9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a68ded9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a68debeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a68db6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a68db6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f5f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f5f2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f5f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a68db6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c (866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f2453315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f245300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f2453389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca9ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca9aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca9ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca9ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f244c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f244c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f244adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f2415d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f2415cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca9ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca9ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca9ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f2415ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c (867 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svtsmul_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.ftsmul.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ftsmul.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000563e1bc8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563e1bc8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563e1bc8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18c591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e1bc23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563e1bc23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563e1bc08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563e1b8b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563e1b8b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f18c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18c591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e1b8b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c (868 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/235596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555db7d0615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555db7d030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555db7d0689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad81649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad816a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad81649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad81631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555db7c9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555db7c9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555db7c80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555db79300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555db792fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad81632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad816330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad816330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555db792fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c (869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3a71a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b3a719f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b3a71a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2489733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f248978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2489733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f248971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3a7137e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3a7137c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3a711cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b3a6dcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b3a6dcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f248971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f248971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f248971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3a6dcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c (870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b70e0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561b70dfd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561b70e0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f696db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f696db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f696db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f696db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b70d95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561b70d95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561b70d7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561b70a2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561b70a29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f696db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f696db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f696db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b70a29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c (871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c (872 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b9639115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b9638e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b9639189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7062905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f706295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7062905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70628ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b96326e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b96326c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b9630bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b95fbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b95fbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70628eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70628ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70628ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b95fbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c (873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc3a67315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc3a6700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc3a67389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c33133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c3318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c33133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c3311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc3a608e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc3a608c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc3a5edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc3a29d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc3a29cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c3311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c3311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c3311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc3a29ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c (874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfe016d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dfe016a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dfe016d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb595d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb595d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb595d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb595d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfe0102e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dfe0102c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dfe00e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dfdfd970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dfdfd96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb595d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb595d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb595d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfdfd96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c (875 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056424bf0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056424befd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056424bf0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbee8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbee8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbee8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbee8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056424be95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056424be95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056424be7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056424bb2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056424bb29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbee8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbee8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbee8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056424bb29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c (876 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583a90d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583a90d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005583a90d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21b0431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583a906ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583a906cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583a9051b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583a8d010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005583a8d00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21b04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583a8d00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c (877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056304dcd715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056304dcd40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056304dcd789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25b4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25b4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25b4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25b4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056304dc6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056304dc6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056304dc51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056304d9010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056304d900dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25b4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25b4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25b4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056304d900cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c (878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64 immarg, i64, i64 # | ... # `---data was truncated (10240/32186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc4e56715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fc4e5640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fc4e56789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cebc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cebca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cebc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cebc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc4e4fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fc4e4fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fc4e4e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fc4e1910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fc4e190dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5cebc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cebc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cebc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc4e190cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c (879 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_s64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i8( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8i16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_u64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.uzp1.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b8( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.nxv16i1( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uzp1.nxv16i1(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svuzp1_b16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = call @llvm.aarch64.sve.uzp1.b16( %0, %1) # | ret %2 # | ... # `---data was truncated (10240/13404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a9aedfb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9aedf80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9aedfb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc585449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5854a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc585449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc585431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9aed90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9aed90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9aed75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9aea250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9aea24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc585432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5854330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5854330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9aea24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c (880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2b2d5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2b2d4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c2b2d5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe221933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe22198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe221933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe22191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2b2ce5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2b2ce5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c2b2ccab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2b297a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c2b2979dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe22191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe22191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe22191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2b2979cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c (881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c (882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055840b10715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055840b1040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055840b10789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e68249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e682a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e68249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e68231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055840b09ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055840b09cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055840b081b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055840ad310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055840ad30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e68232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e682330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e682330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055840ad30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c (883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/98581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3700f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3700ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3700f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa31bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa31bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa31bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa31bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d370085e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d370085c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d37006ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d36fd1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d36fd19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa31bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa31bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa31bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d36fd19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c (884 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c (885 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604f2c3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604f2c2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604f2c3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2524249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25242a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2524249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2524231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604f2bc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604f2bc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604f2bacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604f285c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604f285bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2524232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25242330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25242330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604f285bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c (886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056064250815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005606425050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056064250889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb565d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb565d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb565d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb565d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056064249de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056064249dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560642482b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005606421320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560642131dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb565d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb565d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb565d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560642131cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c (887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef1806815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef180650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef1806889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f339fa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f339faa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f339fa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f339fa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef17ffde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef17ffdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef17fe2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef17c920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef17c91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f339fa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f339fa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f339fa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef17c91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm64-lanes.c (888 of 27911) ******************** TEST 'Clang :: CodeGen/arm64-lanes.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_s8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i8 @test_vdupb_lane_u8(<8 x i8> noundef %src) #0 { # | entry: # | %src.addr = alloca <8 x i8>, align 8 # | %__ret = alloca i8, align 1 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | store <8 x i8> %src, ptr %src.addr, align 8 # | %0 = load <8 x i8>, ptr %src.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vget_lane = extractelement <8 x i8> %1, i32 2 # | store i8 %vget_lane, ptr %ref.tmp, align 1 # | %2 = load i8, ptr %ref.tmp, align 1 # | store i8 %2, ptr %__ret, align 1 # | %3 = load i8, ptr %__ret, align 1 # | store i8 %3, ptr %tmp, align 1 # | %4 = load i8, ptr %tmp, align 1 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_s16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i16 @test_vduph_lane_u16(<4 x i16> noundef %src) #0 { # | entry: # | %src.addr = alloca <4 x i16>, align 8 # | %__ret = alloca i16, align 2 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store <4 x i16> %src, ptr %src.addr, align 8 # | %0 = load <4 x i16>, ptr %src.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i16> %1, i32 2 # | store i16 %vget_lane, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_s32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_vdups_lane_u32(<2 x i32> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %src, ptr %src.addr, align 8 # | %0 = load <2 x i32>, ptr %src.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define float @test_vdups_lane_f32(<2 x float> noundef %src) #0 { # | entry: # | %src.addr = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | store <2 x float> %src, ptr %src.addr, align 8 # | %0 = load <2 x float>, ptr %src.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <2 x float>, ptr %__s0, align 8 # | %vdups_lane = extractelement <2 x float> %1, i32 0 # | store float %vdups_lane, ptr %ref.tmp, align 4 # | %2 = load float, ptr %ref.tmp, align 4 # | store float %2, ptr %__ret, align 4 # | %3 = load float, ptr %__ret, align 4 # | store float %3, ptr %tmp, align 4 # | %4 = load float, ptr %tmp, align 4 # | ret float %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_s64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define i64 @test_vdupd_lane_u64(<1 x i64> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <1 x i64> %src, ptr %src.addr, align 8 # | %0 = load <1 x i64>, ptr %src.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define double @test_vdupd_lane_f64(<1 x double> noundef %src) #0 { # | entry: # | %src.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store <1 x double> %src, ptr %src.addr, align 8 # | %0 = load <1 x double>, ptr %src.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %__s0, align 8 # | %vdupd_lane = extractelement <1 x double> %1, i32 0 # | store double %vdupd_lane, ptr %ref.tmp, align 8 # | %2 = load double, ptr %ref.tmp, align 8 # | store double %2, ptr %__ret, align 8 # | %3 = load double, ptr %__ret, align 8 # | store double %3, ptr %tmp, align 8 # | %4 = load double, ptr %tmp, align 8 # | ret double %4 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557265ce815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557265ce50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557265ce889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6a91533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6a9158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6a91533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6a9151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557265c7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557265c7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557265c62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005572659120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557265911dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6a9151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6a9151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6a9151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557265911cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-lanes.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c (889 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9e966a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9e96670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9e966a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9273b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9273b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9273b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9273aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9e95ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9e95ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9e95e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9e92940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9e9293dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9273aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9273aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9273aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9e9293cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c (890 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624f2dda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624f2dd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624f2dda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe51981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5198725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe51981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe519803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624f2d6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624f2d6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624f2d54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624f2a040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624f2a03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe519804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5198050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5198050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624f2a03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c (891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f150e8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f150e8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f150e8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5e5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5e56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5e5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5e5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f150e22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f150e22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f150e07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f150ab70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f150ab6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd5e5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5e56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5e56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f150ab6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c (892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vror.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562376cde15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562376cdb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562376cde89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b04e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b04ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b04e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b04e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562376c73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562376c73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562376c58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005623769080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562376907dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2b04e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b04e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b04e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562376907cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c (893 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_0_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 0) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.bfdot.lane.v2(, , , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_lane_3_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.bfdot.lane.v2( %0, %1, %2, i32 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_bfdot_n_f32( %x, %y, bfloat noundef %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca bfloat, align 2 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store bfloat %z, ptr %z.addr, align 2 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load bfloat, ptr %z.addr, align 2 # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %3 = call @llvm.aarch64.sve.bfdot( %0, %1, %.splat) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000558cdd93d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558cdd93a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558cdd93d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3963133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f396318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3963133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f396311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cdd8d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558cdd8d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558cdd8b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558cdd5670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558cdd566dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f396311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f396311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f396311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cdd566cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c (894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac9a2fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac9a2f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac9a2fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74c5f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74c5f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74c5f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74c5eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac9a290e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac9a290c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac9a275b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac99f250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac99f24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f74c5eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74c5eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74c5eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac99f24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c (895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c (896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c (897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a311c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a311c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a311c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87e2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87e218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87e2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87e211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a3115be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a3115bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a31140b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a30df00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a30defdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f87e211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87e211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87e211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a30defcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c (898 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | # | ... # `---data was truncated (10240/415319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605a922215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005605a921f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005605a922289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f118f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f118f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f118f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f118f831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605a91b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005605a91b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005605a919cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005605a8e4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005605a8e4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f118f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f118f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f118f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605a8e4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c (899 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/100952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591bb5ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591bb5aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591bb5ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fa6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fa655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fa6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fa64ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591bb542e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005591bb542c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005591bb527b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005591bb1d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005591bb1d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fa64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fa64ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fa64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591bb1d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c (900 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -target-feature +rcpc3 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vldap1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret = alloca <2 x double>, align 16 # | %__s1 = alloca <2 x double>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x double> %3, double %4, i32 1 # | store <2 x double> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %5, ptr %__ret, align 16 # | %6 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %6, ptr %tmp, align 16 # | %7 = load <2 x double>, ptr %tmp, align 16 # | ret <2 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vldap1q_lane_p64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <2 x i64> %3, i64 %4, i32 1 # | store <2 x i64> %vldap1_lane, ptr %ref.tmp, align 16 # | %5 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %5, ptr %__ret, align 16 # | %6 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %6, ptr %tmp, align 16 # | %7 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_u64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_s64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vldap1_lane_f64(ptr noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %4 = load atomic double, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x double> %3, double %4, i32 0 # | store <1 x double> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %5, ptr %__ret, align 8 # | %6 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %6, ptr %tmp, align 8 # | %7 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vldap1_lane_p64(ptr noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__s1, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %__s1, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x i64> # | %4 = load atomic i64, ptr %1 acquire, align 8 # | %vldap1_lane = insertelement <1 x i64> %3, i64 %4, i32 0 # | store <1 x i64> %vldap1_lane, ptr %ref.tmp, align 8 # | %5 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %5, ptr %__ret, align 8 # | %6 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %6, ptr %tmp, align 8 # | %7 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_u64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_s64(ptr noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | store ptr %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__s1, align 16 # | %1 = load ptr, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %__s1, align 16 # | %3 = bitcast <16 x i8> %2 to <2 x i64> # | %4 = extractelement <2 x i64> %3, i32 1 # | store atomic i64 %4, ptr %1 release, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vstl1q_lane_f64(ptr noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca # | ... # `---data was truncated (10240/14230) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056386373215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056386372f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056386373289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4203733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f420378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4203733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f420371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638636c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638636c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638636acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056386335c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056386335bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f420371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f420371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f420371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056386335bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-ldst-one-rcpc3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c (901 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c (902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056025276815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602527650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056025276889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f70533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f7058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f70533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f7051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602526fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602526fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602526e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602523920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560252391dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f7051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f7051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f7051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560252391cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c (903 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bf12c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562bf12be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562bf12c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17cf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17cf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17cf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17cf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bf1256e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562bf1256c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562bf123bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562bf0eeb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562bf0eeadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f17cf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17cf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17cf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bf0eeacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c (904 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/415311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b1964a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b196470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b1964a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2386f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2386f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2386f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2386f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b195dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b195dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b195c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b192740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b19273dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2386f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2386f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2386f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b19273cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c (905 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ff956615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560ff95630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560ff956689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb4e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb4e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb4e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb4e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ff94fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560ff94fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560ff94e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560ff91900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560ff918fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdb4e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb4e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb4e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ff918fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c (906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b1b73d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558b1b73a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558b1b73d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa567249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5672a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa567249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa567231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b1b6d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558b1b6d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558b1b6b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558b1b3670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558b1b366dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa567232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5672330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5672330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b1b366cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c (907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c (908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598c559a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005598c55970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005598c559a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3addf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3addf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3addf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3addf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598c552fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598c552fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598c5514b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598c51c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005598c51c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3addf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3addf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3addf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598c51c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c (909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dfa568615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dfa56830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dfa568689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6000533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f600058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6000533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f600051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dfa561be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dfa561bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dfa5600b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dfa52b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dfa52afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f600051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f600051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f600051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dfa52afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c (910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597ef7d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597ef7d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597ef7d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5acf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5acf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5acf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5acf031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597ef76de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597ef76dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597ef752b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597ef4020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597ef401dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5acf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5acf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5acf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597ef401cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c (911 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_mf8_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv16i8( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_u16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8i16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_f16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8f16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_bf16_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = call { , } @llvm.aarch64.sve.zip.x2.nxv8bf16( %3, %4) # | ret { , } %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.zip.x2.nxv8bf16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svzip_s32_x2( %zn.coerce0, %zn.coerce1) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.c # | ... # `---data was truncated (10240/35785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000563cd7a6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563cd7a690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563cd7a6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05f621bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05f62725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05f621ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05f6203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cd7a01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563cd7a01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563cd79e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563cd76960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563cd7695dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f05f6204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05f62050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05f62050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cd7695cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c (912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056155348715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615534840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056155348789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c77b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c77b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c77b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c77b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056155341ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056155341cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561553401b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615530b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615530b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c77b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c77b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c77b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615530b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c (913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vector-arith-ops.c (914 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = add %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %add = fadd %0, %1 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %b.addr, align 16 # | %1 = load , ptr %a.addr, align 16 # | %add = add %1, %0 # | store %add, ptr %a.addr, align 16 # | ret %add # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @add_inplace_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca < # | ... # `---data was truncated (10240/107144) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b7493f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7493f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7493f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f718c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f718c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f718c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f718c231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b74938ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b74938cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b749371b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7490210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b749020dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f718c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f718c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f718c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b749020cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c (915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c (916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a8dbb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a8dbb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a8dbb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04c081bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04c08725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04c081ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04c0803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a8db48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a8db48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a8db2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a8d7dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a8d7dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f04c0804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04c08050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04c08050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a8d7dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c (917 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/rsqrts.c (918 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/rsqrts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f16( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv8f16( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f32( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv4f32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrsqrts_f64( %op1, %op2) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = call @llvm.aarch64.sve.frsqrts.x.nxv2f64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.frsqrts.x.nxv2f64(, ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x0000557cc30fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557cc30fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557cc30fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3837533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f383758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3837533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f383751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc3092e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557cc3092c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557cc3077b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557cc2d270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557cc2d26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f383751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f383751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f383751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc2d26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/rsqrts.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabavq.c (919 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabavq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2, <4 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2, <16 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2, <8 x i1> %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | store i16 %p, ptr % # | ... # `---data was truncated (10240/11173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000556f0fba815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556f0fba50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556f0fba889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c24933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c2498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c24933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c2491b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f0fb3de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556f0fb3dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556f0fb22b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556f0f7d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556f0f7d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c2491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c2491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c2491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f0f7d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c (920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b6db9e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b6db9b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b6db9e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efdc9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efdc9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efdc9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efdc9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b6db33e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b6db33c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b6db18b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b6d7c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b6d7c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efdc9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efdc9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efdc9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b6d7c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c (921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570abc5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570abc590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570abc5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f170f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f170f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f170f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f170f031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570abbf1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570abbf1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570abbd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570ab8860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570ab885dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f170f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f170f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f170f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570ab885cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c (922 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | s # | ... # `---data was truncated (10240/58326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4de3ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4de3e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b4de3ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f91bd249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f91bd2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f91bd249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f91bd231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4de381e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4de381c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4de366b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4de0160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b4de015dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f91bd232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f91bd2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f91bd2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4de015cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c (923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c (924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c (925 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.a # | ... # `---data was truncated (10240/174713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649745d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005649745cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005649745d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a7d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a7d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a7d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a7d631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564974565e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564974565c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056497454ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649741fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649741f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2a7d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a7d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a7d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649741f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c (926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607e679815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005607e67950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005607e679889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f936a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f936a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f936a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f936a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607e672de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607e672dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607e6712b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607e63c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607e63c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f936a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f936a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f936a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607e63c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c (927 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c (928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c (929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/68054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6b323e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6b323b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6b323e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb586f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb586f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb586f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb586f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6b31d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f6b31d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6b31b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6b2e680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6b2e67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb586f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb586f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb586f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6b2e67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (930 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c (931 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lastb.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lastb.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lastb.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lastb.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlastb_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lastb.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlastb_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lastb.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlastb_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lastb.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlastb_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lastb.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlastb_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lastb.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lastb.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlastb_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lastb.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lastb.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlastb_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lastb.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lastb.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlastb_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lastb.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055a0b1deb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a0b1de80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a0b1deb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff14d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff14d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff14d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff14d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0b1d80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a0b1d80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a0b1d65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a0b1a150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a0b1a14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff14d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff14d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff14d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0b1a14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c (932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7c685315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7c68500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7c685389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f106fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f106fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f106fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f106fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7c67e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7c67e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7c67cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7c647d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7c647cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f106fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f106fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f106fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7c647ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c (933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561187b7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561187b730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561187b7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2abaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2abaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2abaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2abaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561187b0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561187b0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561187af0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005611877a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056118779fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2abaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2abaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2abaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056118779fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-neon-vst.c (934 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-gnueabi -target-feature +neon -target-feature +fp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-gnueabi" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x4x3_t = type { [3 x <4 x half>] } # | %struct.float16x4x4_t = type { [4 x <4 x half>] } # | %struct.float32x2x2_t = type { [2 x <2 x float>] } # | %struct.float32x2x3_t = type { [3 x <2 x float>] } # | %struct.float32x2x4_t = type { [4 x <2 x float>] } # | %struct.poly16x4x2_t = type { [2 x <4 x i16>] } # | %struct.poly16x4x3_t = type { [3 x <4 x i16>] } # | %struct.poly16x4x4_t = type { [4 x <4 x i16>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int16x4x2_t = type { [2 x <4 x i16>] } # | %struct.int16x4x3_t = type { [3 x <4 x i16>] } # | %struct.int16x4x4_t = type { [4 x <4 x i16>] } # | %struct.int32x2x2_t = type { [2 x <2 x i32>] } # | %struct.int32x2x3_t = type { [3 x <2 x i32>] } # | %struct.int32x2x4_t = type { [4 x <2 x i32>] } # | %struct.int64x1x2_t = type { [2 x <1 x i64>] } # | %struct.int64x1x3_t = type { [3 x <1 x i64>] } # | %struct.int64x1x4_t = type { [4 x <1 x i64>] } # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint16x4x2_t = type { [2 x <4 x i16>] } # | %struct.uint16x4x3_t = type { [3 x <4 x i16>] } # | %struct.uint16x4x4_t = type { [4 x <4 x i16>] } # | %struct.uint32x2x2_t = type { [2 x <2 x i32>] } # | %struct.uint32x2x3_t = type { [3 x <2 x i32>] } # | %struct.uint32x2x4_t = type { [4 x <2 x i32>] } # | %struct.uint64x1x2_t = type { [2 x <1 x i64>] } # | %struct.uint64x1x3_t = type { [3 x <1 x i64>] } # | %struct.uint64x1x4_t = type { [4 x <1 x i64>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.float16x8x3_t = type { [3 x <8 x half>] } # | %struct.float16x8x4_t = type { [4 x <8 x half>] } # | %struct.float32x4x2_t = type { [2 x <4 x float>] } # | %struct.float32x4x3_t = type { [3 x <4 x float>] } # | %struct.float32x4x4_t = type { [4 x <4 x float>] } # | %struct.poly16x8x2_t = type { [2 x <8 x i16>] } # | %struct.poly16x8x3_t = type { [3 x <8 x i16>] } # | %struct.poly16x8x4_t = type { [4 x <8 x i16>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | %struct.int16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int16x8x3_t = type { [3 x <8 x i16>] } # | %struct.int16x8x4_t = type { [4 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int32x4x3_t = type { [3 x <4 x i32>] } # | %struct.int32x4x4_t = type { [4 x <4 x i32>] } # | %struct.int64x2x2_t = type { [2 x <2 x i64>] } # | %struct.int64x2x3_t = type { [3 x <2 x i64>] } # | %struct.int64x2x4_t = type { [4 x <2 x i64>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.uint16x8x3_t = type { [3 x <8 x i16>] } # | %struct.uint16x8x4_t = type { [4 x <8 x i16>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.uint32x4x3_t = type { [3 x <4 x i32>] } # | %struct.uint32x4x4_t = type { [4 x <4 x i32>] } # | %struct.uint64x2x2_t = type { [2 x <2 x i64>] } # | %struct.uint64x2x3_t = type { [3 x <2 x i64>] } # | %struct.uint64x2x4_t = type { [4 x <2 x i64>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <4 x i16> # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | call void @llvm.arm.neon.vst1x2.p0.v4i16(ptr %0, <4 x i16> %3, <4 x i16> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x3_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x3_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %b, i32 0, i32 0 # | store [3 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 24, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [3 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [3 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x3_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [3 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %4 = bitcast <8 x i8> %1 to <4 x i16> # | %5 = bitcast <8 x i8> %2 to <4 x i16> # | %6 = bitcast <8 x i8> %3 to <4 x i16> # | call void @llvm.arm.neon.vst1x3.p0.v4i16(ptr %0, <4 x i16> %4, <4 x i16> %5, <4 x i16> %6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x3.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f16_x4(ptr noundef %a, [4 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float16x4x4_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float16x4x4_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %b, i32 0, i32 0 # | store [4 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 32, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [4 x <4 x half>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [4 x <4 x half>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %val3 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx4 = getelementptr inbounds [4 x <4 x half>], ptr %val3, i32 0, i32 2 # | %3 = load <8 x i8>, ptr %arrayidx4, align 8 # | %val5 = getelementptr inbounds nuw %struct.float16x4x4_t, ptr %__s1, i32 0, i32 0 # | %arrayidx6 = getelementptr inbounds [4 x <4 x half>], ptr %val5, i32 0, i32 3 # | %4 = load <8 x i8>, ptr %arrayidx6, align 8 # | %5 = bitcast <8 x i8> %1 to <4 x i16> # | %6 = bitcast <8 x i8> %2 to <4 x i16> # | %7 = bitcast <8 x i8> %3 to <4 x i16> # | %8 = bitcast <8 x i8> %4 to <4 x i16> # | call void @llvm.arm.neon.vst1x4.p0.v4i16(ptr %0, <4 x i16> %5, <4 x i16> %6, <4 x i16> %7, <4 x i16> %8) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x4.p0.v4i16(ptr captures(none), <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x2(ptr noundef %a, [2 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %struct.float32x2x2_t, align 8 # | %a.addr = alloca ptr, align 4 # | %__s1 = alloca %struct.float32x2x2_t, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %b, i32 0, i32 0 # | store [2 x i64] %b.coerce, ptr %coerce.dive, align 8 # | store ptr %a, ptr %a.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %__s1, ptr align 8 %b, i32 16, i1 false) # | %0 = load ptr, ptr %a.addr, align 4 # | %val = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <2 x float>], ptr %val, i32 0, i32 0 # | %1 = load <8 x i8>, ptr %arrayidx, align 8 # | %val1 = getelementptr inbounds nuw %struct.float32x2x2_t, ptr %__s1, i32 0, i32 0 # | %arrayidx2 = getelementptr inbounds [2 x <2 x float>], ptr %val1, i32 0, i32 1 # | %2 = load <8 x i8>, ptr %arrayidx2, align 8 # | %3 = bitcast <8 x i8> %1 to <2 x float> # | %4 = bitcast <8 x i8> %2 to <2 x float> # | call void @llvm.arm.neon.vst1x2.p0.v2f32(ptr %0, <2 x float> %3, <2 x float> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.neon.vst1x2.p0.v2f32(ptr captures(none), <2 x float>, <2 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vst1_f32_x3(ptr noundef %a, [3 x i64] %b.coerce) #0 { # | entry: # | %b = alloca %s # | ... # `---data was truncated (10240/108866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e3673ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3673a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3673ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11f5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11f518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11f5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11f511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e367340e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e367340c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e367325b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e366fd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e366fd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11f511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11f511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11f511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e366fd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=CHECK-A32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c (935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b792ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b792ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b792ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c37a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c37aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c37a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c37a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b79243e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b79243c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b79228b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b78ed80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b78ed7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c37a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c37a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c37a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b78ed7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c (936 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b5f3e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b5f3e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b5f3e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb34f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb34f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb34f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb34f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b5f37ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b5f37cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b5f361b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b5f0110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b5f010dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb34f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb34f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb34f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b5f010cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c (937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8f1c7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8f1c780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8f1c7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2207333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f220738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2207333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f220731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8f1c10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8f1c10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8f1bf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8f18a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8f18a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f220731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f220731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f220731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f18a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c (938 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5bb03d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5bb03a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5bb03d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69e0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69e00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69e0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69e0031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5bafd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5bafd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5bafb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5bac670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5bac66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f69e0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69e00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69e00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5bac66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-tbl.c (939 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-tbl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | %struct.int8x8x2_t = type { [2 x <8 x i8>] } # | %struct.int8x16x2_t = type { [2 x <16 x i8>] } # | %struct.int8x8x3_t = type { [3 x <8 x i8>] } # | %struct.int8x16x3_t = type { [3 x <16 x i8>] } # | %struct.int8x8x4_t = type { [4 x <8 x i8>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint8x8x2_t = type { [2 x <8 x i8>] } # | %struct.uint8x16x2_t = type { [2 x <16 x i8>] } # | %struct.uint8x8x3_t = type { [3 x <8 x i8>] } # | %struct.uint8x16x3_t = type { [3 x <16 x i8>] } # | %struct.uint8x8x4_t = type { [4 x <8 x i8>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.poly8x8x2_t = type { [2 x <8 x i8>] } # | %struct.poly8x16x2_t = type { [2 x <16 x i8>] } # | %struct.poly8x8x3_t = type { [3 x <8 x i8>] } # | %struct.poly8x16x3_t = type { [3 x <16 x i8>] } # | %struct.poly8x8x4_t = type { [4 x <8 x i8>] } # | %struct.poly8x16x4_t = type { [4 x <16 x i8>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl11.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %3) # | store <8 x i8> %vtbl11.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %2, <8 x i8> %3) # | store <8 x i8> %vtbl1.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %4, ptr %__ret.i, align 8 # | %5 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x2_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x2_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | store [2 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [2 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [2 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl1.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl13.i = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %4) # | store <8 x i8> %vtbl13.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x2_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x2_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | store [2 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x2_t, ptr %a, i32 0, i32 0 # | %1 = load [2 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [2 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [2 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %2, <16 x i8> %3, <8 x i8> %4) # | store <8 x i8> %vtbl2.i, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x3_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x3_t, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | store [3 x <8 x i8>] %a.coerce, ptr %coerce.dive, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x8x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <8 x i8>], ptr %coerce.dive1, align 8 # | store [3 x <8 x i8>] %1, ptr %__p0.i, align 8 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.i, align 8 # | %arrayidx2.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <8 x i8>, ptr %arrayidx2.i, align 8 # | %arrayidx4.i = getelementptr inbounds [3 x <8 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <8 x i8>, ptr %arrayidx4.i, align 8 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl2.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | %vtbl25.i = shufflevector <8 x i8> %4, <8 x i8> zeroinitializer, <16 x i32> # | %vtbl26.i = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> %vtbl2.i, <16 x i8> %vtbl25.i, <8 x i8> %5) # | store <8 x i8> %vtbl26.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] alignstack(16) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x16x3_t, align 16 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x16x3_t, align 16 # | %b.addr = alloca <8 x i8>, align 8 # | %coerce.dive = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | store [3 x <16 x i8>] %a.coerce, ptr %coerce.dive, align 16 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %b.addr, align 8 # | %coerce.dive1 = getelementptr inbounds nuw %struct.int8x16x3_t, ptr %a, i32 0, i32 0 # | %1 = load [3 x <16 x i8>], ptr %coerce.dive1, align 16 # | store [3 x <16 x i8>] %1, ptr %__p0.i, align 16 # | store <8 x i8> %0, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.i, align 16 # | %arrayidx2.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 1 # | %3 = load <16 x i8>, ptr %arrayidx2.i, align 16 # | %arrayidx4.i = getelementptr inbounds [3 x <16 x i8>], ptr %__p0.i, i64 0, i64 2 # | %4 = load <16 x i8>, ptr %arrayidx4.i, align 16 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vtbl3.i = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x i8> %2, <16 x i8> %3, <16 x i8> %4, <8 x i8> %5) # | store <8 x i8> %vtbl3.i, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] alignstack(8) %a.coerce, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.i = alloca %struct.int8x8x4_t, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a = alloca %struct.int8x8x4_t, align 8 # | %b.a # | ... # `---data was truncated (10240/125901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac63f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bac63f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bac63f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca93933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca9398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca93933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca9391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac638ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bac638cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bac6371b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bac60210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bac6020dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca9391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca9391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca9391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac6020cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-tbl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c (940 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056292fc0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056292fc080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056292fc0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd49d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd49d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd49d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd49d003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056292fba0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056292fba0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056292fb85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056292f8350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056292f834dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd49d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd49d0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd49d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056292f834cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c (941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | # | ... # `---data was truncated (10240/211223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e944f7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e944f770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e944f7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6d6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6d64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6d6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6d6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e944f0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e944f0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e944ef4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e944ba40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e944ba3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6d6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6d64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6d64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e944ba3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/builtins-arm-exclusive.c (942 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm-exclusive.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Werror -triple thumbv8-linux-gnueabi -fno-signed-char -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabi" # | # | %struct.Simple = type { i8, i8 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldrex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldrexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldrexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldrexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldrex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldrexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ldaex(ptr noundef %addr, ptr noundef %addr64, ptr noundef %addrfloat) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %addr64.addr = alloca ptr, align 4 # | %addrfloat.addr = alloca ptr, align 4 # | %sum = alloca i32, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %addr64, ptr %addr64.addr, align 4 # | store ptr %addrfloat, ptr %addrfloat.addr, align 4 # | store i32 0, ptr %sum, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %ldrex = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %0) # | %1 = trunc i32 %ldrex to i8 # | %conv = zext i8 %1 to i32 # | %2 = load i32, ptr %sum, align 4 # | %add = add nsw i32 %2, %conv # | store i32 %add, ptr %sum, align 4 # | %3 = load ptr, ptr %addr.addr, align 4 # | %ldrex1 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %3) # | %4 = trunc i32 %ldrex1 to i16 # | %conv2 = sext i16 %4 to i32 # | %5 = load i32, ptr %sum, align 4 # | %add3 = add nsw i32 %5, %conv2 # | store i32 %add3, ptr %sum, align 4 # | %6 = load ptr, ptr %addr.addr, align 4 # | %ldrex4 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %6) # | %7 = load i32, ptr %sum, align 4 # | %add5 = add nsw i32 %7, %ldrex4 # | store i32 %add5, ptr %sum, align 4 # | %8 = load ptr, ptr %addr.addr, align 4 # | %ldrexd = call { i32, i32 } @llvm.arm.ldaexd(ptr %8) # | %9 = extractvalue { i32, i32 } %ldrexd, 1 # | %10 = extractvalue { i32, i32 } %ldrexd, 0 # | %11 = zext i32 %9 to i64 # | %12 = zext i32 %10 to i64 # | %shl = shl nuw i64 %11, 32 # | %13 = or i64 %shl, %12 # | %14 = load i32, ptr %sum, align 4 # | %conv6 = sext i32 %14 to i64 # | %add7 = add nsw i64 %conv6, %13 # | %conv8 = trunc i64 %add7 to i32 # | store i32 %conv8, ptr %sum, align 4 # | %15 = load ptr, ptr %addr64.addr, align 4 # | %ldrexd9 = call { i32, i32 } @llvm.arm.ldaexd(ptr %15) # | %16 = extractvalue { i32, i32 } %ldrexd9, 1 # | %17 = extractvalue { i32, i32 } %ldrexd9, 0 # | %18 = zext i32 %16 to i64 # | %19 = zext i32 %17 to i64 # | %shl10 = shl nuw i64 %18, 32 # | %20 = or i64 %shl10, %19 # | %21 = load i32, ptr %sum, align 4 # | %conv11 = sext i32 %21 to i64 # | %add12 = add nsw i64 %conv11, %20 # | %conv13 = trunc i64 %add12 to i32 # | store i32 %conv13, ptr %sum, align 4 # | %22 = load ptr, ptr %addrfloat.addr, align 4 # | %ldrex14 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %22) # | %23 = bitcast i32 %ldrex14 to float # | %24 = load i32, ptr %sum, align 4 # | %conv15 = sitofp i32 %24 to float # | %add16 = fadd float %conv15, %23 # | %conv17 = fptosi float %add16 to i32 # | store i32 %conv17, ptr %sum, align 4 # | %25 = load ptr, ptr %addr.addr, align 4 # | %ldrexd18 = call { i32, i32 } @llvm.arm.ldaexd(ptr %25) # | %26 = extractvalue { i32, i32 } %ldrexd18, 1 # | %27 = extractvalue { i32, i32 } %ldrexd18, 0 # | %28 = zext i32 %26 to i64 # | %29 = zext i32 %27 to i64 # | %shl19 = shl nuw i64 %28, 32 # | %30 = or i64 %shl19, %29 # | %31 = bitcast i64 %30 to double # | %32 = load i32, ptr %sum, align 4 # | %conv20 = sitofp i32 %32 to double # | %add21 = fadd double %conv20, %31 # | %conv22 = fptosi double %add21 to i32 # | store i32 %conv22, ptr %sum, align 4 # | %33 = load ptr, ptr %addr.addr, align 4 # | %ldrex23 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %33) # | %34 = inttoptr i32 %ldrex23 to ptr # | %35 = load i32, ptr %34, align 4 # | %36 = load i32, ptr %sum, align 4 # | %add24 = add nsw i32 %36, %35 # | store i32 %add24, ptr %sum, align 4 # | %37 = load ptr, ptr %addr.addr, align 4 # | %ldrex25 = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %37) # | %38 = inttoptr i32 %ldrex25 to ptr # | %a = getelementptr inbounds nuw %struct.Simple, ptr %38, i32 0, i32 0 # | %39 = load i8, ptr %a, align 1 # | %conv26 = zext i8 %39 to i32 # | %40 = load i32, ptr %sum, align 4 # | %add27 = add nsw i32 %40, %conv26 # | store i32 %add27, ptr %sum, align 4 # | %41 = load i32, ptr %sum, align 4 # | ret i32 %41 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.ldaex.p0(ptr) #1 # | # | ; Function Attrs: nounwind # | declare { i32, i32 } @llvm.arm.ldaexd(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_strex(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %res = alloca i32, align 4 # | %var = alloca %struct.Simple, align 1 # | %tmp = alloca i64, align 8 # | %tmp8 = alloca double, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store i32 0, ptr %res, align 4 # | call void @llvm.memset.p0.i32(ptr align 1 %var, i8 0, i32 2, i1 false) # | %0 = load ptr, ptr %addr.addr, align 4 # | %strex = call i32 @llvm.arm.strex.p0(i32 4, ptr elementtype(i8) %0) # | %1 = load i32, ptr %res, align 4 # | %or = or i32 %1, %strex # | store i32 %or, ptr %res, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | %strex1 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i16) %2) # | %3 = load i32, ptr %res, align 4 # | %or2 = or i32 %3, %strex1 # | store i32 %or2, ptr %res, align 4 # | %4 = load ptr, ptr %addr.addr, align 4 # | %strex3 = call i32 @llvm.arm.strex.p0(i32 42, ptr elementtype(i32) %4) # | %5 = load i32, ptr %res, align 4 # | %or4 = or i32 %5, %strex3 # | store i32 %or4, ptr %res, align 4 # | store i64 42, ptr %tmp, align 8 # | %6 = load { i32, i32 }, ptr %tmp, align 8 # | %7 = extractvalue { i32, i32 } %6, 0 # | %8 = extractvalue { i32, i32 } %6, 1 # | %9 = load ptr, ptr %addr.addr, align 4 # | %strexd = call i32 @llvm.arm.strexd(i32 %7, i32 %8, ptr %9) # | %10 = load i32, ptr %res, align 4 # | %or5 = or i32 %10, %strexd # | store i32 %or5, ptr %res, align 4 # | %11 = load ptr, ptr %addr.addr, align 4 # | %strex6 = call i32 @llvm.arm.strex.p0(i32 1076754509, ptr elementtype(i32) %11) # | %12 = load i32, ptr %res, align 4 # | %or7 = or i32 %12, %strex6 # | store i32 %or7, ptr %res, align 4 # | store double 3.141590e+00, ptr %tmp8, align 8 # | %13 = load { i32, i32 }, ptr %tmp8, align 8 # | %14 = extractvalue { i32, i32 } %13, 0 # | %15 = extractvalue { i32, i32 } %13, 1 # | %16 = load ptr, ptr %addr.addr, align 4 # | %strexd9 = call i32 @llvm.arm.strexd(i32 %14, i32 %15, ptr %16) # | %17 = load i32, ptr %res, align 4 # | %or10 = or i32 %17, %strexd9 # | store i32 %or10, ptr %res, align 4 # | %18 = load ptr, ptr %addr.addr, ali # | ... # `---data was truncated (10240/16971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056081dc6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056081dc6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056081dc6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27ed449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27ed4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27ed449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27ed431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056081dc02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056081dc02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056081dbe7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056081d8970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056081d896dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f27ed432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27ed4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27ed4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056081d896cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm-exclusive.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c (943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc7aa9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc7aa930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc7aa9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa272933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa27298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa272933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa27291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc7aa2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc7aa2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc7aa10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc7a6c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc7a6bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa27291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa27291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa27291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc7a6bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c (944 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558bb2c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558bb2bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558bb2c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93baa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93baaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93baa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93baa31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558bb255e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005558bb255c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005558bb23ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558baeea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558baee9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93baa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93baa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93baa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558baee9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c (945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vsc # | ... # `---data was truncated (10240/121179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558ab55215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558ab54f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558ab55289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2e78c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2e78c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2e78c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2e78c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558ab4e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005558ab4e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005558ab4ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558ab17c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558ab17bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2e78c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2e78c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2e78c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558ab17bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c (946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a192f6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a192f6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a192f6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe24e21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe24e2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe24e21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe24e203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a192f03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a192f03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a192ee8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a192b980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a192b97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe24e204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe24e2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe24e2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a192b97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c (947 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s32_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_s64_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u8_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svrshl_single_u16_x2( %zdn.coerce0, %zdn.coerce1, %zm) #0 { # | entry: # | %zdn = alloca { , }, align 16 # | %zdn.addr = alloca { , }, align 16 # | %zm.addr = alloca , align 16 # | %0 = insertvalue { , } poison, %zdn.coerce0, 0 # | %1 = insertvalue { , } %0, %zdn.coerce1, 1 # | store { , } %1, ptr %zdn, align 16 # | %zdn1 = load { , }, ptr %zdn, align 16 # | store { , } %zdn1, ptr %zdn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %2 = load { , }, ptr %zdn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load , ptr %zm.addr, align 16 # | %6 = call { , } @llvm.aarch64.sve.urshl.single.x2.nxv8i16( %3, %4, %5) # | ret { , } %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , # | ... # `---data was truncated (10240/93119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000056364fd1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056364fd150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056364fd1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14b351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056364fcade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056364fcadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056364fc92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056364f9420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056364f941dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14b351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056364f941cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c (948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056029a48515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056029a4820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056029a48589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f727a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f727a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f727a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f727a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056029a41ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056029a41ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056029a3ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056029a0af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056029a0aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f727a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f727a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f727a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056029a0aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c (949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c (950 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv4i32(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.revh.nxv2i64(, , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_z( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( zeroinitializer, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv4i32( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u64_m( %inactive, %pg, %op) #0 { # | entry: # | %inactive.addr = alloca , align 16 # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %inactive, ptr %inactive.addr, align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %inactive.addr, align 16 # | %1 = load , ptr %pg.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %1) # | %4 = call @llvm.aarch64.sve.revh.nxv2i64( %0, %3, %2) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_s64_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv2i64( undef, %2, %1) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svrevh_u32_x( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.revh.nxv4i32( undef, %2, %1) # | # | ... # `---data was truncated (10240/11488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e5a7b2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5a7b2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5a7b2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8817b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8817b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8817b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8817b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5a7ac4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5a7ac4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5a7aa9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5a77590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5a7758dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8817b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8817b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8817b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5a7758cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c (951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571116fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005571116f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005571116fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8870333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f887038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8870333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f887031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055711168fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055711168fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557111674b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005571113240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557111323dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f887031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f887031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f887031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557111323cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c (952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055760c94d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055760c94a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055760c94d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6349649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63496a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6349649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6349631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055760c8e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055760c8e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055760c8c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055760c5770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055760c576dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6349632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63496330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63496330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055760c576cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c (953 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf7836515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf783620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf7836589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8175333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f817538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8175333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f817531b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf782fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf782fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf782dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf77f8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf77f8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f817531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f817531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f817531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf77f8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c (954 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v1(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 3 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_lane_bf16_v2(<4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_322 = alloca <4 x bfloat>, align 8 # | %__s0_322 = alloca <4 x bfloat>, align 8 # | %__s2_322 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %0, ptr %__s0_322, align 8 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_322, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_322, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <4 x bfloat>, ptr %__s0_322, align 8 # | store <4 x bfloat> %7, ptr %__s1, align 8 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %9, bfloat %8, i32 2 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp3, align 8 # | %10 = load <4 x bfloat>, ptr %ref.tmp3, align 8 # | store <4 x bfloat> %10, ptr %__ret, align 8 # | %11 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %11, ptr %tmp4, align 8 # | %12 = load <4 x bfloat>, ptr %tmp4, align 8 # | store <4 x bfloat> %12, ptr %__ret_322, align 8 # | %13 = load <4 x bfloat>, ptr %__ret_322, align 8 # | store <4 x bfloat> %13, ptr %tmp5, align 8 # | %14 = load <4 x bfloat>, ptr %tmp5, align 8 # | ret <4 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v1(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 2 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 0 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcopyq_lane_bf16_v2(<8 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x bfloat>, align 16 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_298 = alloca <8 x bfloat>, align 16 # | %__s0_298 = alloca <8 x bfloat>, align 16 # | %__s2_298 = alloca <4 x bfloat>, align 8 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp3 = alloca <8 x bfloat>, align 16 # | %tmp4 = alloca <8 x bfloat>, align 16 # | %tmp5 = alloca <8 x bfloat>, align 16 # | store <8 x bfloat> %a, ptr %a.addr, align 16 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <8 x bfloat>, ptr %a.addr, align 16 # | store <8 x bfloat> %0, ptr %__s0_298, align 16 # | %1 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %1, ptr %__s2_298, align 8 # | %2 = load <4 x bfloat>, ptr %__s2_298, align 8 # | store <4 x bfloat> %2, ptr %__s02, align 8 # | %3 = load <4 x bfloat>, ptr %__s02, align 8 # | %vget_lane = extractelement <4 x bfloat> %3, i32 0 # | store bfloat %vget_lane, ptr %ref.tmp, align 2 # | %4 = load bfloat, ptr %ref.tmp, align 2 # | store bfloat %4, ptr %__ret1, align 2 # | %5 = load bfloat, ptr %__ret1, align 2 # | store bfloat %5, ptr %tmp, align 2 # | %6 = load bfloat, ptr %tmp, align 2 # | store bfloat %6, ptr %__s0, align 2 # | %7 = load <8 x bfloat>, ptr %__s0_298, align 16 # | store <8 x bfloat> %7, ptr %__s1, align 16 # | %8 = load bfloat, ptr %__s0, align 2 # | %9 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %9, bfloat %8, i32 6 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x bfloat>, ptr %ref.tmp3, align 16 # | store <8 x bfloat> %10, ptr %__ret, align 16 # | %11 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %11, ptr %tmp4, align 16 # | %12 = load <8 x bfloat>, ptr %tmp4, align 16 # | store <8 x bfloat> %12, ptr %__ret_298, align 16 # | %13 = load <8 x bfloat>, ptr %__ret_298, align 16 # | store <8 x bfloat> %13, ptr %tmp5, align 16 # | %14 = load <8 x bfloat>, ptr %tmp5, align 16 # | ret <8 x bfloat> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcopy_laneq_bf16_v1(<4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 16 # | %__ret_374 = alloca <4 x bfloat>, align 8 # | %__s0_374 = alloca <4 x bfloat>, align 8 # | %__s2_374 = alloca <8 x bfloat>, align 16 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__ret1 = alloca bfloat, align 2 # | %__s02 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca bfloat, align 2 # | %tmp = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp3 = alloca <4 x bfloat>, align 8 # | %tmp4 = alloca <4 x bfloat>, align 8 # | %tmp5 = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.add # | ... # `---data was truncated (10240/18871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b47966a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4796670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b47966a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63ff449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63ff4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63ff449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63ff431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4795ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4795ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4795e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4792940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b479293dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63ff432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63ff4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63ff4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b479293cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-lane-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c (955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b08717515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b0871720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b08717589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfa8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfa878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfa8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfa871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b08710ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b08710ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b0870efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b086d9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b086d9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfa871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfa871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfa871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b086d9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c (956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055febc42e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055febc42b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055febc42e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f037e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f037e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f037e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f037e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055febc3c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055febc3c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055febc3a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055febc0580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055febc057dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f037e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f037e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f037e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055febc057cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c (957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2d416915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2d41660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2d416989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f863e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f863e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f863e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f863e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2d40fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a2d40fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2d40e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2d3d930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2d3d92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f863e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f863e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f863e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2d3d92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c (958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c (959 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645a34f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645a34f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645a34f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5dbd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5dbd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5dbd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5dbd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645a348be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645a348bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645a3470b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645a31200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645a311fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe5dbd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5dbd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5dbd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645a311fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c (960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f16m8( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32f16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32mf2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m1( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m2( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslidedown_vx_f32m4( %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %offset.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8f32.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8f32.i64(, , i # | ... # `---data was truncated (10240/120468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f2a40615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f2a4030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f2a40689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f076d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f076d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f076d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f076d431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f2a39be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f2a39bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f2a380b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f2a0300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f2a02fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f076d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f076d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f076d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f2a02fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c (961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; F # | ... # `---data was truncated (10240/102296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e69b3015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555e69b2d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555e69b3089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd67e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd67e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd67e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd67e0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e69ac5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555e69ac5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555e69aaab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555e6975a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555e69759dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd67e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd67e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd67e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e69759cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c (962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , alig # | ... # `---data was truncated (10240/41926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560aa22615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560aa2230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560aa22689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f05f541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05f54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f05f541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f05f5403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560aa1bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560aa1bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560aa1a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560a9e500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560a9e4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f05f5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05f54050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05f54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560a9e4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c (963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603b359815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603b35950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603b359889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc971249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9712a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc971249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc971231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603b352de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005603b352dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603b3512b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005603b31c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005603b31c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc971232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9712330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9712330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603b31c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c (964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005599c501b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005599c50180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005599c501b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff5a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff5a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff5a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff5a431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005599c4fb0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005599c4fb0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005599c4f95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005599c4c450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005599c4c44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff5a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff5a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff5a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005599c4c44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c (965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c (966 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c (967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ee247215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559ee246f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559ee247289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f996221bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99622725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f996221ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9962203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ee2407e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559ee2407c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559ee23ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559ee209c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559ee209bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9962204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99622050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99622050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ee209bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (968 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b8_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64 %0, i64 %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv16i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b16_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv8i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b32_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv4i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilege.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilege_b64_u64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1.addr = alloca i64, align 8 # | %op2.addr = alloca i64, align 8 # | store i64 %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | %0 = load i64, ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64 %0, i64 %1) # | %3 = extractvalue { , } %2, 0 # | %4 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %3) # | %5 = insertvalue { , } poison, %4, 0 # | %6 = extractvalue { , } %2, 1 # | %7 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %6) # | %8 = insertvalue { , } %5, %7, 1 # | ret { , } %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { , } @llvm.aarch64.sve.whilehs.x2.nxv2i1(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svwhilegt_b8_s64(i64 noundef %op1, i64 noundef %op2) #0 { # | entry: # | %op1 # | ... # `---data was truncated (10240/37926) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055e6fc4a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6fc4a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6fc4a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f22d0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22d04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f22d0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f22d0431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6fc43de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6fc43dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6fc422b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6fc0d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6fc0d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f22d0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22d04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22d04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6fc0d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c (969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d738f2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d738f250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d738f2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea10733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea1078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea10733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea1071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d738ebde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d738ebdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d738ea2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d738b520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d738b51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea1071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea1071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea1071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d738b51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c (970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec2801e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec2801b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec2801e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9baa61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9baa6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9baa61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9baa603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec27fb3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec27fb3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec27f98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec27c480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec27c47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9baa604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9baa6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9baa6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec27c47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c (971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1_tu( %maskedoff, %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %borrowin.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , < # | ... # `---data was truncated (10240/117389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6ee93115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6ee92e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6ee93189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe62ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe62ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe62ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe62ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6ee8c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6ee8c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6ee8abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6ee55b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6ee55add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe62ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe62ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe62ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6ee55acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c (972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f5a83815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560f5a8350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560f5a83889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b4c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b4c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b4c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b4c831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f5a7cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560f5a7cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560f5a7b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560f5a4620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560f5a461dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b4c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b4c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b4c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f5a461cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c (973 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f16mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <8 x half> @test_vmmlaq_f16_mf8(<8 x half> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %p0.addr = alloca <8 x half>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <8 x half> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <8 x half>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = bitcast <16 x i8> %4 to <8 x half> # | %fmmla1.i = call <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half> %fmmla.i, <16 x i8> %5, <16 x i8> %6) # | store <8 x half> %fmmla1.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.aarch64.neon.fmmla.v8f16.v16i8(<8 x half>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f16mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000560e7d9ac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e7d9a90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e7d9ac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f703a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f703a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f703a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f703a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e7d941e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e7d941c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e7d926b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e7d5d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e7d5d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f703a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f703a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f703a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e7d5d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c (974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f2b6e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f2b6e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f2b6e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8048705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f804875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8048705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80486ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f2b67de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f2b67dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f2b662b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f2b3120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f2b311dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80486eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80486ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80486ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f2b311cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c (975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f48c57115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f48c56e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f48c57189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbde4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbde42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbde4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbde4231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48c506e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f48c506c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f48c4ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f48c19b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f48c19add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbde4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbde42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbde42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f48c19acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c (976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615fb35f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615fb35c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005615fb35f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1603733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f160378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1603733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f160371b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615fb2f4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615fb2f4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615fb2d9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615faf890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615faf88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f160371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f160371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f160371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615faf88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c (977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8c69b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8c69b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8c69b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc60a849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc60a8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc60a849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc60a831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8c694ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8c694ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8c6933b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8c65e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8c65e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc60a832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc60a8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc60a8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8c65e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c (978 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu( %maske # | ... # `---data was truncated (10240/75397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633312e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633312e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633312e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b79b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b79b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b79b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b79b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056333127ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056333127ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056333125fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563330f0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563330f0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b79b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b79b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b79b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563330f0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c (979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | re # | ... # `---data was truncated (10240/120915) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5cba3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5cba370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5cba3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6bdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6bdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6bdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6bdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5cb9cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5cb9cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5cb9b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5cb6640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5cb663dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6bdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6bdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6bdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5cb663cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c (980 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e61349415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6134910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e61349489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b8fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b8fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b8fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b8fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e613429e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e613429c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e61340eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6130be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6130bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b8fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b8fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b8fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6130bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c (981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16f32.nxv8f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align # | ... # `---data was truncated (10240/102872) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056555022d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056555022a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056555022d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a9ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a9ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a9ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a9feed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005655501c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005655501c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005655501a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056554fe570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056554fe56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a9feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a9feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a9feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056554fe56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c (982 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ebd59fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ebd59fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ebd59fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5611449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56114a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5611449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5611431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ebd5992e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ebd5992c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ebd5977b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ebd56270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ebd5626dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5611432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56114330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56114330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ebd5626cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c (983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c (984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/126428) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a070de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a070db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a070de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc4bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc4bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc4bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc4bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a07073e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a07073c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a07058b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a06d080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a06d07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc4bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc4bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc4bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a06d07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c (985 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b6a22f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b6a22c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b6a22f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdab7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdab78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdab7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdab7831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b6a1c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b6a1c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b6a1a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b69e590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b69e58dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdab7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdab78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdab78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b69e58cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c (986 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c (987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627981fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627981f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627981fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9be81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9be8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9be81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9be803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056279818fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056279818fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562798174b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562797e240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562797e23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb9be804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9be8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9be8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562797e23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c (988 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbbc88e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbbc88b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbbc88e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc897c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc897ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc897c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc897c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbbc823e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbbc823c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbbc808b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbbc4b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbbc4b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc897c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc897c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc897c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbbc4b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c (989 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c (990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0cb26515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a0cb2620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a0cb26589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2137249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21372a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2137249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2137231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0cb1fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a0cb1fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a0cb1dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a0cae8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a0cae8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2137232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21372330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21372330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0cae8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c (991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c (992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056519730015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005651972fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056519730089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95f2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95f218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95f2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95f211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565197295e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565197295c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056519727ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565196f2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565196f29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95f211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95f211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95f211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565196f29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c (993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6ce4c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6ce4c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6ce4c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcda001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcda00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcda001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcda0003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6ce458e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f6ce458c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6ce43db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6ce0ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6ce0ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcda0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcda00050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcda00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6ce0eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c (994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4f32.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzip_vv_f32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8f32.nxv4f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwi # | ... # `---data was truncated (10240/235604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055990d9df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055990d9dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055990d9df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39c2533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39c258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39c2533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39c251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055990d974e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055990d974c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055990d959b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055990d6090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055990d608dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f39c251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39c251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39c251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055990d608cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c (995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c (996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638c56aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638c56a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005638c56aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9432705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f943275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9432705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94326ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638c563fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638c563fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638c5624b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638c52d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638c52d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f94326eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94326ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94326ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638c52d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c (997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc4a7dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc4a7d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc4a7dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e3881bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e388725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e3881ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e38803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc4a771e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc4a771c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc4a756b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc4a4060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc4a405dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e38804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e388050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e388050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc4a405cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c (998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c (999 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsub.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsub.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsub_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c (1000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.a # | ... # `---data was truncated (10240/86092) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c2f21515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c2f2120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c2f21589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea9af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c2f1aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c2f1aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c2f18fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c2ee3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c2ee3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c2ee3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c (1001 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %2, ptr %1) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv4i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i16.p0( %3, ptr %4) # | %6 = zext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_s32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i16.nxv4i32(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64( %2, %1, i64 0) # | %4 = zext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i16.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1uh_gather_u32base_u32( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.a # | ... # `---data was truncated (10240/36974) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim # | #0 0x000055e64c47115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e64c46e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e64c47189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba28e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba28ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba28e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba28e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e64c406e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e64c406c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e64c3ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e64c09b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e64c09add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fba28e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba28e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba28e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e64c09acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c (1002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c (1003 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vector-compare-ops.c (1004 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vector-compare-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp eq %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_u64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp eq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @eq_f64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = fcmp oeq %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_bool( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 2 # | %b.addr = alloca , align 2 # | store %a, ptr %a.addr, align 2 # | store %b, ptr %b.addr, align 2 # | %0 = load , ptr %a.addr, align 2 # | %1 = load , ptr %b.addr, align 2 # | %cmp = icmp ne %0, %1 # | ret %cmp # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i8( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i16( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i32( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | store %a, ptr %a.addr, align 16 # | store %b, ptr %b.addr, align 16 # | %0 = load , ptr %a.addr, align 16 # | %1 = load , ptr %b.addr, align 16 # | %cmp = icmp ne %0, %1 # | %sext = sext %cmp to # | ret %sext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @neq_i64( %a, %b) #0 { # | entry: # | %a.addr = alloca , align 16 # | %b.addr = alloca , align 16 # | stor # | ... # `---data was truncated (10240/44453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055afe5a3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055afe5a2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055afe5a3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a40f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a40f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a40f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a40f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055afe59c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055afe59c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055afe59acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055afe565c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055afe565bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5a40f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a40f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a40f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055afe565bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vector-compare-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c (1005 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7f7e1e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7f7e1b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7f7e1e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6451a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6451aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6451a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6451a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7f7db3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e7f7db3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e7f7d98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e7f7a480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e7f7a47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6451a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6451a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6451a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7f7a47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c (1006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624a15b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624a15b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624a15b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f378bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f378bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f378bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f378bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624a154be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624a154bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624a1530b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624a11e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624a11dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f378bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f378bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f378bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624a11dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c (1007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563713b9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563713b960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563713b9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01faa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563713b2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563713b2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563713b13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005637137c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005637137c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01faa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637137c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c (1008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m1_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv4f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m2_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv8f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f16m4_f16m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %val.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32f16.nxv16f16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv16f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv4f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv2f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m2_f32m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv8f32.nxv4f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f32.nxv4f32(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_f32m1_f32m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 4 # | store %dest, ptr %dest.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 4 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %val.addr, align 4 # | %2 = call @llvm.vector.insert.nxv16f32.nxv2f32( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c (1009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8bcbb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8bcbb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8bcbb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9bc7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9bc74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9bc7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9bc7431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8bcb48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8bcb48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8bcb2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8bc7dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8bc7dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9bc7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9bc74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9bc74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8bc7dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c (1010 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e77b2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557e77b290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557e77b2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4350049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43500a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4350049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4350031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e77ac1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557e77ac1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557e77aa6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557e777560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557e77755dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4350032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43500330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43500330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e77755cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c (1011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vand.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9131ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9131c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9131ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e39733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e3978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e39733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e3971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c91315fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c91315fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c913144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c912df40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c912df3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e3971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e3971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e3971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c912df3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c (1012 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv16i8(i8, i8) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv8i16(i16, i16) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_s64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.index.nxv2i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u8(i8 noundef %base, i8 noundef %step) #0 { # | entry: # | %base.addr = alloca i8, align 1 # | %step.addr = alloca i8, align 1 # | store i8 %base, ptr %base.addr, align 1 # | store i8 %step, ptr %step.addr, align 1 # | %0 = load i8, ptr %base.addr, align 1 # | %1 = load i8, ptr %step.addr, align 1 # | %2 = call @llvm.aarch64.sve.index.nxv16i8(i8 %0, i8 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u16(i16 noundef %base, i16 noundef %step) #0 { # | entry: # | %base.addr = alloca i16, align 2 # | %step.addr = alloca i16, align 2 # | store i16 %base, ptr %base.addr, align 2 # | store i16 %step, ptr %step.addr, align 2 # | %0 = load i16, ptr %base.addr, align 2 # | %1 = load i16, ptr %step.addr, align 2 # | %2 = call @llvm.aarch64.sve.index.nxv8i16(i16 %0, i16 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u32(i32 noundef %base, i32 noundef %step) #0 { # | entry: # | %base.addr = alloca i32, align 4 # | %step.addr = alloca i32, align 4 # | store i32 %base, ptr %base.addr, align 4 # | store i32 %step, ptr %step.addr, align 4 # | %0 = load i32, ptr %base.addr, align 4 # | %1 = load i32, ptr %step.addr, align 4 # | %2 = call @llvm.aarch64.sve.index.nxv4i32(i32 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svindex_u64(i64 noundef %base, i64 noundef %step) #0 { # | entry: # | %base.addr = alloca i64, align 8 # | %step.addr = alloca i64, align 8 # | store i64 %base, ptr %base.addr, align 8 # | store i64 %step, ptr %step.addr, align 8 # | %0 = load i64, ptr %base.addr, align 8 # | %1 = load i64, ptr %step.addr, align 8 # | %2 = call @llvm.aarch64.sve.index.nxv2i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000559daf6f415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559daf6f10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559daf6f489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe9db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe9db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe9db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe9db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559daf689e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559daf689c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559daf66eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559daf31e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559daf31ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbe9db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe9db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe9db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559daf31dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_index.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c (1013 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055969c86115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055969c85e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055969c86189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa391249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3912a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa391249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa391231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055969c7f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055969c7f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055969c7dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055969c48b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055969c48add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa391232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3912330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3912330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055969c48acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c (1014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055809139c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580913990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055809139c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbb6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbb6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbb6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbb6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558091331e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558091331c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558091316b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558090fc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558090fc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcbb6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbb6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbb6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558090fc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c (1015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b292fb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b292fb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b292fb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe84049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe84049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe84031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b292f4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b292f4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b292f31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b292be10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b292be0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe84032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe840330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b292be0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c (1016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600f590415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005600f59010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005600f590489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3946849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3946849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3946831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600f5899e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005600f5899c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005600f587eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600f552e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600f552ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3946832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39468330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600f552dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c (1017 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -Werror -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv16i8(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv16i8( %0, %1, i32 4) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8i16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8i16( %0, %1, i32 5) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4i32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4i32( %0, %1, i32 3) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_u64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2i64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_s64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2i64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8f16( %0, %1, i32 7) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8f16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f32( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv4f32( %0, %1, i32 2) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv4f32(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_f64( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv2f64( %0, %1, i32 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv2f64(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_bf16( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, align 16 # | %2 = call @llvm.aarch64.sve.extq.nxv8bf16( %0, %1, i32 6) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.extq.nxv8bf16(, , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svextq_mf8( %zn, %zm) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %zm.addr = alloca , align 16 # | store %zn, ptr %zn.addr, align 16 # | store %zm, ptr %zm.addr, align 16 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load , ptr %zm.addr, # | ... # `---data was truncated (10240/11061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055629be2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055629be230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055629be2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4dc449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4dc4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4dc449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4dc431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055629bdbbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055629bdbbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055629bda0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055629ba500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055629ba4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4dc432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4dc4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4dc4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055629ba4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c (1018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c (1019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_f64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c (1020 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call { , } @llvm.aarch64.sve.ld2.sret.nxv16i8.p0( %0, ptr %1) # | ret { , } %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8i16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4i32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2i64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f16( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv8f16.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm.aarch64.sve.ld2.sret.nxv4f32.p0(, ptr) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_svld2_f64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call { , } @llvm.aarch64.sve.ld2.sret.nxv2f64.p0( %2, ptr %1) # | ret { , } %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { , } @llvm # | ... # `---data was truncated (10240/24404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000562d9d62015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d9d61d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d9d62089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ca105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ca15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ca105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ca0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d9d5b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d9d5b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d9d59ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d9d24a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d9d249dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd3ca0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ca0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ca0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d9d249cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c (1021 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qrdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqrdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qrdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqrdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qrdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 # | ... # `---data was truncated (10240/11881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056405649b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640564980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056405649b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d62d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d62d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d62d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d62ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564056430e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564056430c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564056415b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640560c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640560c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d62ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d62cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d62cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640560c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c (1022 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9144d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9144d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9144d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5132449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51324a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5132449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5132431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e91446de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e91446dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e914452b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9141020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e914101dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5132432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51324330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51324330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e914101cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c (1023 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv16i8(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv8i16(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv4i32(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_s64_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv2i64( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.msb.nxv2i64(, , , ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u8_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = select %0, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.msb.nxv16i8( %0, %4, %2, %3) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u16_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv8i16( %4, %5, %2, %3) # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmsb_u32_z( %pg, %op1, %op2, %op3) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = load , ptr %op3.addr, align 16 # | %4 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %5 = select %4, %1, zeroinitializer # | %6 = call @llvm.aarch64.sve.msb.nxv4i32( %4, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c (1024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a3b1ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a3b1ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a3b1ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0245449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02454a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0245449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0245431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a3b184e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a3b184c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a3b169b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a3ae190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a3ae18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0245432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02454330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02454330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a3ae18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c (1025 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.aarch64.sve.prf.nxv4i1.p0(, ptr, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_1( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_2( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_3( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_4( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_5( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_6( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 8) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_7( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 9) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_8( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 10) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_9( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 11) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_10( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 12) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_11( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %2, ptr %1, i32 13) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_vnum( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | call void @llvm.aarch64.sve.prf.nxv4i1.p0( %3, ptr %4, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u32base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | call void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32( %2, %1, i64 0, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.aarch64.sve.prfw.gather.scalar.offset.nxv4i32(, , i64, i32 immarg) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local void @test_svprfw_gather_u64base( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store # | ... # `---data was truncated (10240/17826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556d0819815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d081950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d0819889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e1f449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e1f4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e1f449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e1f431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d0812de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d0812dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d08112b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d07dc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d07dc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e1f432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e1f4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e1f4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d07dc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c (1026 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/10610) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558afe87815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558afe8750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558afe87889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd1fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd1fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd1fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd1fc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558afe80de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558afe80dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558afe7f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558afe4a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558afe4a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd1fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd1fc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd1fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558afe4a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c (1027 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d0e2f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d0e2f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d0e2f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7f8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7f88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7f8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7f8831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d0e28be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d0e28bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d0e270b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d0df200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d0df1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd7f8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7f88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7f88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d0df1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c (1028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cacbfeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cacbfe80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cacbfeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a0a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a0a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cacbf80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cacbf80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cacbf65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cacbc150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cacbc14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a0a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cacbc14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c (1029 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bcc1a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556bcc1a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556bcc1a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce32e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce32e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce32e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce32e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bcc13be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556bcc13bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556bcc120b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556bcbdd00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556bcbdcfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce32e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce32e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce32e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bcbdcfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c (1030 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c7372915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c737260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c7372989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b3231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c736bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c736bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c736a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c733530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c73352dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9b3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c73352cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp (1031 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vbicq_n_s1617__simd128_int16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vbicq_n_u3218__simd128_uint32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <4 x i32> @_Z16test_vorrq_n_s3217__simd128_int32_t(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z16test_vorrq_n_u1618__simd128_uint16_t(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef zeroext i16 @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <8 x i16> @_Z14test_vld1q_u16PKt(ptr noundef %base) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | store ptr %base, ptr %base.addr, align 4 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %0, align 2 # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(ptr noundef %base, <4 x i32> noundef %value, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %value.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | call void @llvm.masked.store.v4i32.p0(<4 x i32> %0, ptr align 4 %1, <4 x i1> %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr captures(none), <4 x i1>) #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc noundef <2 x i64> @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %1, i32 576) # | %3 = extractvalue { <2 x i64>, <2 x i64> } %2, 1 # | store <2 x i64> %3, ptr %0, align 8 # | %4 = extractvalue { <2 x i64>, <2 x i64> } %2, 0 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64>, i32) #3 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local arm_aapcs_vfpcc void @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(ptr noundef %addr, <4 x i32> noundef %value) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %value.addr = alloca <4 x i32>, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store <4 x i32> %value, ptr %value.addr, align 8 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = load <4 x i32>, ptr %value.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> %1, i32 64, <4 x i32> %2) # | store <4 x i32> %3, ptr %0, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32>, i32, <4 x i32>) #4 # | # | attributes #0 = { mustprogress noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #4 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef18aeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef18ae80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef18aeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8220733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f822078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8220733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f822071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef18a80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef18a80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef18a65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef187150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef18714dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f822071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f822071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f822071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef18714cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c (1032 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c (1033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/78328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562dbb79615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562dbb7930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562dbb79689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effd2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effd20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effd2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effd2031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dbb72be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562dbb72bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562dbb710b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562dbb3c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562dbb3bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007effd2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effd20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effd20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dbb3bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c (1034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c23920f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c23920c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c23920f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57e4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57e478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57e4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57e471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2391a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2391a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c239189b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c238e390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c238e38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f57e471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57e471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57e471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c238e38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c (1035 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3c439a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b3c43970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b3c439a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe552a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe552aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe552a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe552a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3c432fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3c432fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3c4314b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b3c3fc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b3c3fc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe552a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe552a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe552a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3c3fc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c (1036 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4c4a2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4c4a210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4c4a2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f046bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f046bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f046bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f046bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4c49b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a4c49b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a4c499eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4c464e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4c464ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f046bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f046bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f046bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4c464dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c (1037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598ef3a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005598ef3a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005598ef3a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0311333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f031138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0311333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f031131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598ef33ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598ef33ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598ef31fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598eefcf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005598eefcedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f031131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f031131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f031131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598eefcecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c (1038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005601bad7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005601bad710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005601bad7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a3ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a3aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a3ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a3ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601bad09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005601bad09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005601baceeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005601ba99e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005601ba99ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a3ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a3ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a3ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005601ba99dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c (1039 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c (1040 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3b8e9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3b8e8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3b8e9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbde849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbde8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbde849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbde831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3b8e25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c3b8e25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c3b8e0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c3b8aba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c3b8ab9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbde832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbde8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbde8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3b8ab9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c (1041 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c (1042 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617782af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005617782ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005617782af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e62049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e620a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e62049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e62031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561778244e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561778244c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561778229b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561777ed90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561777ed8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e62032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e620330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e620330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561777ed8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c (1043 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvt.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvtn_f32_x4( %zn.coerce0, %zn.coerce1, %zn.coerce2, %zn.coerce3, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , , , }, align 16 # | %zn.addr = alloca { , , , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , , , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , , , } %0, %zn.coerce1, 1 # | %2 = insertvalue { , , , } %1, %zn.coerce2, 2 # | %3 = insertvalue { , , , } %2, %zn.coerce3, 3 # | store { , , , } %3, ptr %zn, align 16 # | %zn1 = load { , , , }, ptr %zn, align 16 # | store { , , , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %4 = load { , , , }, ptr %zn.addr, align 16 # | %5 = extractvalue { , , , } %4, 0 # | %6 = extractvalue { , , , } %4, 1 # | %7 = extractvalue { , , , } %4, 2 # | %8 = extractvalue { , , , } %4, 3 # | %9 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %9) # | %10 = call @llvm.aarch64.sve.fp8.cvtn.x4( %5, %6, %7, %8) # | ret %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvtn.x4(, , , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_cvt_bf16_x2( %zn.coerce0, %zn.coerce1, i64 noundef %fpmr) #0 { # | entry: # | %zn = alloca { , }, align 16 # | %zn.addr = alloca { , }, align 16 # | %fpmr.addr = alloca i64, align 8 # | %0 = insertvalue { , } poison, %zn.coerce0, 0 # | %1 = insertvalue { , } %0, %zn.coerce1, 1 # | store { , } %1, ptr %zn, align 16 # | %zn1 = load { , }, ptr %zn, align 16 # | store { , } %zn1, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %2 = load { , }, ptr %zn.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | %4 = extractvalue { , } %2, 1 # | %5 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %5) # | %6 = call @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16( %3, %4) # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt1_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr, align 16 # | store i64 %fpmr, ptr %fpmr.addr, align 8 # | %0 = load , ptr %zn.addr, align 16 # | %1 = load i64, ptr %fpmr.addr, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %1) # | %2 = call { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16( %0) # | ret { , } %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) # | declare { , } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local { , } @test_cvt2_f16_x2( %zn, i64 noundef %fpmr) #0 { # | entry: # | %zn.addr = alloca , align 16 # | %fpmr.addr = alloca i64, align 8 # | store %zn, ptr %zn.addr # | ... # `---data was truncated (10240/17058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x00005618cf57515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005618cf5720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005618cf57589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ff7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ff72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ff7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ff7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618cf50ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005618cf50ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005618cf4efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005618cf19f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005618cf19edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ff7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ff72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ff72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618cf19ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c (1044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eca913515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eca91320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eca913589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fe2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fe2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fe2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fe2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eca90cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eca90cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eca90afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eca8d5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eca8d5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9fe2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fe2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fe2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eca8d5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/thinlto_embed_bitcode.ll (1045 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_embed_bitcode.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/Inputs/start-lib1.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_embed_bitcode.ll.tmp1.bc # | #0 0x000055b2d111715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2d11140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2d111789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f498981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49898725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f498981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4989803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2d10ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2d10acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2d1091b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2d0d410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2d0d40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4989804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49898050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49898050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2d0d40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminaq.c (1046 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | %4 = load <16 x i8>, ptr %a.addr, align 8 # | %5 = icmp ule <16 x i8> %4, %3 # | %6 = select <16 x i1> %5, <16 x i8> %4, <16 x i8> %3 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | %4 = load <8 x i16>, ptr %a.addr, align 8 # | %5 = icmp ule <8 x i16> %4, %3 # | %6 = select <8 x i1> %5, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | %4 = load <4 x i32>, ptr %a.addr, align 8 # | %5 = icmp ule <4 x i32> %4, %3 # | %6 = select <4 x i1> %5, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminaq_m_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminaq_m_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmina.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminaq_m_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmina.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570d351115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570d350e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570d351189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d0ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d0caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d0ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d0ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570d34a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570d34a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570d348bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570d313b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570d313add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d0ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d0ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d0ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570d313acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c (1047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562699dda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562699dd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562699dda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0952849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09528a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0952849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0952831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562699d6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562699d6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562699d54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562699a040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562699a03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0952832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09528330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09528330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562699a03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c (1048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568594fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568594f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005568594fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18c5d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18c5d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18c5d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18c5ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556859491e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556859491c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556859476b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005568591260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556859125dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f18c5ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18c5cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18c5cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556859125cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c (1049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575587a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055755879f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575587a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff19b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff19b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff19b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff19b431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557558737e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557558737c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055755871cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575583cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575583cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff19b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff19b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff19b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575583cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c (1050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec7319815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec731950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec7319889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78dba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78dbaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78dba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78dba31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec7312de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec7312dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec73112b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec72dc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec72dc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f78dba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78dba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78dba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec72dc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/compare.c (1051 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/compare.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fcmp oeq <8 x half> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fcmp oeq <4 x float> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp eq <16 x i8> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp eq <8 x i16> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp eq <4 x i32> %0, %1 # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fcmp oeq <8 x half> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_f32(<4 x float> noundef %a, float noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = fcmp oeq <4 x float> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = icmp eq <4 x i32> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = icmp eq <16 x i8> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = icmp eq <8 x i16> %0, %.splat # | %3 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vcmpeqq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = # | ... # `---data was truncated (10240/125481) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005578c2e5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005578c2e530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005578c2e5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddc1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddc12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddc1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddc1231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005578c2debe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005578c2debc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005578c2dd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005578c2a800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005578c2a7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fddc1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddc12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddc12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005578c2a7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/compare.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c (1052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564892a0415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564892a010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564892a0489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0624e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0624ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0624e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0624e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564892999e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564892999c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056489297eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056489262e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056489262ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0624e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0624e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0624e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056489262dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c (1053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056370d99215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056370d98f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056370d99289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff41e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff41e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff41e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff41e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056370d927e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056370d927c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056370d90cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056370d5bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056370d5bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff41e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff41e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff41e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056370d5bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c (1054 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c (1055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6515c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6515c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6515c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c7cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c7cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c7cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c7cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65155ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f65155ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f65153fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6511ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6511eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c7cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c7cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c7cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6511eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c (1056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600ede5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005600ede5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005600ede5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6055849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60558a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6055849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6055831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600eddf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005600eddf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005600eddd7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600eda870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600eda86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6055832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60558330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60558330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600eda86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c (1057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.add # | ... # `---data was truncated (10240/153913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bb9fc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557bb9fc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557bb9fc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effc9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effc9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effc9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effc9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bb9f59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557bb9f59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557bb9f3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557bb9bee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557bb9beddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007effc9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effc9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effc9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bb9bedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c (1058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c (1059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_i8m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv64i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i8.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse8_v_u8m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %bas # | ... # `---data was truncated (10240/29817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c5cb4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555c5cb480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555c5cb4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f213be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f213bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f213be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f213be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c5cae0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555c5cae0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555c5cac5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555c5c7750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555c5c774dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f213be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f213be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f213be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c5c774cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c (1060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055601ef0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055601ef040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055601ef0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f633ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f633ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f633ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f633ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055601ee9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055601ee9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055601ee81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055601eb310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055601eb30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f633ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f633ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f633ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055601eb30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c (1061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591735f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591735f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591735f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ed7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ed7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ed7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ed7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559173588e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559173588c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055917356db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055917321d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055917321cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ed7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ed7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ed7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055917321ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c (1062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ec228915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563ec22860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563ec228989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d1c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d1c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d1c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d1c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ec221ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563ec221ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563ec2203b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563ec1eb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563ec1eb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d1c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d1c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d1c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ec1eb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c (1063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipo_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b49a88215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b49a87f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b49a88289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa781a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa781aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa781a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa781a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b49a817e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b49a817c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b49a7fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b49a4ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b49a4abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa781a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa781a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa781a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b49a4abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c (1064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561e819e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561e819b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561e819e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f116901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11690725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f116901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1169003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561e8133e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561e8133c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561e8118b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561e7dc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561e7dc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1169004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11690050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11690050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561e7dc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c (1065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7289d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a7289cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a7289d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f546a449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f546a4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f546a449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f546a431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a728965e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a728965c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a72894ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a7285fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a7285f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f546a432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f546a4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f546a4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7285f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c (1066 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f # | ... # `---data was truncated (10240/165246) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568f6c1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568f6c160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005568f6c1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f50b4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50b42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f50b4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50b4231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568f6baee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005568f6baec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005568f6b93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005568f68430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005568f6842dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f50b4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50b42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50b42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005568f6842cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c (1067 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592626df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005592626dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005592626df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc1ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc1ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc1ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc1ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559262674e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559262674c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559262659b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592623090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559262308dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcc1ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc1ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc1ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559262308cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c (1068 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v9.6a -target-feature +f8f32mm -target-feature +fp8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local <4 x float> @test_vmmlaq_f32_mf8(<4 x float> noundef %p0, <16 x i8> %p1, <16 x i8> %p2, i64 noundef %p3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__p2.addr.i = alloca <16 x i8>, align 16 # | %__p3.addr.i = alloca i64, align 8 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <4 x float>, align 16 # | %p0.addr = alloca <4 x float>, align 16 # | %p1.addr = alloca <16 x i8>, align 16 # | %p2.addr = alloca <16 x i8>, align 16 # | %p3.addr = alloca i64, align 8 # | store <4 x float> %p0, ptr %p0.addr, align 16 # | store <16 x i8> %p1, ptr %p1.addr, align 16 # | store <16 x i8> %p2, ptr %p2.addr, align 16 # | store i64 %p3, ptr %p3.addr, align 8 # | %0 = load <4 x float>, ptr %p0.addr, align 16 # | %1 = load <16 x i8>, ptr %p1.addr, align 16 # | %2 = load <16 x i8>, ptr %p2.addr, align 16 # | %3 = load i64, ptr %p3.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | store <16 x i8> %2, ptr %__p2.addr.i, align 16 # | store i64 %3, ptr %__p3.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %7 = load i64, ptr %__p3.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %7) # | %fmmla.i = call <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float> %4, <16 x i8> %5, <16 x i8> %6) # | store <4 x float> %fmmla.i, ptr %ref.tmp.i, align 16 # | %8 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %8, ptr %__ret.i, align 16 # | %9 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) # | declare void @llvm.aarch64.set.fpmr(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+cmpbr,+complxnum,+cpa,+crc,+cssc,+dit,+dotprod,+f8f32mm,+faminmax,+flagm,+fp-armv8,+fp8,+fullfp16,+hbc,+hinte,+i8mm,+jsconv,+lse,+lsui,+lut,+mec,+mops,+neon,+occmo,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9.5a,+v9.6a,+v9a,+wfxt" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005569e836115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569e835e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569e836189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed25e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed25ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed25e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed25e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569e82f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569e82f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569e82dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569e7f8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569e7f8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed25e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed25e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed25e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569e7f8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c (1069 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b94cbd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b94cbd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b94cbd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e8a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e8a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e8a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e8a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b94cb68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b94cb68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b94cb4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b94c7fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b94c7fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e8a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e8a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e8a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b94c7fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c (1070 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055661aa0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055661aa040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055661aa0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa00333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa0038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa00333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa0031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055661a99ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055661a99cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055661a981b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055661a6310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055661a630dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa0031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa0031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa0031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055661a630cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c (1071 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf4_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv1f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv1f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16mf2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv2f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv2f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m1_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv4f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv4f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_ext_v_f16m2_f16m8( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32f16.nxv8f16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32f16.nxv8f16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/83080) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564699e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564699df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005564699e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5130733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f513078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5130733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f513071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556469977e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556469977c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055646995cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055646960c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055646960bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f513071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f513071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f513071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055646960bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c (1072 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555608f6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555608f5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555608f6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f808a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f808a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f808a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f808a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555608ef6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555608ef6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555608edbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555608b8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555608b8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f808a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f808a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f808a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555608b8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c (1073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/296943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c98a95515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c98a9520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c98a95589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a8e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a8e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a8e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a8e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c98a8eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c98a8eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c98a8cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c98a57f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c98a57edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a8e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a8e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a8e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c98a57ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c (1074 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f92bab415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f92bab10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f92bab489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d5b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d5b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d5b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d5b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f92ba49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f92ba49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f92ba2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f92b6de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f92b6dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d5b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d5b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d5b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f92b6ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c (1075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d62469815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6246950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d62469889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b80533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b8058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b80533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b8051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d62462de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d62462dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d624612b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6242c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6242c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b8051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b8051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b8051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6242c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c (1076 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8.i64(< # | ... # `---data was truncated (10240/17495) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562af305a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562af30570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562af305a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8efae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8efae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8efae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8efae03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562af2fefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562af2fefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562af2fd4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562af2c840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562af2c83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8efae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8efae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8efae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562af2c83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c (1077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bef5e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562bef5e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562bef5e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51fc61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51fc6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51fc61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51fc603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bef57ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562bef57ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562bef55fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562bef20f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562bef20edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f51fc604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51fc6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51fc6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bef20ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c (1078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056126342b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612634280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056126342b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc411a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc411a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc411a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc411a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612633c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005612633c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005612633a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005612630550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561263054dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc411a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc411a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc411a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561263054cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c (1079 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e4e5d6a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e4e5d670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e4e5d6a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f496b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f496b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f496b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f496b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e4e5cffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e4e5cffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e4e5ce4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e4e59940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e4e5993dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f496b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f496b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f496b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4e5993cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/admin.c (1080 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/admin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcreateq_f16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x half> # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcreateq_f32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x float> # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_s16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_s32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_s64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_s8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcreateq_u16(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcreateq_u32(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcreateq_u64(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcreateq_u8(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = insertelement <2 x i64> poison, i64 %0, i64 0 # | %2 = load i64, ptr %b.addr, align 8 # | %3 = insertelement <2 x i64> %1, i64 %2, i64 1 # | %4 = bitcast <2 x i64> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_polymorphic_f16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_polymorphic_f32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_s8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_s16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_s32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_s64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_polymorphic_u8(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_polymorphic_u16(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_polymorphic_u32(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_polymorphic_u64(ptr noundef %funcptr) #0 { # | entry: # | %funcptr.addr = alloca ptr, align 4 # | store ptr %funcptr, ptr %funcptr.addr, align 4 # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vuninitializedq_f16() #0 { # | entry: # | ret <8 x half> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vuninitializedq_f32() #0 { # | entry: # | ret <4 x float> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_s16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_s32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_s64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_s8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vuninitializedq_u16() #0 { # | entry: # | ret <8 x i16> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vuninitializedq_u32() #0 { # | entry: # | ret <4 x i32> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vuninitializedq_u64() #0 { # | entry: # | ret <2 x i64> undef # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vuninitializedq_u8() #0 { # | entry: # | ret <16 x i8> undef # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000056345b92515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056345b9220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056345b92589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dcf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dcf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dcf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dcf031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056345b8bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056345b8bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056345b89fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056345b54f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056345b54edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1dcf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dcf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dcf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056345b54ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/admin.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c (1081 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fc167715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fc16740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fc167789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadde649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadde6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadde649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadde631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fc160ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fc160cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fc15f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fc12a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fc12a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadde632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadde6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadde6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fc12a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c (1082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c (1083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @orc_b_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.orc.b.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @ctz_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @cpop_32(i32 noundef %a) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.ctpop.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.orc.b.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.cttz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctpop.i32(i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558258c2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558258c270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558258c2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4d5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4d5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4d5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4d5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558258bbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558258bbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558258ba4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582588540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558258853dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc4d5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4d5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4d5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558258853cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbb.c -check-prefix=RV32ZBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c (1084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align # | ... # `---data was truncated (10240/22890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6919a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6919a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6919a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f007ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f007ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f007ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f007ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f69193be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f69193bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f691920b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6915d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6915cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f007ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f007ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f007ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6915cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c (1085 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_x_f_v_i32mf2(< # | ... # `---data was truncated (10240/119297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a8278315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a827800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a8278389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f78b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f78b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f78b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f78b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a82718e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a82718c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a826fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a823ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a823acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f78b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f78b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f78b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a823accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c (1086 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6ddb8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6ddb830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a6ddb8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5a2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5a2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5a2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5a2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6ddb1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a6ddb1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a6ddb00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a6dd7b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a6dd7afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb5a2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5a2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5a2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6dd7afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/poly128.c (1087 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/poly128.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vldrq_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | ret i128 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_ld_st_p128(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %__s1 = alloca i128, align 16 # | %__ret = alloca i128, align 16 # | %ref.tmp = alloca i128, align 16 # | %tmp = alloca i128, align 16 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i128, ptr %0, align 16 # | store i128 %1, ptr %ref.tmp, align 16 # | %2 = load i128, ptr %ref.tmp, align 16 # | store i128 %2, ptr %__ret, align 16 # | %3 = load i128, ptr %__ret, align 16 # | store i128 %3, ptr %tmp, align 16 # | %4 = load i128, ptr %tmp, align 16 # | store i128 %4, ptr %__s1, align 16 # | %5 = load ptr, ptr %ptr.addr, align 8 # | %add.ptr = getelementptr inbounds i128, ptr %5, i64 1 # | %6 = load i128, ptr %__s1, align 16 # | store i128 %6, ptr %add.ptr, align 16 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #1 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca i128, align 16 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load i64, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %2, i64 %3) # | %vmull_p641.i = bitcast <16 x i8> %vmull_p64.i to i128 # | store i128 %vmull_p641.i, ptr %ref.tmp.i, align 16 # | %4 = load i128, ptr %ref.tmp.i, align 16 # | store i128 %4, ptr %__ret.i, align 16 # | %5 = load i128, ptr %__ret.i, align 16 # | ret i128 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 { # | entry: # | %__p0.addr.i3 = alloca <2 x i64>, align 16 # | %__ret.i4 = alloca <1 x i64>, align 8 # | %__p0.addr.i1 = alloca <2 x i64>, align 16 # | %__ret.i2 = alloca <1 x i64>, align 8 # | %__p0.addr.i.i = alloca i64, align 8 # | %__p1.addr.i.i = alloca i64, align 8 # | %__ret.i.i = alloca i128, align 16 # | %ref.tmp.i.i = alloca i128, align 16 # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %ref.tmp.i = alloca <1 x i64>, align 8 # | %ref.tmp1.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %2, ptr %__p0.addr.i3, align 16 # | %3 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %4 = load <2 x i64>, ptr %__p0.addr.i3, align 16 # | %shuffle.i5 = shufflevector <2 x i64> %3, <2 x i64> %4, <1 x i32> # | store <1 x i64> %shuffle.i5, ptr %__ret.i4, align 8 # | %5 = load <1 x i64>, ptr %__ret.i4, align 8 # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load i64, ptr %ref.tmp.i, align 8 # | %7 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | store <2 x i64> %7, ptr %__p0.addr.i1, align 16 # | %8 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %9 = load <2 x i64>, ptr %__p0.addr.i1, align 16 # | %shuffle.i = shufflevector <2 x i64> %8, <2 x i64> %9, <1 x i32> # | store <1 x i64> %shuffle.i, ptr %__ret.i2, align 8 # | %10 = load <1 x i64>, ptr %__ret.i2, align 8 # | store <1 x i64> %10, ptr %ref.tmp1.i, align 8 # | %11 = load i64, ptr %ref.tmp1.i, align 8 # | store i64 %6, ptr %__p0.addr.i.i, align 8 # | store i64 %11, ptr %__p1.addr.i.i, align 8 # | %12 = load i64, ptr %__p0.addr.i.i, align 8 # | %13 = load i64, ptr %__p1.addr.i.i, align 8 # | %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %12, i64 %13) # | %vmull_p641.i.i = bitcast <16 x i8> %vmull_p64.i.i to i128 # | store i128 %vmull_p641.i.i, ptr %ref.tmp.i.i, align 16 # | %14 = load i128, ptr %ref.tmp.i.i, align 16 # | store i128 %14, ptr %__ret.i.i, align 16 # | %15 = load i128, ptr %__ret.i.i, align 16 # | store i128 %15, ptr %__ret.i, align 16 # | %16 = load i128, ptr %__ret.i, align 16 # | ret i128 %16 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca i128, align 16 # | %a.ad # | ... # `---data was truncated (10240/19795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055a5d75fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a5d75f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a5d75fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf22049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf220a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf22049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf22031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5d7591e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a5d7591c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a5d7576b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5d72260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a5d7225dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf22032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf220330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf220330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5d7225cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/poly128.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c (1088 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b48be5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b48be5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b48be5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf64533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf6458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf64533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf6451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b48bdf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b48bdf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b48bdd7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b48ba870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b48ba86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbf6451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf6451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf6451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b48ba86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c (1089 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv # | ... # `---data was truncated (10240/68225) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560e8f1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560e8f1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560e8f1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c2c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c2c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c2c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c2c803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560e8eb2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560e8eb2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560e8e97b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560e8b470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560e8b46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c2c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c2c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c2c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560e8b46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c (1090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vx_i16m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmul_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/153905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1f5d3015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1f5d2d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1f5d3089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97f1d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97f1d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97f1d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97f1d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1f5cc5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1f5cc5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1f5caab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1f595a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b1f5959dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97f1d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97f1d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97f1d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1f5959cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c (1091 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae39cac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae39ca90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae39cac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e14533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e1458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e14533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e1451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae39c41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae39c41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae39c26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae398d60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae398d5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e1451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e1451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e1451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae398d5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c (1092 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055795953915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005579595360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055795953989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bd6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bd6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bd6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bd6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579594cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579594cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579594b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579591630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557959162dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1bd6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bd6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bd6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557959162cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c (1093 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_s32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_s64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.adrd.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u32base_u32index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv4i32( %0, %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svadrd_u64base_u64index( %bases, %indices) #0 { # | entry: # | %bases.addr = alloca , align 16 # | %indices.addr = alloca , align 16 # | store %bases, ptr %bases.addr, align 16 # | store %indices, ptr %indices.addr, align 16 # | %0 = load , ptr %bases.addr, align 16 # | %1 = load , ptr %indices.addr, align 16 # | %2 = call @llvm.aarch64.sve.adrd.nxv2i64( %0, %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x0000556859a4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556859a4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556859a4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f70b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f70b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f70b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f70b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005568599e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005568599e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005568599c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005568596770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556859676dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f70b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f70b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f70b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556859676cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c (1094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/41659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055588da1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055588da150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055588da1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f399e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f399e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f399e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f399e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055588d9ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055588d9adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055588d992b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055588d6420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055588d641dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f399e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f399e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f399e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055588d641cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/distributed-thin-lto/backend-skip.ll (1095 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/backend-skip.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/backend-skip.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/backend-skip.ll # | #0 0x0000559973f0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559973f0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559973f0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2882649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2882649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2882631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559973ea3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559973ea3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559973e88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559973b380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559973b37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2882632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28826330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559973b37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c (1096 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602d24b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602d24b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602d24b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75ca733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75ca78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75ca733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75ca71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602d244ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602d244cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602d2431b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602d20e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005602d20e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f75ca71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75ca71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75ca71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602d20e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/add.c (1097 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vadd_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %add.i = add <8 x i8> %2, %3 # | store <8 x i8> %add.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vadd_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %add.i = add <4 x i16> %2, %3 # | store <4 x i16> %add.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vadd_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %add.i = add <2 x i32> %2, %3 # | store <2 x i32> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vadd_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %add.i = add <1 x i64> %2, %3 # | store <1 x i64> %add.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vaddq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %add.i = add <16 x i8> %2, %3 # | store <16 x i8> %add.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %add.i = add <8 x i16> %2, %3 # | store <8 x i16> %add.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vaddq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b # | ... # `---data was truncated (10240/221881) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055e9407a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9407a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9407a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40f441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40f44725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40f441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40f4403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e94073be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e94073bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e940720b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9403d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e9403cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f40f4404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40f44050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40f44050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9403cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/add.c --check-prefix=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c (1098 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df8aa5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df8aa520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df8aa5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78d9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78d958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78d9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78d951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df8a9eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df8a9eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df8a9cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df8a67f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df8a67edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f78d951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78d951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78d951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df8a67ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c (1099 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d563a3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d563a310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d563a3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f007b305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f007b35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f007b305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f007b2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5639c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5639c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5639aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d56365e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d56365ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f007b2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f007b2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f007b2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d56365dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c (1100 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svadda_f16( %pg, half noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca half, align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store half %initial, ptr %initial.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load half, ptr %initial.addr, align 2 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call half @llvm.aarch64.sve.fadda.nxv8f16( %3, half %1, %2) # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fadda.nxv8f16(, half, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svadda_f32( %pg, float noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca float, align 4 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store float %initial, ptr %initial.addr, align 4 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load float, ptr %initial.addr, align 4 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = call float @llvm.aarch64.sve.fadda.nxv4f32( %3, float %1, %2) # | ret float %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fadda.nxv4f32(, float, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svadda_f64( %pg, double noundef %initial, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %initial.addr = alloca double, align 8 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store double %initial, ptr %initial.addr, align 8 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load double, ptr %initial.addr, align 8 # | %2 = load , ptr %op.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call double @llvm.aarch64.sve.fadda.nxv2f64( %3, double %1, %2) # | ret double %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fadda.nxv2f64(, double, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055df38e7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df38e700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df38e7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff19cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff19cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff19cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff19cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df38e08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df38e08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df38dedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df38a9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df38a9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff19cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff19cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff19cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df38a9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c (1101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a769d8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a769d870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a769d8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c6b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c6b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c6b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c6b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a769d1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a769d1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a769d04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a7699b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a7699b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c6b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c6b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c6b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7699b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c (1102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574e9c3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574e9c2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574e9c3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4010a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4010aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4010a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4010a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574e9bc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005574e9bc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005574e9bacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574e985c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005574e985bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4010a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4010a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4010a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574e985bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c (1103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c (1104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a12ffd415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a12ffd10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a12ffd489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f253f905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f253f95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f253f905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f253f8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a12ff69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a12ff69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a12ff4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a12fbfe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a12fbfddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f253f8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f253f8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f253f8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a12fbfdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c (1105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/365423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8a002a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8a00270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8a002a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b7cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b7cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b7cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b7cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c89ffbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c89ffbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c89ffa4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c89fc540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c89fc53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b7cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b7cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b7cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c89fc53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c (1106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c (1107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c (1108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26d23615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c26d2330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c26d23689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ba5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ba52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ba5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ba5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c26d1cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c26d1cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c26d1b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c26ce600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c26ce5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ba5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ba52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ba52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26ce5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenCXX/attr-musttail.cpp (1109 of 27911) ******************** TEST 'Clang :: CodeGenCXX/attr-musttail.cpp' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fno-elide-constructors -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp -triple x86_64-unknown-linux-gnu -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-musttail.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %class.Foo = type { i8 } # | %class.HasTrivialDestructor = type { i8 } # | %struct.Data = type { ptr } # | %struct.HasNonTrivialCopyConstructor = type { i8 } # | %struct.HasNonTrivialCopyConstructor2 = type { i8 } # | %struct.LargeWithCopyConstructor = type { [32 x i8] } # | %class.anon = type { i8 } # | # | $_Z12TemplateFuncIiET_S0_ = comdat any # | # | $_Z6Func10IiEii = comdat any # | # | $_Z6Func12IiET_S0_ = comdat any # | # | @pmf = global { i64, i64 } zeroinitializer, align 8 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func1i(i32 noundef %x) #0 { # | entry: # | %retval = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %tobool = icmp ne i32 %0, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %entry # | %1 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %1) # | ret i32 %call # | # | 2: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | if.else: ; preds = %entry # | %3 = load i32, ptr %x.addr, align 4 # | %call1 = musttail call noundef i32 @_Z3Bazi(i32 noundef %3) # | ret i32 %call1 # | # | 4: ; No predecessors! # | store i32 undef, ptr %retval, align 4 # | br label %return # | # | return: ; preds = %4, %2 # | %5 = load i32, ptr %retval, align 4 # | ret i32 %5 # | } # | # | declare noundef i32 @_Z3Bari(i32 noundef) #1 # | # | declare noundef i32 @_Z3Bazi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func2i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z3Bari(i32 noundef %0) # | %call1 = musttail call noundef i32 @_Z3Bari(i32 noundef %call) # | ret i32 %call1 # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo8TailFromEi(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1) %this1, i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo14MemberFunctionEi(ptr noundef nonnull align 1 dereferenceable(1), i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func3i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func4i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.Foo, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_ZN3Foo12StaticMethodEi(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom2Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_ZN3Foo9TailFrom3Ei(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load { i64, i64 }, ptr @pmf, align 8 # | %memptr.adj = extractvalue { i64, i64 } %0, 1 # | %1 = getelementptr inbounds i8, ptr %this1, i64 %memptr.adj # | %memptr.ptr = extractvalue { i64, i64 } %0, 0 # | %2 = and i64 %memptr.ptr, 1 # | %memptr.isvirtual = icmp ne i64 %2, 0 # | br i1 %memptr.isvirtual, label %memptr.virtual, label %memptr.nonvirtual # | # | memptr.virtual: ; preds = %entry # | %vtable = load ptr, ptr %1, align 8 # | %3 = sub i64 %memptr.ptr, 1 # | %4 = getelementptr i8, ptr %vtable, i64 %3, !nosanitize !1 # | %memptr.virtualfn = load ptr, ptr %4, align 8, !nosanitize !1 # | br label %memptr.end # | # | memptr.nonvirtual: ; preds = %entry # | %memptr.nonvirtualfn = inttoptr i64 %memptr.ptr to ptr # | br label %memptr.end # | # | memptr.end: ; preds = %memptr.nonvirtual, %memptr.virtual # | %5 = phi ptr [ %memptr.virtualfn, %memptr.virtual ], [ %memptr.nonvirtualfn, %memptr.nonvirtual ] # | %6 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 %5(ptr noundef nonnull align 1 dereferenceable(1) %1, i32 noundef %6) # | ret i32 %call # | # | 7: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local void @_Z5Func5v() #0 { # | entry: # | musttail call void @_Z11ReturnsVoidv() # | ret void # | # | 0: ; No predecessors! # | ret void # | } # | # | declare void @_Z11ReturnsVoidv() #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func6i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | %foo = alloca %class.HasTrivialDestructor, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z10ReturnsInti(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | declare noundef i32 @_Z10ReturnsInti(i32 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func7P4Data(ptr noundef %data) #0 { # | entry: # | %data.addr = alloca ptr, align 8 # | store ptr %data, ptr %data.addr, align 8 # | %0 = load ptr, ptr %data.addr, align 8 # | %fptr = getelementptr inbounds nuw %struct.Data, ptr %0, i32 0, i32 0 # | %1 = load ptr, ptr %fptr, align 8 # | %2 = load ptr, ptr %data.addr, align 8 # | %call = musttail call noundef i32 %1(ptr noundef %2) # | ret i32 %call # | # | 3: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z5Func9i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z12TemplateFuncIiET_S0_(i32 noundef %0) #0 comdat { # | entry: # | %.addr = alloca i32, align 4 # | store i32 %0, ptr %.addr, align 4 # | ret i32 5 # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func11i(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z6Func10IiEii(i32 noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define linkonce_odr noundef i32 @_Z6Func10IiEii(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | %t = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = musttail call noundef i32 @_Z3Bari(i32 noundef %0) # | ret i32 %call # | # | 1: ; No predecessors! # | ret i32 undef # | } # | # | ; Function Attrs: mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6Func13i(i32 noundef %x) #0 { # | entry: # | %x.ad # | ... # `---data was truncated (10240/18685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=verify # | #0 0x000055f4c0c5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4c0c5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4c0c5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f644a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f644a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f644a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f644a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4c0bf3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f4c0bf3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f4c0bd8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4c08880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4c0887dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f644a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f644a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f644a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4c0887cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c (1110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/424835) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f55c08b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f55c0880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f55c08b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae01305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae0135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae01305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae012ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f55c020e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f55c020c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f55c005b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f55bcb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f55bcb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae012eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae012ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae012ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f55bcb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c (1111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c (1112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c (1113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c3d6ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c3d6ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c3d6ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f600d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f600d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f600d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f600d631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c3d643e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c3d643c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c3d628b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c3d2d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c3d2d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f600d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f600d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f600d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c3d2d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c (1114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgeu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056450412d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056450412a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056450412d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34c4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34c478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34c4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34c471b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645040c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645040c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645040a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564503d570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564503d56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f34c471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34c471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34c471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564503d56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c (1115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eda076415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eda07610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eda076489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f728e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f728e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f728e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f728e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eda06f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eda06f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eda06deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eda038e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eda038ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f728e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f728e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f728e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eda038dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c (1116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4652ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4652ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b4652ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31c6049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31c60a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31c6049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31c6031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b465284e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b465284c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b465269b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b464f190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b464f18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f31c6032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31c60330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31c60330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b464f18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c (1117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = l # | ... # `---data was truncated (10240/23247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557fa36f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557fa36ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557fa36f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea37f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea37f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea37f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea37f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fa3686e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557fa3686c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557fa366bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557fa331b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557fa331add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea37f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea37f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea37f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fa331acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c (1118 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vreinterpretq_f16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vreinterpretq_f32_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vreinterpretq_s16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vreinterpretq_s32_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align # | ... # `---data was truncated (10240/30281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055ab4cfdb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ab4cfd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ab4cfdb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64f1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64f198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64f1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64f191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab4cf70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ab4cf70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ab4cf55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ab4cc050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ab4cc04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64f191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64f191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64f191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab4cc04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --check-prefix=BOTH --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c (1119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fbbc44115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fbbc43e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fbbc44189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fd5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fd5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fd5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fd5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fbbc3d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fbbc3d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fbbc3bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fbbc06b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fbbc06add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5fd5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fd5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fd5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fbbc06acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c (1120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056147e7ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056147e7b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056147e7ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5a2049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5a20a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5a2049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5a2031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056147e74fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056147e74fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056147e734b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056147e3e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056147e3e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb5a2032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5a20330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5a20330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056147e3e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c (1121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vs # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa0479b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa047980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa0479b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1b2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1b2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1b2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1b2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa04730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa04730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa04715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa043c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa043c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1b2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1b2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1b2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa043c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c (1122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e992fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e992f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e992fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ea6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ea618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ea6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ea611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e99290e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e99290c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e99275b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e98f250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e98f24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7ea611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ea611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ea611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e98f24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c (1123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c (1124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c (1125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vtdiscard() #0 { # | entry: # | call void @llvm.riscv.sf.vtdiscard() # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtdiscard() #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6ee30815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6ee3050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6ee30889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaaaa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaaaa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaaaa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaaaa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6ee29de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6ee29dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6ee282b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6edf320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6edf31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faaaaa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaaaa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaaaa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6edf31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c (1126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055663ae8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055663ae8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055663ae8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d46533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d4658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d46533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d4651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055663ae23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055663ae23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055663ae08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055663aab80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055663aab7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d4651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d4651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d4651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055663aab7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c (1127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i32.i64.p0( poison, ptr %0, i64 %2) # | %4 = # | ... # `---data was truncated (10240/33471) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585d31ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585d31a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585d31ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb75c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb75ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb75c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb75c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585d3140e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585d3140c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585d3125b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585d2dd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585d2dd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb75c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb75c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb75c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585d2dd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c (1128 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_s64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u8( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_u64( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f16( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 0 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svget2_f32( %tuple.coerce0, %tuple.coerce1) #0 { # | entry: # | %tuple = alloca { , }, align 16 # | %tuple.addr = alloca { , }, align 16 # | %0 = insertvalue { , } poison, %tuple.coerce0, 0 # | %1 = insertvalue { , } %0, %tuple.coerce1, 1 # | store { , } %1, ptr %tuple, align 16 # | %tuple1 = load { , }, ptr %tuple, align 16 # | store { , } %tuple1, ptr %tuple.addr, align 16 # | %2 = load { , }, ptr %tuple.addr, align 16 # | %3 = extractvalue { , } %2, 1 # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | d # | ... # `---data was truncated (10240/14679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055667b49f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055667b49c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055667b49f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa757249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7572a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa757249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa757231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055667b434e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055667b434c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055667b419b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055667b0c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055667b0c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa757232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7572330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7572330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055667b0c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c (1129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c (1130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | s # | ... # `---data was truncated (10240/280209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055befb84515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055befb8420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055befb84589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1f9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1f94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1f9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1f9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055befb7dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055befb7dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055befb7bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055befb46f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055befb46edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1f9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1f94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1f94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055befb46ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c (1131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630972c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630972c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005630972c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52a9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52a9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52a9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52a9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563097259e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563097259c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056309723eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563096eee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563096eeddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f52a9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52a9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52a9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563096eedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c (1132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056017e2c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056017e2c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056017e2c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93a1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93a1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93a1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93a1aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056017e25ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056017e25cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056017e241b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056017def10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056017def0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93a1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93a1aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93a1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056017def0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c (1133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | # | ... # `---data was truncated (10240/222475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6d5e7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6d5e760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6d5e7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1644933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f164498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1644933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f164491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6d5e0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6d5e0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6d5df3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6d5aa30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6d5aa2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f164491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f164491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f164491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6d5aa2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c (1134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c (1135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 1 # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, a # | ... # `---data was truncated (10240/71115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6e176815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6e17650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6e176889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77d6533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77d658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77d6533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77d651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6e16fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c6e16fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c6e16e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6e13920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c6e1391dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f77d651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77d651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77d651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6e1391cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c (1136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c (1137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635fb71e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005635fb71b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005635fb71e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b72249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b722a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b72249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b72231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635fb6b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005635fb6b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005635fb698b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635fb3480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005635fb347dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b72232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b722330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b722330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635fb347cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c (1138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c (1139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c (1140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/205813) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557403ec715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557403ec40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557403ec789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe14ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe14ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe14ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe14ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557403e5ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557403e5cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557403e41b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557403af10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557403af0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe14ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe14ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe14ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557403af0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c (1141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b198ad715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b198ad40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b198ad789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e98049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e980a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e98049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e98031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b198a6ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b198a6cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b198a51b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1987010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b198700dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e98032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e980330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e980330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b198700cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c (1142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056178638b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005617863880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056178638b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0880705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f088075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0880705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08806ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561786320e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561786320c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561786305b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561785fb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561785fb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f08806eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08806ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08806ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561785fb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c (1143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c (1144 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620a2c5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620a2c4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005620a2c5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb0b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb0b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb0b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb0b803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620a2be7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620a2be7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005620a2bccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620a287c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005620a287bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb0b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb0b8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb0b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620a287bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c (1145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562fc527815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562fc52750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562fc527889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0de705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0de75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0de705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0de6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562fc520de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562fc520dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562fc51f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562fc4ea20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562fc4ea1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0de6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0de6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0de6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562fc4ea1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c (1146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c (1147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei8_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline noun # | ... # `---data was truncated (10240/121187) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055853f61615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055853f6130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055853f61689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbfe01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbfe0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbfe01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbfe003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055853f5abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055853f5abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055853f590b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055853f2400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055853f23fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbbfe004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbfe0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbfe0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055853f23fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c (1148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627304b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627304b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627304b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec0cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec0cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec0cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec0cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056273044ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056273044ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562730433b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627300e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627300e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec0cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec0cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec0cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627300e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c (1149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d6759615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d675930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d6759689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faaeb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faaeb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faaeb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faaeb231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d6752be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d6752bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d67510b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d671c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d671bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faaeb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faaeb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faaeb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d671bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (1150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesvsintload,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvsintload5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cd2da315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561cd2da00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561cd2da389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f479fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f479fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f479fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f479fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cd2d38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561cd2d38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561cd2d1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561cd29cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561cd29ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f479fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f479fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f479fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cd29cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c (1151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrem.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564263f4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564263f4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564263f4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c5cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c5cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c5cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c5cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564263ee3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564263ee3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564263ec8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564263b780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564263b77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0c5cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c5cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c5cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564263b77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c (1152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv # | ... # `---data was truncated (10240/165238) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d032f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d032f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d032f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3abe105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3abe15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3abe105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3abe0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d0328ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d0328ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d0326fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d02f1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d02f1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3abe0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3abe0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3abe0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d02f1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c (1153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df297ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df297ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df297ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4812b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4812b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4812b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4812b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df29782e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df29782c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df29767b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df294170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df29416dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4812b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4812b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4812b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df29416cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c (1154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c (1155 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svclamp_bf16( %op1, %op2, %op3) #0 { # | entry: # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | %op3.addr = alloca , align 16 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | store %op3, ptr %op3.addr, align 16 # | %0 = load , ptr %op1.addr, align 16 # | %1 = load , ptr %op2.addr, align 16 # | %2 = load , ptr %op3.addr, align 16 # | %3 = call @llvm.aarch64.sve.fclamp.nxv8bf16( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fclamp.nxv8bf16(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve,+sve-b16b16,+sve2,+sve2p1" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x000055703854715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570385440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055703854789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12be733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12be78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12be733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12be71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570384dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570384dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570384c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570381710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557038170dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f12be71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12be71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12be71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557038170cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c (1156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabd.nxv16i8 # | ... # `---data was truncated (10240/215036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f30810315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3081000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f30810389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77c1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77c1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77c1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77c1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f308098e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f308098c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f30807db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f307d2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f307d2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f77c1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77c1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77c1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f307d2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c (1157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, # | ... # `---data was truncated (10240/30874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612c305415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612c30510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005612c305489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43a3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43a36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43a3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43a3631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612c2fe9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005612c2fe9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005612c2fceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005612c2c7e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005612c2c7ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f43a3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43a36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43a36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612c2c7dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vaddv.c (1158 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vaddv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v8i16(<8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 0) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u8(i32 noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u16(i32 noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v8i16(<8 x i16> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = call i32 @llvm.arm.mve.addv.v4i32(<4 x i32> %0, i32 1) # | %2 = load i32, ptr %a.addr, align 4 # | %3 = add i32 %1, %2 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 0, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8> %0, i32 1, <16 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvq_p_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vaddvaq_p_s8(i32 noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = # | ... # `---data was truncated (10240/19190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056248f1c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056248f1c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056248f1c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed1e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed1e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed1e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed1e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056248f159e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056248f159c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056248f13eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056248edee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056248ededdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed1e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed1e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed1e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056248ededcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vaddv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c (1159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561339f8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561339f870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561339f8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbf5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbf58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbf5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbf5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561339f1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561339f1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561339f04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561339bb40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561339bb3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbf5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbf58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbf58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561339bb3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c (1160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645c780615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645c78030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645c780689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9662705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f966275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9662705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96626ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645c779be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645c779bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645c7780b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645c74300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645c742fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f96626eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96626ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96626ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645c742fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c (1161 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2_tu( %maskedoff, ptr noundef % # | ... # `---data was truncated (10240/280171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560b70eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560b70e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560b70eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe9f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe9f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe9f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe9f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560b7080e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560b7080c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560b7065b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560b6d150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560b6d14dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe9f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe9f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe9f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560b6d14cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c (1162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a6b10015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a6b0fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a6b10089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a2f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a2f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a2f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a2f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a6b095e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a6b095c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a6b07ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a6ad2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a6ad29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a2f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a2f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a2f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a6ad29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-vls-arith-ops.c (1163 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.v64i8(, <64 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i16.v32i16(, <32 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i32.v16i32(, <16 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i64.v8i64(, <8 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <64 x i8>, align 16 # | %a.addr = alloca <64 x i8>, align 16 # | %b.addr = alloca <64 x i8>, align 16 # | %a = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %a.coerce, i64 0) # | %b = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8( %b.coerce, i64 0) # | store <64 x i8> %a, ptr %a.addr, align 16 # | store <64 x i8> %b, ptr %b.addr, align 16 # | %0 = load <64 x i8>, ptr %a.addr, align 16 # | %1 = load <64 x i8>, ptr %b.addr, align 16 # | %add = add <64 x i8> %0, %1 # | store <64 x i8> %add, ptr %retval, align 16 # | %2 = load <64 x i8>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv16i8.v64i8( poison, <64 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i16>, align 16 # | %a.addr = alloca <32 x i16>, align 16 # | %b.addr = alloca <32 x i16>, align 16 # | %a = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %a.coerce, i64 0) # | %b = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16( %b.coerce, i64 0) # | store <32 x i16> %a, ptr %a.addr, align 16 # | store <32 x i16> %b, ptr %b.addr, align 16 # | %0 = load <32 x i16>, ptr %a.addr, align 16 # | %1 = load <32 x i16>, ptr %b.addr, align 16 # | %add = add <32 x i16> %0, %1 # | store <32 x i16> %add, ptr %retval, align 16 # | %2 = load <32 x i16>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv8i16.v32i16( poison, <32 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i32>, align 16 # | %a.addr = alloca <16 x i32>, align 16 # | %b.addr = alloca <16 x i32>, align 16 # | %a = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %a.coerce, i64 0) # | %b = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32( %b.coerce, i64 0) # | store <16 x i32> %a, ptr %a.addr, align 16 # | store <16 x i32> %b, ptr %b.addr, align 16 # | %0 = load <16 x i32>, ptr %a.addr, align 16 # | %1 = load <16 x i32>, ptr %b.addr, align 16 # | %add = add <16 x i32> %0, %1 # | store <16 x i32> %add, ptr %retval, align 16 # | %2 = load <16 x i32>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv4i32.v16i32( poison, <16 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i64>, align 16 # | %a.addr = alloca <8 x i64>, align 16 # | %b.addr = alloca <8 x i64>, align 16 # | %a = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %a.coerce, i64 0) # | %b = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64( %b.coerce, i64 0) # | store <8 x i64> %a, ptr %a.addr, align 16 # | store <8 x i64> %b, ptr %b.addr, align 16 # | %0 = load <8 x i64>, ptr %a.addr, align 16 # | %1 = load <8 x i64>, ptr %b.addr, align 16 # | %add = add <8 x i64> %0, %1 # | store <8 x i64> %add, ptr %retval, align 16 # | %2 = load <8 x i64>, ptr %retval, align 16 # | %cast.scalable = call @llvm.vector.insert.nxv2i64.v8i64( poison, <8 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x half>, align 16 # | %a.addr = alloca <32 x half>, align 16 # | %b.addr = alloca <32 x half>, align 16 # | %a = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %a.coerce, i64 0) # | %b = call <32 x half> @llvm.vector.extract.v32f16.nxv8f16( %b.coerce, i64 0) # | store <32 x half> %a, ptr %a.addr, align 16 # | store <32 x half> %b, ptr %b.addr, align 16 # | %0 = load <32 x ha # | ... # `---data was truncated (10240/161192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000555daa63f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555daa63c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555daa63f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14a2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14a2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14a2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14a2eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555daa5d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555daa5d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555daa5b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555daa2690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555daa268dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14a2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14a2eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14a2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555daa268cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c (1164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/95437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af2dc7d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055af2dc7a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055af2dc7d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f819cc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f819cc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f819cc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f819cc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af2dc12e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055af2dc12c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055af2dbf7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af2d8a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af2d8a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f819cc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f819cc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f819cc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af2d8a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c (1165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594a99f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594a99f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594a99f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2beba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bebaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2beba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2beba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594a998de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594a998dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594a9972b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594a96220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594a9621dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2beba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2beba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2beba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594a9621cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c (1166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nx # | ... # `---data was truncated (10240/78682) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3181d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3181d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f3181d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a14c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a14ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a14c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a14c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f318169e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f318169c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f31814eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f317dfe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f317dfddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2a14c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a14c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a14c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f317dfdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c (1167 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d3ef4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d3ef4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d3ef4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce8681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce868725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce8681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce86803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d3eee4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d3eee4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d3eec9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d3eb790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d3eb78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce86804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce868050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce868050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d3eb78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c (1168 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i8 @test_vsqaddb_u8() #0 { # | entry: # | %__p0.addr.i = alloca i8, align 1 # | %__p1.addr.i = alloca i8, align 1 # | %__ret.i = alloca i8, align 1 # | %ref.tmp.i = alloca i8, align 1 # | store i8 1, ptr %__p0.addr.i, align 1 # | store i8 -1, ptr %__p1.addr.i, align 1 # | %0 = load i8, ptr %__p0.addr.i, align 1 # | %1 = load i8, ptr %__p1.addr.i, align 1 # | %2 = insertelement <8 x i8> poison, i8 %0, i64 0 # | %3 = insertelement <8 x i8> poison, i8 %1, i64 0 # | %vsqaddb_u8.i = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %2, <8 x i8> %3) # | %4 = extractelement <8 x i8> %vsqaddb_u8.i, i64 0 # | store i8 %4, ptr %ref.tmp.i, align 1 # | %5 = load i8, ptr %ref.tmp.i, align 1 # | store i8 %5, ptr %__ret.i, align 1 # | %6 = load i8, ptr %__ret.i, align 1 # | ret i8 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vsqaddh_u16() #0 { # | entry: # | %__p0.addr.i = alloca i16, align 2 # | %__p1.addr.i = alloca i16, align 2 # | %__ret.i = alloca i16, align 2 # | %ref.tmp.i = alloca i16, align 2 # | store i16 1, ptr %__p0.addr.i, align 2 # | store i16 -1, ptr %__p1.addr.i, align 2 # | %0 = load i16, ptr %__p0.addr.i, align 2 # | %1 = load i16, ptr %__p1.addr.i, align 2 # | %2 = insertelement <4 x i16> poison, i16 %0, i64 0 # | %3 = insertelement <4 x i16> poison, i16 %1, i64 0 # | %vsqaddh_u16.i = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %2, <4 x i16> %3) # | %4 = extractelement <4 x i16> %vsqaddh_u16.i, i64 0 # | store i16 %4, ptr %ref.tmp.i, align 2 # | %5 = load i16, ptr %ref.tmp.i, align 2 # | store i16 %5, ptr %__ret.i, align 2 # | %6 = load i16, ptr %__ret.i, align 2 # | ret i16 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vsqadds_u32() #0 { # | entry: # | %__p0.addr.i = alloca i32, align 4 # | %__p1.addr.i = alloca i32, align 4 # | %__ret.i = alloca i32, align 4 # | %ref.tmp.i = alloca i32, align 4 # | store i32 1, ptr %__p0.addr.i, align 4 # | store i32 -1, ptr %__p1.addr.i, align 4 # | %0 = load i32, ptr %__p0.addr.i, align 4 # | %1 = load i32, ptr %__p1.addr.i, align 4 # | %vsqadds_u32.i = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %0, i32 %1) # | store i32 %vsqadds_u32.i, ptr %ref.tmp.i, align 4 # | %2 = load i32, ptr %ref.tmp.i, align 4 # | store i32 %2, ptr %__ret.i, align 4 # | %3 = load i32, ptr %__ret.i, align 4 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vsqaddd_u64() #0 { # | entry: # | %__p0.addr.i = alloca i64, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca i64, align 8 # | %ref.tmp.i = alloca i64, align 8 # | store i64 1, ptr %__p0.addr.i, align 8 # | store i64 -1, ptr %__p1.addr.i, align 8 # | %0 = load i64, ptr %__p0.addr.i, align 8 # | %1 = load i64, ptr %__p1.addr.i, align 8 # | %vsqaddd_u64.i = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %0, i64 %1) # | store i64 %vsqaddd_u64.i, ptr %ref.tmp.i, align 8 # | %2 = load i64, ptr %ref.tmp.i, align 8 # | store i64 %2, ptr %__ret.i, align 8 # | %3 = load i64, ptr %__ret.i, align 8 # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,dce # | #0 0x000055902163315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590216300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055902163389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6f0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6f00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6f0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6f0031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590215c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590215c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590215adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055902125d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055902125cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6f0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6f00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6f00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055902125ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vsqadd-float-conversion.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c (1169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f0991d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f0991a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f0991d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb52e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb52e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb52e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb52e431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f098b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f098b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f09897b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f095470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f09546dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb52e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb52e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb52e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f09546cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c (1170 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not=' @llvm.fma.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=maytrap -DEXCEPT=1 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> # | %fmla = bitcast <16 x i8> %4 to <8 x half> # | %fmla1 = bitcast <16 x i8> %3 to <8 x half> # | %fmla2 = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %fmla, <8 x half> %lane, <8 x half> %fmla1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <8 x half> %fmla2, ptr %ref.tmp, align 16 # | %7 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %7, ptr %__ret, align 16 # | %8 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %8, ptr %tmp, align 16 # | %9 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <4 x half> @test_vfma_laneq_f16(<4 x half> noundef %a, <4 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %8, <8 x half> %8, <4 x i32> # | %9 = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %lane, <4 x half> %7, <4 x half> %6, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store <4 x half> %9, ptr %ref.tmp, align 8 # | %10 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %10, ptr %__ret, align 8 # | %11 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %11, ptr %tmp, align 8 # | %12 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %12 # | } # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local <8 x half> @test_vfmaq_laneq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 # | ... # `---data was truncated (10240/13273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055f8b67cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8b67cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f8b67cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f403cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f403cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f403cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f403cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8b6764e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f8b6764c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f8b6749b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f8b63f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f8b63f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f403cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f403cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f403cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8b63f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap '--implicit-check-not= @llvm.fma.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=fpexcept.maytrap --implicit-check-not= @llvm.fma. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c (1171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmax.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c (1172 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a6b88b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a6b8880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a6b88b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d4ce1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d4ce725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d4ce1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d4ce03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a6b820e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a6b820c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a6b805b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a6b4b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a6b4b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7d4ce04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d4ce050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d4ce050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a6b4b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c (1173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = # | ... # `---data was truncated (10240/39218) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056065e93a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056065e9370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056065e93a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed5ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed5ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed5ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed5feed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056065e8cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056065e8cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056065e8b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056065e5640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056065e563dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed5feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed5feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed5feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056065e563cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c (1174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c (1175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645adeb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645adeaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645adeb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb54101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5410725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb54101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb541003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645ade47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645ade47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645ade2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645adadc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645adadbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb541004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5410050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5410050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645adadbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c (1176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvw_se_u16m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void # | ... # `---data was truncated (10240/179328) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb1faf315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb1faf00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb1faf389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efefdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efefdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efefdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efefdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb1fa88e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb1fa88c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb1fa6db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb1f71d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb1f71cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efefdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efefdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efefdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb1f71ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c (1177 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <4 x half> # | %7 = bitcast <8 x i8> %4 to <4 x half> # | %8 = bitcast <8 x i8> %5 to <4 x half> # | %9 = call <4 x half> @llvm.fma.v4f16(<4 x half> %7, <4 x half> %8, <4 x half> %6) # | store <4 x half> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %10, ptr %__ret.i, align 8 # | %11 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %6 = bitcast <16 x i8> %3 to <8 x half> # | %7 = bitcast <16 x i8> %4 to <8 x half> # | %8 = bitcast <16 x i8> %5 to <8 x half> # | %9 = call <8 x half> @llvm.fma.v8f16(<8 x half> %7, <8 x half> %8, <8 x half> %6) # | store <8 x half> %9, ptr %ref.tmp.i, align 16 # | %10 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %10, ptr %__ret.i, align 16 # | %11 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x half>, align 8 # | %__p1.addr.i.i = alloca <4 x half>, align 8 # | %__p2.addr.i.i = alloca <4 x half>, align 8 # | %__ret.i.i = alloca <4 x half>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i.i, align 8 # | store <4 x half> %5, ptr %__p2.addr.i.i, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i.i, align 8 # | store <4 x half> %13, ptr %__ret.i.i, align 8 # | %14 = load <4 x half>, ptr %__ret.i.i, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i.i = alloca <8 x half>, align 16 # | %__p1.addr.i.i = alloca <8 x half>, align 16 # | %__p2.addr.i.i = alloca <8 x half>, align 16 # | %__ret.i.i = alloca <8 x half>, align 16 # | %ref.tmp.i.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i.i, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i.i, align 16 # | store <8 x half> %5, ptr %__p2.addr.i.i, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i.i, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i.i, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i.i, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i.i, align 16 # | store <8 x half> %13, ptr %__ret.i.i, align 16 # | %14 = load <8 x half>, ptr %__ret.i.i, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_lane_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> # | %fmla = bitcast <8 x i8> %4 to <4 x half> # | %fmla1 = bitcast <8 x i8> %3 to <4 x half> # | %fmla2 = call <4 x half> @llvm.fma.v4f16(<4 x half> %fmla, <4 x half> %lane, <4 x half> %fmla1) # | store <4 x half> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %7, ptr %__ret, align 8 # | %8 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %8, ptr %tmp, align 8 # | %9 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_lane_f16(<8 x half> noundef %a, <8 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1 # | ... # `---data was truncated (10240/42739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bd843a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bd8439d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bd843a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f93733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f9378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f93733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f9371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd84335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bd84335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bd8431ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bd83fca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bd83fc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f9371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f9371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f9371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd83fc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fused-multiple-fullfp16.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c (1178 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c (1179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563197e8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563197e830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563197e8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e4cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e4cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e4cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e4cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563197e1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563197e1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563197e00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563197ab00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563197aafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e4cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e4cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e4cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563197aafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c (1180 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c (1181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2 # | ... # `---data was truncated (10240/94673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b789a4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b789a430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b789a4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0fb521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0fb52725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0fb521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0fb5203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7899dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b7899dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b7899c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7896700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b78966fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0fb5204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0fb52050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0fb52050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b78966fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c (1182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c (1183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cac51b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563cac5180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563cac51b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dae81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dae8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dae81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dae803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cac4b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563cac4b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563cac495b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563cac1450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563cac144dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dae804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dae8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dae8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cac144cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c (1184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrem.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrem.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrem_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559420ed215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559420ecf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559420ed289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53c211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559420e67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559420e67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559420e4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559420afc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559420afbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f53c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53c211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559420afbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c (1185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei16_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056321d1e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056321d1e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056321d1e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e18d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e18d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e18d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e18d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056321d17ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056321d17ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056321d15fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056321ce0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056321ce0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e18d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e18d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e18d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056321ce0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c (1186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd3b72d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd3b72a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd3b72d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e97249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e972a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e97249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e97231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd3b6c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd3b6c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd3b6a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd3b3570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd3b356dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8e97232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e972330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e972330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd3b356cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c (1187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcpopv.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_ran # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c91e20c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c91e2090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c91e20c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd460e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd460e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd460e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd460e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c91e1a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c91e1a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c91e186b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c91de360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c91de35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd460e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd460e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd460e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c91de35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c (1188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e74c34115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e74c33e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e74c34189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ea1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ea198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ea1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ea191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e74c2d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e74c2d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e74c2bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e74bf6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e74bf6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ea191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ea191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ea191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e74bf6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c (1189 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vadd_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %add.i = fadd <2 x float> %2, %3 # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vaddq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %add.i = fadd <4 x float> %2, %3 # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vsub_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %sub.i = fsub <2 x float> %2, %3 # | store <2 x float> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vsubq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <4 x float> %2, %3 # | store <4 x float> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vsubq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %sub.i = fsub <2 x double> %2, %3 # | store <2 x double> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmul_f32(<2 x float> noundef %v1, <2 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %mul.i = fmul <2 x float> %2, %3 # | store <2 x float> %mul.i, ptr %__ret.i, align 8 # | %4 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmulq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <4 x float> %2, %3 # | store <4 x float> %mul.i, ptr %__ret.i, align 16 # | %4 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vmulq_f64(<2 x double> noundef %v1, <2 x double> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__p1.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v1.addr = alloca <2 x double>, align 16 # | %v2.addr = alloca <2 x double>, align 16 # | store <2 x double> %v1, ptr %v1.addr, align 16 # | store <2 x double> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x double>, ptr %v1.addr, align 16 # | %1 = load <2 x double>, ptr %v2.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x double>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x double>, ptr %__p1.addr.i, align 16 # | %mul.i = fmul <2 x double> %2, %3 # | store <2 x double> %mul.i, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmla_f32(<2 x float> noundef %v1, <2 x float> noundef %v2, <2 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %v1.addr = alloca <2 x float>, align 8 # | %v2.addr = alloca <2 x float>, align 8 # | %v3.addr = alloca <2 x float>, align 8 # | store <2 x float> %v1, ptr %v1.addr, align 8 # | store <2 x float> %v2, ptr %v2.addr, align 8 # | store <2 x float> %v3, ptr %v3.addr, align 8 # | %0 = load <2 x float>, ptr %v1.addr, align 8 # | %1 = load <2 x float>, ptr %v2.addr, align 8 # | %2 = load <2 x float>, ptr %v3.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load <2 x float>, ptr %__p2.addr.i, align 8 # | %mul.i = fmul <2 x float> %4, %5 # | %add.i = fadd <2 x float> %3, %mul.i # | store <2 x float> %add.i, ptr %__ret.i, align 8 # | %6 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmlaq_f32(<4 x float> noundef %v1, <4 x float> noundef %v2, <4 x float> noundef %v3) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <4 x float>, align 16 # | %__p2.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v1.addr = alloca <4 x float>, align 16 # | %v2.addr = alloca <4 x float>, align 16 # | %v3.addr = alloca <4 x float>, align 16 # | store <4 x float> %v1, ptr %v1.addr, align 16 # | store <4 x float> %v2, ptr %v2.addr, align 16 # | store <4 x float> %v3, ptr %v3.addr, align 16 # | %0 = load <4 x float>, ptr %v1.addr, align 16 # | %1 = load <4 x float>, ptr %v2.addr, align 16 # | %2 = load <4 x float>, ptr %v3.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__p1.addr.i, align 16 # | store <4 x float> %2, ptr %__p2.addr.i, align 16 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 16 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 16 # | %5 = load <4 x float>, ptr %__p2.addr.i, align 16 # | %mul.i = fmul <4 x float> %4, %5 # | %add.i = fadd <4 x float> %3, %mul.i # | store <4 x float> %add.i, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; F # | ... # `---data was truncated (10240/91378) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055cca00d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cca00d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cca00d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feda5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feda578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feda5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feda571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cca006de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cca006dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cca0052b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc9fd020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc9fd01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feda571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feda571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feda571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc9fd01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c (1190 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8b702715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8b70240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8b702789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc03733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc0378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc03733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc0371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8b6fbce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8b6fbcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8b6fa1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8b6c510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8b6c50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc0371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc0371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc0371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8b6c50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c (1191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e44e1f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555e44e1c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555e44e1f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8875c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8875ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8875c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8875c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e44db4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555e44db4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555e44d99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555e44a490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555e44a48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8875c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8875c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8875c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e44a48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c (1192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055770acc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055770acbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055770acc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c38d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c38d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c38d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c38d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055770ac55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055770ac55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055770ac3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055770a8ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055770a8e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c38d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c38d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c38d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055770a8e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c (1193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, pt # | ... # `---data was truncated (10240/71947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c16eaeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c16eae80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c16eaeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cd1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cd175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cd1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cd16ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c16ea80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c16ea80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c16ea65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c16e7150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c16e714dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6cd16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cd16ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cd16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c16e714cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c (1194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c (1195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_l # | ... # `---data was truncated (10240/13585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ac1f4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ac1f4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ac1f4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9171733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f917178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9171733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f917171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ac1ee4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ac1ee4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ac1ec9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ac1b790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ac1b78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f917171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f917171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f917171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ac1b78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c (1196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnmsac.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnmsac.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnmsac_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c (1197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056028fecf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056028fecc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056028fecf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23ea505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23ea55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23ea505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23ea4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056028fe64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056028fe64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056028fe49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056028faf90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056028faf8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23ea4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23ea4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23ea4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056028faf8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (1198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.ad # | ... # `---data was truncated (10240/26762) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7ebabf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7ebabc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7ebabf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f227cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f227cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f227cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f227cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7eba54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7eba54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7eba39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7eb6e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7eb6e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f227cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f227cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f227cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7eb6e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c (1199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m # | ... # `---data was truncated (10240/134565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f19b40115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f19b3fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f19b40189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fa4049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fa40a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fa4049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fa4031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f19b396e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f19b396c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f19b37bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f19b02b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f19b02add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fa4032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fa40330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fa40330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f19b02acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c (1200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055727182015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055727181d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055727182089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe265705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe26575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe265705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2656ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572717b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005572717b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055727179ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055727144a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557271449dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe2656eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2656ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2656ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557271449cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c (1201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u8m8( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf4( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16mf2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m1( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 immarg, i32 immarg, , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vv_se_u16m2( %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, %0, %1, i32 %2) # | ret void # | } # | # | ; Function # | ... # `---data was truncated (10240/200802) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561f407e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561f407b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561f407e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23d2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23d28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23d2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23d2831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561f4013e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561f4013c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561f3ff8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561f3ca80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561f3ca7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23d2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23d28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23d28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561f3ca7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c (1202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m4( %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrga # | ... # `---data was truncated (10240/28435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c06d1b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c06d1ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c06d1b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02f9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02f96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02f9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02f9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c06d146e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c06d146c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c06d12bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c06cddb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c06cddadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02f9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02f96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02f96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c06cddacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c (1203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056372d35a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056372d3570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056372d35a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f84133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f8418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f84133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f8411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056372d2efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056372d2efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056372d2d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056372cf840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056372cf83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f8411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f8411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f8411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056372cf83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c (1204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/108848) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d50f95b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d50f9580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d50f95b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe62d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe62d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe62d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe62d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d50f8f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d50f8f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d50f8d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d50f5850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d50f584dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe62d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe62d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe62d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d50f584cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c (1205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down. # | ... # `---data was truncated (10240/14900) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f6b6fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f6b6fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f6b6fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8706733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f870678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8706733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f870671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6b692e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f6b692c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f6b677b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f6b3270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f6b326dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f870671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f870671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f870671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f6b326cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c (1206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv32i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv64i8.i8.i64( %0, %1, i8 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i16.i16.i64( %0, %1, i16 -1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i6 # | ... # `---data was truncated (10240/182165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ad21a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ad21a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ad21a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f47105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f4715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f47105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f470ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ad213ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ad213ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ad2123b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ad1dd30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ad1dd2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f470eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f470ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f470ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ad1dd2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c (1207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = e # | ... # `---data was truncated (10240/100513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a22f40115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a22f3fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a22f40189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51ffc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51ffc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51ffc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51ffc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22f396e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a22f396c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a22f37bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a22f02b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a22f02add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f51ffc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51ffc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51ffc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a22f02acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c (1208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588fff4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588fff400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588fff4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f283f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f283f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f283f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f283f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588ffed8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588ffed8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588ffebdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588ffb6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588ffb6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f283f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f283f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f283f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588ffb6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c (1209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4( %vd, %v # | ... # `---data was truncated (10240/148843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056429c56615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056429c5630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056429c56689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe51c649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe51c6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe51c649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe51c631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056429c4fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056429c4fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056429c4e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056429c1900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056429c18fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe51c632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe51c6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe51c6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056429c18fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c (1210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd8428715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd842840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd8428789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b6bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b6bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b6bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b6bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd8421ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd8421cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd84201b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd83eb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd83eb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1b6bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b6bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b6bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd83eb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c (1211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561ce1d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561ce1cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561ce1d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d0d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d0d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d0d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d0d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561ce165e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561ce165c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561ce14ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561cddfa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561cddf9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4d0d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d0d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d0d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561cddf9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c (1212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c (1213 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562258ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005562258fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005562258ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42c2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42c278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42c2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42c271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556225894e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556225894c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556225879b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005562255290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556225528dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42c271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42c271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42c271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556225528cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c (1214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056153946a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615394670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056153946a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9fbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615393ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615393ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615393e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615390940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561539093dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9fbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561539093cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c (1215 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f1cea515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f1cea20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f1cea589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bfd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bfd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bfd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bfd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f1ce3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f1ce3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f1ce1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f1cacf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f1cacedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bfd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bfd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bfd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f1cacecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c (1216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b81f7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b81f710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b81f7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f216cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f216cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f216cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b81f09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b81f09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b81eeeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b81b9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b81b9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f216cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f216cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f216cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b81b9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c (1217 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c (1218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/61929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565549ceb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565549ce80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565549ceb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3f6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565549c80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565549c80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565549c65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005655499150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565549914dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc3f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565549914cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c (1219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c (1220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597811e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597811de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597811e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc22449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc224a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc22449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc22431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559781176e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559781176c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055978115bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559780e0b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559780e0add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc22432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc224330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc224330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559780e0acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c (1221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32bf16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %v # | ... # `---data was truncated (10240/11349) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b60ece615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b60ece30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b60ece689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1d0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1d0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1d0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1d0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b60ec7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b60ec7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b60ec60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b60e9100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b60e90fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1d0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1d0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1d0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b60e90fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c (1222 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641f218915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641f21860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641f218989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa78b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa78b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa78b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa78b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641f211ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005641f211ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005641f2103b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641f1db30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641f1db2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa78b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa78b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa78b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641f1db2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c (1223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f1702115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563f1701e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563f1702189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc71b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc71b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc71b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc71b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f16fb6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563f16fb6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563f16f9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563f16c4b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563f16c4add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc71b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc71b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc71b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f16c4acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c (1224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562efb9e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562efb9e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562efb9e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c9c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c9c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c9c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c9c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562efb97ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562efb97ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562efb95fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562efb60f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562efb60edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c9c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c9c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c9c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562efb60ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c (1225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c (1226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, pt # | ... # `---data was truncated (10240/174721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee4a77c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee4a7790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee4a77c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2275a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2275aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2275a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2275a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee4a711e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee4a711c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee4a6f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee4a3a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee4a3a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2275a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2275a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2275a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee4a3a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c (1227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e60f04915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e60f0460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e60f04989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8de9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8de978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8de9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8de971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e60efdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e60efdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e60efc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e60ec730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e60ec72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8de971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8de971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8de971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e60ec72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c (1228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu # | ... # `---data was truncated (10240/156765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fab5f3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fab5f390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fab5f3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe57f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe57f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe57f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe57f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fab5ed1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fab5ed1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fab5eb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fab5b660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fab5b65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe57f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe57f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe57f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fab5b65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c (1229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bac88cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bac88c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bac88cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f586b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f586b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f586b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f586b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bac8861e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bac8861c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bac8846b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bac84f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bac84f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f586b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f586b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f586b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bac84f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c (1230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556b9dd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005556b9dd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005556b9dd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8638b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8638b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8638b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8638b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556b9d6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005556b9d6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005556b9d53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005556b9a030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005556b9a02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8638b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8638b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8638b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556b9a02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c (1231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( % # | ... # `---data was truncated (10240/149145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf7f9b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bf7f9b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bf7f9b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4a9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4a94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4a9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4a9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf7f94ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bf7f94ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bf7f933b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bf7f5e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bf7f5e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4a9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4a94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4a94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf7f5e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c (1232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2_tu # | ... # `---data was truncated (10240/288275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d4c2b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d4c2af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d4c2b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3cb533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3cb58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3cb533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3cb51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d4c247e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d4c247c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d4c22cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d4bedc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d4bedbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb3cb51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3cb51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3cb51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d4bedbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c (1233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, alig # | ... # `---data was truncated (10240/150641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575d155415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575d15510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575d155489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe598705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe59875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe598705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5986ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575d14e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575d14e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575d14ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575d117e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575d117ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe5986eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5986ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5986ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575d117dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c (1234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/126436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555564ce315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555564ce00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555564ce389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f54d5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54d5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f54d5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54d5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555564c78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555564c78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555564c5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055556490d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055556490cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f54d5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54d5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54d5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055556490ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c (1235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16 # | ... # `---data was truncated (10240/33616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bef4ac315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bef4ac00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bef4ac389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42aa449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42aa4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42aa449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42aa431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bef4a58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bef4a58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bef4a3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bef46ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bef46ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42aa432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42aa4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42aa4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bef46eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c (1236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570f4d6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570f4d5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570f4d6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cf0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cf0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cf0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cf0eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570f4cf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570f4cf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570f4cdcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570f498c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570f498bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3cf0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cf0eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cf0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570f498bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c (1237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call < # | ... # `---data was truncated (10240/66998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e2012815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559e201250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559e2012889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f08049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f08049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f08031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e200bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559e200bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559e200a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559e1fd520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559e1fd51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6f08032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f080330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e1fd51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c (1238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmax.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmax.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmax_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056235591615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005623559130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056235591689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc52b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc52b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc52b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc52b431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623558abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005623558abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562355890b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005623555400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056235553fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc52b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc52b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc52b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056235553fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c (1239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd7b58f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd7b58c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd7b58f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1106849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11068a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1106849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1106831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd7b524e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd7b524c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd7b509b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd7b1b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd7b1b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1106832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11068330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11068330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd7b1b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c (1240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c (1241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c (1242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/134736) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fd3d6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556fd3d680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556fd3d6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f353c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f353c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f353c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f353c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fd3d00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556fd3d00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556fd3ce5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556fd39950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556fd3994dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f353c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f353c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f353c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fd3994cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c (1243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | # | ... # `---data was truncated (10240/26460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b4fa8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b4fa8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b4fa8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc108533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc10858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc108533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc10851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b4fa24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b4fa24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b4fa09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b4f6b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b4f6b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc10851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc10851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc10851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b4f6b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c (1244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c (1245 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615d871815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615d87150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005615d871889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe038e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe038e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe038e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe038e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615d86ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615d86adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615d8692b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615d83420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615d8341dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe038e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe038e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe038e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615d8341cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c (1246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca # | ... # `---data was truncated (10240/98343) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c0082315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558c008200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558c0082389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8f1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8f198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8f1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8f191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c007b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558c007b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558c0079db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558c0044d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558c0044cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8f191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8f191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8f191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c0044ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c (1247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056389105f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056389105c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056389105f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb149705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb14975c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb149705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1496ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563890ff4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563890ff4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563890fd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563890c890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563890c88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1496eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1496ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1496ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563890c88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c (1248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611ec1d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005611ec1d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005611ec1d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6770849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6770849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6770831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611ec16ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005611ec16cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005611ec151b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005611ebe010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005611ebe00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6770832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67708330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611ebe00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c (1249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c (1250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8a2be015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8a2bdd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8a2be089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdbd849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdbd8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdbd849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdbd831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8a2b75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8a2b75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8a2b5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8a280a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8a2809dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbdbd832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdbd8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdbd8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8a2809cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c (1251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vctz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c (1252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef966fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef966f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef966fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5c7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5c72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5c7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5c7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef9668fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef9668fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef96674b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef963240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef96323dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff5c7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5c72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5c72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef96323cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c (1253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | % # | ... # `---data was truncated (10240/201226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616fe6b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005616fe6b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005616fe6b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42dda31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005616fe64be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005616fe64bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005616fe630b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005616fe2e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005616fe2dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42dda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005616fe2dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c (1254 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/223367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563732a1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563732a110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563732a1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe754f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe754f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe754f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe754f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637329a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005637329a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056373298eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056373263e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056373263ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe754f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe754f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe754f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056373263dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c (1255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec5d7ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec5d7aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec5d7ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4c3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4c338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4c3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4c331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec5d742e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec5d742c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec5d727b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec5d3d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec5d3d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe4c331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4c331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4c331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec5d3d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c (1256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 nou # | ... # `---data was truncated (10240/78890) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588edcb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588edcaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588edcb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f610af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f610af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f610af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f610af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588edc47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588edc47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588edc2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588ed8dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588ed8dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f610af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f610af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f610af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588ed8dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c (1257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617500d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005617500d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005617500d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5178c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5178ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5178c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5178c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056175006de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056175006dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561750052b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056174fd020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056174fd01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5178c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5178c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5178c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056174fd01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c (1258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_t # | ... # `---data was truncated (10240/128436) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c2351b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c235180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c2351b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5fcbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5fcbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5fcbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5fcbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c234b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c234b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c23495b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c231450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c23144dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5fcbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5fcbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5fcbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c23144cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c (1259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645b55f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645b55ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645b55f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e49849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e49849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e49831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645b5587e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645b5587c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645b556cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645b521c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645b521bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e49832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e498330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645b521bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c (1260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ccb8f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ccb8f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ccb8f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76b9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76b918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76b9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76b911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ccb88ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ccb88cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ccb871b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ccb5210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ccb520dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f76b911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76b911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76b911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ccb520cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c (1261 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | ... # `---data was truncated (10240/170489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1ad6ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1ad6ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1ad6ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e82f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e82f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e82f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e82f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1ad684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1ad684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1ad669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1ad3190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b1ad318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8e82f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e82f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e82f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1ad318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c (1262 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vabs_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vabs.i = bitcast <8 x i8> %1 to <4 x half> # | %vabs1.i = call <4 x half> @llvm.fabs.v4f16(<4 x half> %vabs.i) # | store <4 x half> %vabs1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %2, ptr %__ret.i, align 8 # | %3 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vabs.i = bitcast <16 x i8> %1 to <8 x half> # | %vabs1.i = call <8 x half> @llvm.fabs.v8f16(<8 x half> %vabs.i) # | store <8 x half> %vabs1.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %2, ptr %__ret.i, align 16 # | %3 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vceqz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oeq <4 x half> %2, zeroinitializer # | %vceqz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vceqz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oeq <8 x half> %2, zeroinitializer # | %vceqz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vceqz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp oge <4 x half> %2, zeroinitializer # | %vcgez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp oge <8 x half> %2, zeroinitializer # | %vcgez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ogt <4 x half> %2, zeroinitializer # | %vcgtz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcgtz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ogt <8 x half> %2, zeroinitializer # | %vcgtz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcgtz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vclez_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp ole <4 x half> %2, zeroinitializer # | %vclez.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vclez.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vclezq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp ole <8 x half> %2, zeroinitializer # | %vclez.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vclez.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vcltz_f16(<4 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %2 = bitcast <8 x i8> %1 to <4 x half> # | %3 = fcmp olt <4 x half> %2, zeroinitializer # | %vcltz.i = sext <4 x i1> %3 to <4 x i16> # | store <4 x i16> %vcltz.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %4, ptr %__ret.i, align 8 # | %5 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %2 = bitcast <16 x i8> %1 to <8 x half> # | %3 = fcmp olt <8 x half> %2, zeroinitializer # | %vcltz.i = sext <8 x i1> %3 to <8 x i16> # | store <8 x i16> %vcltz.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %4, ptr %__ret.i, align 16 # | %5 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloc # | ... # `---data was truncated (10240/122004) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056111ad0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056111acff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056111ad0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cb9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cb9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cb9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cb9aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056111ac97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056111ac97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056111ac7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056111a92c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056111a92bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7cb9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cb9aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cb9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056111a92bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c (1263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561bc819815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561bc81950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561bc819889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bd3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bd3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bd3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bd3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bc812de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561bc812dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561bc8112b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561bc7dc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561bc7dc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1bd3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bd3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bd3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bc7dc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c (1264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005651c0c5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005651c0c4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005651c0c5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c3f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c3f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c3f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c3f231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651c0be6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005651c0be6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005651c0bcbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005651c087b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005651c087add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c3f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c3f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c3f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651c087acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c (1265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fd814815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559fd81450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559fd814889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cc041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cc04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cc041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cc0403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fd80dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559fd80ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559fd80c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559fd7d720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559fd7d71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7cc0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cc04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cc04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fd7d71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c (1266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei32_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cb57cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558cb57c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558cb57cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef95f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef95f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef95f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef95eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cb5760e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558cb5760c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558cb5745b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558cb53f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558cb53f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fef95eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef95eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef95eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cb53f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c (1267 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve/maxnmv.c (1268 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve/maxnmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 has no command after substitutions # RUN: at line 6 has no command after substitutions # RUN: at line 8 has no command after substitutions # RUN: at line 9 has no command after substitutions # RUN: at line 10 has no command after substitutions # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +sve -o - -emit-llvm -disable-O0-optnone -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svmaxnmv_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svmaxnmv_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svmaxnmv_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(, ) #2 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg -S # | #0 0x000055724e23e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055724e23b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055724e23e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37cac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37caca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37cac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37cac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055724e1d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055724e1d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055724e1b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055724de680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055724de67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37cac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37cac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37cac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055724de67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve/maxnmv.c --check-prefixes=C,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c (1269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a21aa8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a21aa890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a21aa8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd613133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd61318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd613133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd61311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a21aa21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a21aa21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a21aa06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a21a6b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a21a6b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd61311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd61311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd61311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a21a6b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c (1270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056002fa2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056002fa210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056002fa2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b26631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056002f9b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056002f9b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056002f99eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056002f64e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056002f64ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b266330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056002f64dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c (1271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055723958e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055723958b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055723958e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f738e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f738e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f738e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f738e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557239523e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557239523c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557239508b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005572391b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005572391b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f738e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f738e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f738e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572391b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c (1272 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe1e45615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fe1e4530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fe1e45689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56e5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56e52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56e5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56e5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe1e3ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fe1e3ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fe1e3d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fe1e0800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fe1e07fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56e5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56e52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56e52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe1e07fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c (1273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f677f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f677f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f677f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae6741bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae674725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae6741ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae67403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f6778de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f6778dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f67772b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f674220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f67421dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae67404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae674050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae674050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f67421cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c (1274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d26b4c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d26b4bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d26b4c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3518649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35186a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3518649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3518631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d26b455e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d26b455c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d26b43ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d26b0ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d26b0e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3518632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35186330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35186330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d26b0e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c (1275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c (1276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612f358915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612f35860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005612f358989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2370f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2370f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2370f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2370f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612f351ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005612f351ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005612f3503b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005612f31b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005612f31b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2370f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2370f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2370f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612f31b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/neon/rounding.c (1277 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/rounding.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrnd_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndz1.i = call <2 x float> @llvm.trunc.v2f32(<2 x float> %vrndz.i) # | store <2 x float> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndz1.i = call <4 x float> @llvm.trunc.v4f32(<4 x float> %vrndz.i) # | store <4 x float> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrnd_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndz.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndz1.i = call <1 x double> @llvm.trunc.v1f64(<1 x double> %vrndz.i) # | store <1 x double> %vrndz1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndz.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndz1.i = call <2 x double> @llvm.trunc.v2f64(<2 x double> %vrndz.i) # | store <2 x double> %vrndz1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndn_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndn1.i = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %vrndn.i) # | store <2 x float> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndn1.i = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %vrndn.i) # | store <4 x float> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndn_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndn.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndn1.i = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %vrndn.i) # | store <1 x double> %vrndn1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndnq_f64(<2 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x double>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <2 x double>, align 16 # | store <2 x double> %a, ptr %a.addr, align 16 # | %0 = load <2 x double>, ptr %a.addr, align 16 # | store <2 x double> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndn.i = bitcast <16 x i8> %1 to <2 x double> # | %vrndn1.i = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %vrndn.i) # | store <2 x double> %vrndn1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x double>, ptr %ref.tmp.i, align 16 # | store <2 x double> %2, ptr %__ret.i, align 16 # | %3 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vrndns_f32(float noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vrndn.i = call float @llvm.roundeven.f32(float %1) # | store float %vrndn.i, ptr %ref.tmp.i, align 4 # | %2 = load float, ptr %ref.tmp.i, align 4 # | store float %2, ptr %__ret.i, align 4 # | %3 = load float, ptr %__ret.i, align 4 # | ret float %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndm_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndm1.i = call <2 x float> @llvm.floor.v2f32(<2 x float> %vrndm.i) # | store <2 x float> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vrndm.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndm1.i = call <4 x float> @llvm.floor.v4f32(<4 x float> %vrndm.i) # | store <4 x float> %vrndm1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %2, ptr %__ret.i, align 16 # | %3 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vrndm_f64(<1 x double> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndm.i = bitcast <8 x i8> %1 to <1 x double> # | %vrndm1.i = call <1 x double> @llvm.floor.v1f64(<1 x double> %vrndm.i) # | store <1 x double> %vrndm1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %2, ptr %__ret.i, align 8 # | %3 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vrndmq_f64(<2 x double> noundef %a # | ... # `---data was truncated (10240/29785) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000558797bee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558797beb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558797bee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fedf9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fedf9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fedf9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fedf9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558797b83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558797b83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558797b68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587978180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558797817dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fedf9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fedf9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fedf9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558797817cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/rounding.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c (1278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055771f3d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055771f3d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055771f3d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd7ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd7cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd7ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd7ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055771f36de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055771f36dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055771f352b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055771f0020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055771f001dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd7ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd7ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd7ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055771f001cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c (1279 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055767108115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055767107e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055767108189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fded4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fded46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fded4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fded4631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557671016e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557671016c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557670ffbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557670cab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557670caadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fded4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fded46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fded46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557670caacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c (1280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c (1281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c (1282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5c8c3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5c8c340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5c8c3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c6511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5c8bcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5c8bccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5c8bb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5c88610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5c8860dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0c6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c6511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5c8860cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c (1283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a3ac2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a3ac270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a3ac2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7dfae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7dfaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7dfae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7dfae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a3abbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a3abbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a3aba4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a3a8540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a3a853dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7dfae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7dfae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7dfae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a3a853cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c (1284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c (1285 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c02e49e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c02e49b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c02e49e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbac7e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbac7ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbac7e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbac7e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c02e433e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c02e433c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c02e418b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c02e0c80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c02e0c7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbac7e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbac7e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbac7e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c02e0c7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c (1286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b24fb9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b24fb990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b24fb9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dd5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dd5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dd5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dd5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b24fb31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b24fb31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b24fb16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b24f7c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b24f7c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4dd5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dd5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dd5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b24f7c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c (1287 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_s8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i8 @llvm.aarch64.sve.lasta.nxv16i8(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_s16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.aarch64.sve.lasta.nxv8i16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_s32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.lasta.nxv4i32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_s64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.lasta.nxv2i64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i8 @test_svlasta_u8( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call i8 @llvm.aarch64.sve.lasta.nxv16i8( %0, %1) # | ret i8 %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i16 @test_svlasta_u16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call i16 @llvm.aarch64.sve.lasta.nxv8i16( %2, %1) # | ret i16 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svlasta_u32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call i32 @llvm.aarch64.sve.lasta.nxv4i32( %2, %1) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svlasta_u64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call i64 @llvm.aarch64.sve.lasta.nxv2i64( %2, %1) # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local half @test_svlasta_f16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call half @llvm.aarch64.sve.lasta.nxv8f16( %2, %1) # | ret half %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare half @llvm.aarch64.sve.lasta.nxv8f16(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local float @test_svlasta_f32( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call float @llvm.aarch64.sve.lasta.nxv4f32( %2, %1) # | ret float %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.aarch64.sve.lasta.nxv4f32(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local double @test_svlasta_f64( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call double @llvm.aarch64.sve.lasta.nxv2f64( %2, %1) # | ret double %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.aarch64.sve.lasta.nxv2f64(, ) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local bfloat @test_svlasta_bf16( %pg, %op) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %3 = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( %2, %1) # | ret bfloat %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willretur # | ... # `---data was truncated (10240/10821) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055faed64b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055faed6480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055faed64b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f1ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f1cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f1ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f1ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055faed5e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055faed5e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055faed5c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055faed2750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055faed274dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f1ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f1ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f1ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055faed274cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c (1288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca # | ... # `---data was truncated (10240/97514) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f67769215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f67768f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f67769289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cc3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cc398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cc3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cc391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f677627e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f677627c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f67760cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6772bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6772bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9cc391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cc391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cc391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6772bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c (1289 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c487d1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c487d0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c487d1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66bf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c487ca5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c487ca5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c487c8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c48793a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c487939dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f66bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c487939cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c (1290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, al # | ... # `---data was truncated (10240/30861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056125456315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612545600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056125456389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d7001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d700725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d7001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d70003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612544f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005612544f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005612544ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056125418d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056125418cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4d70004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d700050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d700050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056125418ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c (1291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5e4f2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5e4f280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5e4f2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d46649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d466a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d46649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d46631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5e4ec0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5e4ec0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5e4ea5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5e4b550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5e4b54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d46632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d466330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d466330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5e4b54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c (1292 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( po # | ... # `---data was truncated (10240/50898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a0b11a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a0b1170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a0b11a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1ef933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1ef98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1ef933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1ef91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a0b0afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a0b0afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a0b094b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a0ad440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a0ad43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa1ef91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1ef91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1ef91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a0ad43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c (1293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e63bd9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e63bd900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e63bd9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58ba333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58ba38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58ba333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58ba31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e63bd28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e63bd28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e63bd0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e63b9bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e63b9bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f58ba31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58ba31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58ba31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e63b9bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c (1294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614ac03215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614ac02f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005614ac03289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f35fc505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35fc55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f35fc505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f35fc4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614abfc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005614abfc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005614abfacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005614abc5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005614abc5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f35fc4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35fc4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35fc4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614abc5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGenCoroutines/coro-gro4.cpp (1295 of 27911) ******************** TEST 'Clang :: CodeGenCoroutines/coro-gro4.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='default,default' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O2 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.wrapper = type { %struct.task } # | %struct.task = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { %"struct.std::coroutine_handle.0" } # | %"struct.std::coroutine_handle.0" = type { ptr } # | %"struct.task::promise_type" = type { i8 } # | %"struct.std::suspend_always" = type { i8 } # | # | $_ZN4task12promise_type17get_return_objectEv = comdat any # | # | $_ZN4task12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN4task12promise_type11return_voidEv = comdat any # | # | $_ZN4task12promise_type13final_suspendEv = comdat any # | # | $_ZN7wrapperC1EO4task = comdat any # | # | $_ZN4taskD1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZN4taskC1ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN4task12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | $_ZN4taskC2ESt16coroutine_handleINS_12promise_typeEE = comdat any # | # | $_ZN7wrapperC2EO4task = comdat any # | # | $_ZN4taskC1EOS_ = comdat any # | # | $_ZN4taskC2EOS_ = comdat any # | # | $_ZNSt16coroutine_handleIvEaSEDn = comdat any # | # | $_ZN4taskD2Ev = comdat any # | # | $_ZNKSt16coroutine_handleIvEcvbEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7destroyEv = comdat any # | # | ; Function Attrs: mustprogress nounwind presplitcoroutine # | define dso_local void @_Z2fnv(ptr dead_on_unwind noalias writable sret(%struct.wrapper) align 8 %agg.result) #0 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %gro.active = alloca i1, align 1 # | %__promise = alloca %"struct.task::promise_type", align 1 # | %__coro_gro = alloca %struct.task, align 8, !coro.outside.frame !6 # | %ref.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %ref.tmp2 = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp3 = alloca %"struct.std::suspend_always", align 1 # | store ptr %agg.result, ptr %result.ptr, align 8 # | %0 = call token @llvm.coro.id(i32 16, ptr %__promise, ptr null, ptr null) # | %1 = call i1 @llvm.coro.alloc(token %0) # | br i1 %1, label %coro.alloc, label %coro.init # | # | coro.alloc: ; preds = %entry # | %2 = call i64 @llvm.coro.size.i64() # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef %2) #14 # | br label %coro.init # | # | coro.init: ; preds = %coro.alloc, %entry # | %3 = phi ptr [ null, %entry ], [ %call, %coro.alloc ] # | %4 = call ptr @llvm.coro.begin(token %0, ptr %3) # | store i1 false, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %__promise) #9 # | call void @llvm.lifetime.start.p0(ptr %__coro_gro) #9 # | call void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind writable sret(%struct.task) align 8 %__coro_gro, ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | store i1 true, ptr %gro.active, align 1 # | call void @llvm.lifetime.start.p0(ptr %ref.tmp) #9 # | call void @_ZN4task12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call1 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br i1 %call1, label %init.ready, label %init.suspend # | # | init.suspend: ; preds = %coro.init # | %5 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__init) #9 # | %6 = call i8 @llvm.coro.suspend(token %5, i1 false) # | switch i8 %6, label %pre.gvo.conv [ # | i8 0, label %init.ready # | i8 1, label %init.cleanup # | ] # | # | init.cleanup: ; preds = %init.suspend # | br label %cleanup # | # | init.ready: ; preds = %init.suspend, %coro.init # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp) #9 # | br label %cleanup # | # | cleanup: ; preds = %init.ready, %init.cleanup # | %cleanup.dest.slot.0 = phi i32 [ 0, %init.ready ], [ 2, %init.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp) #9 # | switch i32 %cleanup.dest.slot.0, label %unreachable [ # | i32 0, label %cleanup.cont # | i32 2, label %coro.cleanup # | ] # | # | cleanup.cont: ; preds = %cleanup # | call void @_ZN4task12promise_type11return_voidEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | br label %coro.final # | # | coro.final: ; preds = %cleanup.cont # | call void @llvm.lifetime.start.p0(ptr %ref.tmp2) #9 # | call void @_ZN4task12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise) #9 # | %call4 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br i1 %call4, label %final.ready, label %final.suspend # | # | final.suspend: ; preds = %coro.final # | %7 = call token @llvm.coro.save(ptr null) # | call void @llvm.coro.await.suspend.void(ptr %ref.tmp2, ptr %4, ptr @_Z2fnv.__await_suspend_wrapper__final) #9 # | %8 = call i8 @llvm.coro.suspend(token %7, i1 true) # | switch i8 %8, label %pre.gvo.conv [ # | i8 0, label %final.ready # | i8 1, label %final.cleanup # | ] # | # | final.cleanup: ; preds = %final.suspend # | br label %cleanup5 # | # | final.ready: ; preds = %final.suspend, %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp2) #9 # | br label %cleanup5 # | # | cleanup5: ; preds = %final.ready, %final.cleanup # | %cleanup.dest.slot.1 = phi i32 [ 0, %final.ready ], [ 2, %final.cleanup ] # | call void @llvm.lifetime.end.p0(ptr %ref.tmp2) #9 # | switch i32 %cleanup.dest.slot.1, label %unreachable [ # | i32 0, label %pre.gvo.conv # | i32 2, label %coro.cleanup # | ] # | # | pre.gvo.conv: ; preds = %cleanup5, %final.suspend, %init.suspend # | %9 = phi i1 [ true, %cleanup5 ], [ false, %final.suspend ], [ false, %init.suspend ] # | %InRamp = call i1 @llvm.coro.is_in_ramp() # | br i1 %InRamp, label %gro.conv, label %after.gro.conv # | # | gro.conv: ; preds = %pre.gvo.conv # | call void @_ZN7wrapperC1EO4task(ptr noundef nonnull align 8 dereferenceable(8) %agg.result, ptr noundef nonnull align 8 dereferenceable(8) %__coro_gro) #9 # | %cleanup.is_active = load i1, ptr %gro.active, align 1 # | br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done # | # | cleanup.action: ; preds = %gro.conv # | call void @_ZN4taskD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %__coro_gro) #9 # | br label %cleanup.done # | # | cleanup.done: ; preds = %cleanup.action, %gro.conv # | br label %after.gro.conv # | # | after.gro.conv: ; preds = %cleanup.done, %pre.gvo.conv # | br i1 %9, label %cleanup.cont7, label %coro.ret # | # | cleanup.cont7: ; preds = %after.gro.conv # | br label %coro.cleanup # | # | coro.cleanup: ; preds = %cleanup.cont7, %cleanup5, %cleanup # | call void @llvm.lifetime.end.p0(ptr %__coro_gro) #9 # | call void @llvm.lifetime.end.p0(ptr %__promise) #9 # | %10 = call ptr @llvm.coro.free(token %0, ptr %4) # | %11 = icmp ne ptr %10, null # | br i1 %11, label %coro.free, label %after.coro.free # | # | coro.free: ; preds = %coro.cleanup # | %12 = call i64 @llvm.coro.size.i64() # | call void @_ZdlPvm(ptr noundef %10, i64 noundef %12) #9 # | br label %after.coro.free # | # | after.coro.free: ; preds = %coro.cleanup, %coro.free # | call void @llvm.coro.dead(ptr %4) # | br label %coro.ret # | # | coro.ret: ; preds = %after.coro.free, %after.gro.conv # | call void @llvm.coro.end(ptr null, i1 false, token none) # | ret void # | # | unreachable: ; preds = %cleanup5, %cleanup # | unreachable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare token @llvm.coro.id(i32, ptr readnone, ptr readonly captures(none), ptr) #1 # | # | ; Function Attrs: nounwind memory(none) # | declare i1 @llvm.coro.alloc(token) #2 # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #3 # | # | ; Function Attrs: nounwind memory(none) # | declare i64 @llvm.coro.size.i64() #2 # | # | ; Function Attrs: nounwind memory(argmem: readwrite) # | declare ptr @llvm.coro.begin(token, ptr writeonly) #4 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.lifetime.start.p0(ptr captures(none)) #5 # | # | ; Function Attrs: mustprogress nounwind # | define linkonce_odr void @_ZN4task12promise_type17get_return_objectEv(ptr dead_on_unwind noalias writable sret(%struct.task) align 8 %agg.result, ptr noundef nonnull align 1 dereferenceable(1) %this) #6 comdat align 2 { # | entry: # | %result.ptr = alloca ptr, align 8 # | %this.addr = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | store ptr %agg.result, ptr %result.ptr, align 8 # | store ptr %this, ptr %this.addr, align 8, !tbaa !7 # | %this1 = load ptr, ptr %this.addr, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN4task12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %agg.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"s # | ... # `---data was truncated (10240/31146) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt '-passes=default,default' -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=default,default -S # | #0 0x0000556d176c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d176c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d176c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21cd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21cd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21cd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21cd631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d1765be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d1765bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d17640b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d172f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d172efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21cd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21cd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21cd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d172efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/coro-gro4.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c (1296 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056213ed5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056213ed5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056213ed5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98edd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98edd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98edd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98edd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056213ecf3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056213ecf3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056213ecd8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056213e9880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056213e987dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98edd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98edd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98edd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056213e987cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c (1297 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c (1298 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056280299c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005628029990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056280299c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3db849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3db8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3db849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3db831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562802931e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562802931c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562802916b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005628025c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005628025c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe3db832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3db8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3db8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628025c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c (1299 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c (1300 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caaefb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055caaefb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055caaefb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70ca21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70ca2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70ca21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70ca203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caaef4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055caaef4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055caaef32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055caaebe20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055caaebe1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70ca204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70ca2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70ca2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caaebe1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c (1301 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredusum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfc208b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cfc20880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cfc208b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1df5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1df54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1df5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1df5431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfc2020e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cfc2020c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cfc2005b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cfc1cb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cfc1cb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1df5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1df54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1df54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfc1cb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrev.c (1302 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev32q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev64q_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shufflevector <16 x i8> %0, <16 x i8> poison, <16 x i32> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrev64q_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x i16> %0, <8 x i16> poison, <8 x i32> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev64q_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = shufflevector <8 x half> %0, <8 x half> poison, <8 x i32> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrev64q_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x float> %0, <4 x float> poison, <4 x i32> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrev64q_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev16q_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %0, i32 16, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrev32q_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half> %0, i32 32, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrev.predicated.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrev32q_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | # | ... # `---data was truncated (10240/29535) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c26575415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2657510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c26575489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04e9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2656e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2656e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c2656ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c26537e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c26537ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f04e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c26537dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c (1303 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/68255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563744f9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563744f8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563744f9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ef8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ef858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ef8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ef851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563744f25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563744f25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563744f0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563744bba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563744bb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ef851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ef851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ef851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563744bb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c (1304 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m4(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.x.nxv32i8.i64( poison, i8 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv32i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m8(i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i8, ptr %src.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/121927) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056067b06515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056067b0620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056067b06589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f885d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f885d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f885d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f885d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056067affae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056067affac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056067afdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056067ac8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056067ac8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f885d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f885d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f885d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056067ac8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c (1305 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3e3a0f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3e3a0c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3e3a0f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc74333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc7438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc74333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc7431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3e39a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e3e39a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e3e3989b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3e36390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3e3638dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc7431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc7431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc7431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3e3638cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c (1306 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c (1307 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e5m2_w4_f8e5m2m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056096e30115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056096e2fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056096e30189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9ef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9ef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9ef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9ef231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056096e296e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056096e296c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056096e27bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056096df2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056096df2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe9ef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9ef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9ef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056096df2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c (1308 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c (1309 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sme -target-feature +sme2 -target-feature +sve-b16b16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_m( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv8i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_z( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %2) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_x( %pg, %op1, %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store %op2, ptr %op2.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load , ptr %op2.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmax.u.nxv8bf16(, , ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_m( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_z( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = select %3, %1, zeroinitializer # | %5 = call @llvm.aarch64.sve.fmax.nxv8bf16( %3, %4, %.splat) # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmax_bf16_n_x( %pg, %op1, bfloat noundef %op2) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %op1.addr = alloca , align 16 # | %op2.addr = alloca bfloat, align 2 # | store %pg, ptr %pg.addr, align 2 # | store %op1, ptr %op1.addr, align 16 # | store bfloat %op2, ptr %op2.addr, align 2 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %op1.addr, align 16 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %0) # | %.splatinsert = insertelement poison, bfloat %2, i64 0 # | %.splat = shufflevector %.splatinsert, poison, zeroinitializer # | %4 = call @llvm.aarch64.sve.fmax.u.nxv8bf16( %3, %1, %.splat) # | ret %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2,+sve-b16b16" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine,tailcallelim # | #0 0x0000556cc359b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556cc35980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556cc359b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefe3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefe3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefe3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefe3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cc3530e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556cc3530c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556cc3515b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556cc31c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556cc31c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fefe3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefe3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefe3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cc31c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c (1310 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i32.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_u32m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, a # | ... # `---data was truncated (10240/29450) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e614c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005646e61490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005646e614c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdad1305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdad135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdad1305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdad12ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e60e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005646e60e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005646e60c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646e5d760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005646e5d75dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdad12eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdad12ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdad12ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e5d75cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c (1311 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vor.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vor_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/424049) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5a195315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5a19500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5a195389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7143c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7143ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7143c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7143c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5a18e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5a18e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5a18cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5a157d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5a157cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7143c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7143c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7143c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5a157ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c (1312 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vr # | ... # `---data was truncated (10240/96265) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c8962115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c8961e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c8962189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96d2d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96d2d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96d2d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96d2ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c895b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c895b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c8959bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c8924b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c8924add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f96d2ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96d2cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96d2cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c8924acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c (1313 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611d448215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005611d447f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005611d448289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd435b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd435b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd435b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd435aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005611d4417e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005611d4417c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005611d43fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005611d40ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005611d40abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd435aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd435aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd435aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611d40abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c (1314 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581ce93915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005581ce9360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005581ce93989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c56449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c564a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c56449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c56431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581ce8cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005581ce8cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005581ce8b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005581ce5630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005581ce562dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c56432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c564330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c564330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581ce562cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c (1315 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056463cca715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056463cca40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056463cca789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb02705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb0275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb02705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb026ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056463cc3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056463cc3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056463cc21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056463c8d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056463c8d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbb026eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb026ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb026ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056463c8d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c (1316 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr # | ... # `---data was truncated (10240/29319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b407c7815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b407c750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b407c7889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f401bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f401bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f401bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f401bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b407c0de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b407c0dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b407bf2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4078a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b4078a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f401bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f401bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f401bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4078a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c (1317 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c (1318 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c (1319 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, al # | ... # `---data was truncated (10240/81312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056523471015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056523470d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056523471089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa770f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa770f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa770f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa770f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652346a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005652346a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056523468ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056523433a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565234339dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa770f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa770f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa770f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565234339cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c (1320 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm3p1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sm3p1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm3p1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a298e9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a298e900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a298e9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e60649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e606a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e60649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e60631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a298e28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a298e28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a298e0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a298abd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a298abcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e60632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e606330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e606330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a298abccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksh.c -check-prefix=RV32ZKSH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c (1321 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c (1322 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vremu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559632a2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559632a250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559632a2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff027133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff02718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff027133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff02711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596329bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596329bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596329a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596326520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559632651dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff02711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff02711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff02711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559632651cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c (1323 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8cd1dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8cd1da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8cd1dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a34e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a34ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a34e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a34e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8cd172e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8cd172c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8cd157b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8cce070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8cce06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a34e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a34e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a34e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8cce06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c (1324 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc2d12c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc2d1290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc2d12c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4070d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4070d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4070d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4070d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc2d0c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc2d0c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc2d0a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc2cd560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc2cd55dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4070d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4070d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4070d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc2cd55cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c (1325 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c (1326 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsle.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643561b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643561ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643561b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3b801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3b80725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3b801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3b8003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564356146e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564356146c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056435612bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564355ddb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564355ddadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd3b8004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3b80050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3b80050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564355ddacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c (1327 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c (1328 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2315ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2315c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2315ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee7ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee7ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee7ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee7ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a23155fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a23155fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a231544b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2311f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2311f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fee7ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee7ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee7ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2311f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c (1329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/246606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc06e3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fc06e340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fc06e3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14a0649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14a06a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14a0649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14a0631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc06dcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fc06dccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fc06db1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fc06a610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fc06a60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14a0632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14a06330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14a06330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc06a60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c (1330 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b60d7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b60d6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b60d7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb832305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb83235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb832305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8322ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b60d05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b60d05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b60ceab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b6099a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b60999dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8322eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8322ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8322ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b60999cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c (1331 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c (1332 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv4i8.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv8i8.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.q.nxv16i8.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.q.mask.nxv1i8.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_q_f8e4m3mf8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/69542) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d4177715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d417740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d4177789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d0731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d4170ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d4170cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d416f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d413a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d413a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d0731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d413a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c (1333 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsne.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsne_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsne.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d318dec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d318de90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d318dec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eec133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eec18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eec133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eec11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d318d81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d318d81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d318d66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d318a160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d318a15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5eec11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eec11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eec11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d318a15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c (1334 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), p # | ... # `---data was truncated (10240/87316) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055645840115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564583fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055645840189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab26733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab2678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab26733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab2671b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556458396e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556458396c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055645837bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055645802b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055645802add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab2671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab2671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab2671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055645802acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c (1335 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056086ba2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056086ba250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056086ba2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f033b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f033b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f033b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f033b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056086b9bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056086b9bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056086b9a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056086b6520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056086b651dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f033b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f033b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f033b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056086b651cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c (1336 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv1f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv1f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16mf2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv2f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv2f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m1_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv4f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv4f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m2_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv8f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv8f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m4_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv16f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv16f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local half @test_vfmv_f_s_f16m8_f16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call half @llvm.riscv.vfmv.f.s.nxv32f16( %0) # | ret half %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare half @llvm.riscv.vfmv.f.s.nxv32f16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32mf2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv1f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv1f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m1_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv2f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m2_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv4f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv4f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m4_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv8f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv8f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @test_vfmv_f_s_f32m8_f32( %src) #0 { # | entry: # | %src.addr = alloca , align 4 # | store %src, ptr %src.addr, align 4 # | %0 = load , ptr %src.addr, align 4 # | %1 = call float @llvm.riscv.vfmv.f.s.nxv16f32( %0) # | ret float %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.riscv.vfmv.f.s.nxv16f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m1_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv1f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv1f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m2_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv2f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv2f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m4_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv4f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv4f64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local double @test_vfmv_f_s_f64m8_f64( %src) #0 { # | entry: # | %src.addr = alloca , align 8 # | store %src, ptr %src.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call double @llvm.riscv.vfmv.f.s.nxv8f64( %0) # | ret double %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.riscv.vfmv.f.s.nxv8f64() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645e58fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645e58f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645e58fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3682449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36824a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3682449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3682431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645e5891e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645e5891c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645e5876b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645e55260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645e5525dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3682432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36824330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36824330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645e5525cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c (1337 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2_tu( %maskedoff, %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i16, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = c # | ... # `---data was truncated (10240/207083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571d103515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005571d10320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005571d103589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5eed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5eed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5eed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5eed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571d0fcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005571d0fcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005571d0fafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005571d0c5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005571d0c5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5eed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5eed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5eed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571d0c5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c (1338 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c (1339 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv1i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e6df5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e6df520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e6df5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8005733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f800578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8005733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f800571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e6deeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e6deeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e6decfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e6db7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e6db7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f800571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f800571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f800571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e6db7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c (1340 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c (1341 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3256a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3256a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3256a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbaa933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbaa98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbaa933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbaa91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c32563de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c32563dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c325622b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c3252d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c3252d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbaa91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbaa91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbaa91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3252d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c (1342 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf29ae015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bf29add0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bf29ae089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f170861bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17086725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f170861ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1708603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf29a75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bf29a75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bf29a5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bf2970a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bf29709dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1708604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17086050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17086050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf29709cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c (1343 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c (1344 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef4b93915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef4b9360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef4b93989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b35d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b35d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b35d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b35d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef4b8cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef4b8cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef4b8b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef4b5630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef4b562dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b35d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b35d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b35d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef4b562cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c (1345 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b111e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b111e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b111e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafbd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafbd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafbd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafbd631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b1117ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b1117ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b11163b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b10e130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b10e12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fafbd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafbd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafbd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b10e12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c (1346 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f359e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f359df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f359e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b07733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b0778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b07733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b0771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f35977e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f35977c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f3595cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f3560c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f3560bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b0771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b0771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b0771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f3560bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c (1347 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591de63315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591de6300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591de63389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f125d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f125d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f125d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f125d203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591de5c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005591de5c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005591de5adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005591de25d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005591de25cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f125d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f125d2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f125d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591de25ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c (1348 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, # | ... # `---data was truncated (10240/157173) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055784870615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005578487030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055784870689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc53533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc5358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc53533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc5351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055784869be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055784869bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557848680b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005578483300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055784832fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efc5351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc5351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc5351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055784832fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c (1349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c (1350 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c (1351 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e67c6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e67c640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e67c6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f183ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f183ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183eced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e67bfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e67bfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e67be1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e678910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e67890dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f183eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e67890cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c (1352 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632b09db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632b09d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005632b09db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1784f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1784f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1784f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1784f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632b0970e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005632b0970c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005632b0955b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632b06050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005632b0604dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1784f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1784f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1784f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632b0604cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c (1353 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function # | ... # `---data was truncated (10240/66322) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055695a3c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055695a3c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055695a3c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4bf8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4bf84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4bf8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4bf8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055695a359e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055695a359c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055695a33eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556959fee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556959feddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4bf8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4bf84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4bf84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556959fedcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c (1354 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6(ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df9dace15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df9dacb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df9dace89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe95aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe95aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe95aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe95aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df9da63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df9da63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df9da48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df9d6f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df9d6f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe95aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe95aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe95aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df9d6f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c (1355 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/18691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e7bf1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e7bf150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e7bf1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12bd533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12bd58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12bd533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12bd51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e7beade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e7beadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e7be92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e7bb420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e7bb41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f12bd51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12bd51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12bd51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e7bb41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c (1356 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5ae21215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5ae20f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5ae21289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc09449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc094a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc09449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc09431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5ae1a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5ae1a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5ae18cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5ade3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5ade3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcc09432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc094330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc094330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5ade3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c (1357 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c (1358 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055794926215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055794925f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055794926289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5030d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5030d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5030d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5030d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579491f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579491f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579491dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557948e8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557948e8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5030d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5030d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5030d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557948e8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c (1359 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562265a9a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562265a970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562265a9a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf3f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf3f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf3f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf3f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562265a2fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562265a2fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562265a14b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622656c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622656c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf3f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf3f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf3f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622656c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c (1360 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkx -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm8_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm8.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @xperm4_32(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.xperm4.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm8.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.xperm4.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkx" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkx1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eeb170715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eeb17040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eeb170789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75ee849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75ee8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75ee849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75ee831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eeb169ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eeb169cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eeb1681b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eeb13310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eeb1330dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f75ee832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75ee8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75ee8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eeb1330cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkx.c -check-prefix=RV32ZBKX # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c (1361 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/58460) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595d4b2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595d4b250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595d4b2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe357133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe35718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe357133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe35711b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595d4abde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595d4abdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595d4aa2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595d47520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595d4751dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe35711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe35711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe35711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595d4751cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c (1362 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562020a1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562020a1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562020a1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f27e7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27e72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f27e7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f27e7231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620209b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620209b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562020997b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620206470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562020646dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f27e7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27e72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27e72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562020646cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c (1363 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 1) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.sqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_s32_1(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.sqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 31, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_s32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.sqdecw.n32(i32 %0, i32 31, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_s64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.sqdecw.n64(i64 %0, i32 0, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i32 @test_svqdecw_pat_n_u32(i32 noundef %op) #0 { # | entry: # | %op.addr = alloca i32, align 4 # | store i32 %op, ptr %op.addr, align 4 # | %0 = load i32, ptr %op.addr, align 4 # | %1 = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %0, i32 1, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local i64 @test_svqdecw_pat_n_u64(i64 noundef %op) #0 { # | entry: # | %op.addr = alloca i64, align 8 # | store i64 %op, ptr %op.addr, align 8 # | %0 = load i64, ptr %op.addr, align 8 # | %1 = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %0, i32 2, i32 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 31, i32 16) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.sqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 31, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.uqdecw.nxv4i32(, i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_s32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.sqdecw.nxv4i32( %0, i32 3, i32 16) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svqdecw_pat_u32( %op) #0 { # | entry: # | %op.addr = alloca , align 16 # | store %op, ptr %op.addr, align 16 # | %0 = load , ptr %op.addr, align 16 # | %1 = call @llvm.aarch64.sve.uqdecw.nxv4i32( %0, i32 4, i32 1) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055b3cc29415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b3cc2910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b3cc29489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb6b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb6b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb6b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb6b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3cc229e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3cc229c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3cc20eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b3cbebe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b3cbebddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbb6b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb6b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb6b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3cbebdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c (1364 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, pt # | ... # `---data was truncated (10240/73955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055923c8ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055923c8ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055923c8ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff807d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff807d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff807d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff807d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055923c882e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055923c882c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055923c867b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055923c5170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055923c516dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff807d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff807d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff807d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055923c516cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c (1365 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a6ac4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558a6ac4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558a6ac4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ff7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ff76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ff7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ff7631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a6abe2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558a6abe2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558a6abc7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558a6a8770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558a6a876dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9ff7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ff76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ff76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a6a876cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c (1366 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.nxv1i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.nxv2i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.nxv4i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m1( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.nxv8i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.nxv16i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.nxv32i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u8m8( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.nxv64i8.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf4( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 3, %0, %1, %2, i32 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.nxv1i16.i32(i32 immarg, , , , i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_vvv_se_u16mf2( %vd, %vs2, %vs1, i32 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i32, align 4 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.nxv # | ... # `---data was truncated (10240/255166) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a71a1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557a71a120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557a71a1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe140d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe140d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe140d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe140ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a719aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557a719aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557a7198fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557a7163f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557a7163edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe140ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe140cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe140cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a7163ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c (1367 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.i6 # | ... # `---data was truncated (10240/18619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e4dc9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e4dc960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e4dc9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3549733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f354978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3549733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f354971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e4dc2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e4dc2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e4dc13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e4d8c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e4d8c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f354971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f354971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f354971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e4d8c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c (1368 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 0, # | ... # `---data was truncated (10240/69839) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639bb8dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639bb8da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639bb8dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff81f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff81f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff81f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff81f631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639bb872e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639bb872c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639bb857b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639bb5070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639bb506dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff81f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff81f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff81f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639bb506cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c (1369 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b0ce5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b0ce590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b0ce5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbe8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbe818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbe8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbe811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b0cdf1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b0cdf1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b0cdd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b0ca860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b0ca85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbe811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbe811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbe811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b0ca85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c (1370 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644a4fcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644a4fc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644a4fcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe184449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1844a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe184449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe184431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644a4f60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644a4f60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644a4f45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644a4bf50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644a4bf4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe184432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1844330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1844330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644a4bf4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c (1371 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63df1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c63df0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c63df1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7b1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7b198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7b1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7b191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63dea7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c63dea7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c63de8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c63db3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c63db3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd7b191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7b191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7b191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63db3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c (1372 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8f5eed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8f5eea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8f5eed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0128d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0128d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0128d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0128ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8f5e82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8f5e82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8f5e67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8f5b170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8f5b16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0128ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0128cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0128cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8f5b16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c (1373 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c (1374 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf8_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv1i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv1i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf4_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv2i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv2i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8mf2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv4i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv4i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m1_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv8i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv8i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_x_i8m2_tu( %maskedoff, i8 noundef signext %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i8 %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i8, ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmv.v.x.nxv16i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.x.nxv16i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/134744) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563701e4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563701e400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563701e4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0feb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0feb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0feb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0feb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563701dd8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563701dd8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563701dbdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563701a6d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563701a6cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0feb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0feb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0feb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563701a6ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c (1375 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557651ef915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557651ef60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557651ef989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4ff305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4ff35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4ff305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4ff2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557651e8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557651e8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557651e73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557651b230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557651b22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4ff2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4ff2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4ff2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557651b22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c (1376 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576323a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055763239e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005576323a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa6d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa6d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa6d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa6d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557632336e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557632336c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055763231bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557631fcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557631fcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa6d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa6d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa6d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557631fcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c (1377 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cd2e8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564cd2e8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564cd2e8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04a8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04a84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04a8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04a8431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cd2e24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564cd2e24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564cd2e09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564cd2ab90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564cd2ab8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f04a8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04a84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04a84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cd2ab8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c (1378 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c (1379 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee7d94f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee7d94c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee7d94f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6573449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6573449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6573431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee7d8e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee7d8e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee7d8c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee7d5790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee7d578dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6573432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65734330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee7d578cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/thinlto-multi-module.ll (1380 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-multi-module.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-multi-module.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-multi-module.ll # | #0 0x00005637e2d7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005637e2d730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005637e2d7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f862ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f862caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f862ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f862ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637e2d0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005637e2d0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005637e2cf0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005637e29a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005637e299fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f862ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f862ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f862ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637e299fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c (1381 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005645fee4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645fee4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005645fee4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff91e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff91e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff91e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff91e6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645fede3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645fede3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645fedc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645fea780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005645fea77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff91e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff91e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff91e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005645fea77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c (1382 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c (1383 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/135997) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056239ee0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056239ee000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056239ee0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1bdc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1bdca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1bdc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1bdc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056239ed98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056239ed98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056239ed7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056239ea2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056239ea2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1bdc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1bdc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1bdc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056239ea2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c (1384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5adfa915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5adfa60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5adfa989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8c4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8c46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8c4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8c4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5adf3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5adf3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5adf23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5adbd30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5adbd2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe8c4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8c46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8c46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5adbd2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c (1385 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , al # | ... # `---data was truncated (10240/92370) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf86d4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bf86d410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bf86d4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0b3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0b38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0b3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0b3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf86cd9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bf86cd9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bf86cbeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bf8696e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bf8696ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0b3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0b38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0b38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf8696dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c (1386 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test # | ... # `---data was truncated (10240/94993) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ff6b3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ff6b2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ff6b3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b17705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b1775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b17705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b176ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ff6ac7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ff6ac7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ff6aacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ff675c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ff675bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b176eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b176ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b176ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ff675bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c (1387 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4_tu( %maskedoff, %op1, %op2, i6 # | ... # `---data was truncated (10240/157165) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e47ce7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e47ce6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e47ce7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c2dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c2dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c2dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c2dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e47ce05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e47ce05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e47cdeab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e47ca9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e47ca99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c2dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c2dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c2dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e47ca99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c (1388 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b58b1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b58b120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b58b1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fa5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fa5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fa5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fa5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b58aaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b58aaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b58a8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b5873f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b5873edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4fa5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fa5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fa5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b5873ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c (1389 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f4909c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562f490990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562f4909c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb06de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb06dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb06de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb06de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f49031e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562f49031c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562f49016b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562f48cc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562f48cc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb06de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb06de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb06de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f48cc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c (1390 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056055d16815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056055d1650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056055d16889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9906449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99064a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9906449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9906431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056055d0fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056055d0fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056055d0e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056055cd920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056055cd91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9906432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99064330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99064330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056055cd91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c (1391 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ # | ... # `---data was truncated (10240/18570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595fc73115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595fc72e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595fc73189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7645133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f764518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7645133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f764511b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595fc6c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595fc6c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595fc6abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595fc35b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595fc35add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f764511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f764511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f764511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595fc35acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c (1392 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c (1393 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4c118015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4c117d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4c118089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f161701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16170725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f161701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1617003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4c1115e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a4c1115c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a4c10fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4c0daa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4c0da9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1617004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16170050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16170050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4c0da9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c (1394 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv8i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv4i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.to.svbool.nxv2i1() #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 0) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_1() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 1) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_2() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 2) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_3() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 3) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_4() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 4) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_5() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 5) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_6() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 6) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_7() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 7) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_8() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 8) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_9() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 9) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_10() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 10) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_11() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 11) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_12() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 12) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_13() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 13) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_14() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 29) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_15() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 30) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b8_16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b16() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 0) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b32() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 1) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svptrue_pat_b64() #0 { # | entry: # | %0 = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 2) # | %1 = call @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %0) # | ret %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x00005555b414615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005555b41430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005555b414689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f68f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f68f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f68f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f68f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555b40dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005555b40dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005555b40c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005555b3d700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005555b3d6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6f68f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f68f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f68f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555b3d6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c (1395 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056268b6a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056268b6a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056268b6a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f064bf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f064bf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f064bf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f064beed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056268b639e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056268b639c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056268b61eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056268b2ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056268b2cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f064beeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f064beef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f064beef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056268b2cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c (1396 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b61923415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6192310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b61923489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9c0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9c0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9c0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9c0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6191c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6191c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6191aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b618e5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b618e5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9c0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9c0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9c0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b618e5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c (1397 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d409d6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d409d5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d409d6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fd4a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fd4aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fd4a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fd4a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d409cf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d409cf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d409cdcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d40998c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d40998bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8fd4a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fd4a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fd4a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d40998bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c (1398 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb48bc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb48bc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb48bc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd170533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd17058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd170533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd17051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb48b5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb48b5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb48b42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb487f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb487f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd17051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd17051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd17051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb487f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c (1399 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | % # | ... # `---data was truncated (10240/13690) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de9d69c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055de9d6990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055de9d69c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11ccc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11ccc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11ccc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11ccc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de9d631e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055de9d631c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055de9d616b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055de9d2c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055de9d2c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11ccc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11ccc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11ccc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de9d2c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c (1400 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056054026215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056054025f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056054026289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5ec649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5ec6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5ec649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5ec631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605401f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005605401f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005605401dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056053fe8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056053fe8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5ec632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5ec6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5ec6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056053fe8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c (1401 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noin # | ... # `---data was truncated (10240/25042) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630bdbb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630bdbaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005630bdbb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30b611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630bdb47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005630bdb47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005630bdb2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005630bd7dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005630bd7dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f30b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30b611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630bd7dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c (1402 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c92bf5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c92bf4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c92bf5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a8fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a8fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a8fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a8faed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c92bee6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c92bee6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c92becbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c92bb7b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c92bb7add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4a8faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a8faef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a8faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c92bb7acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c (1403 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d99432615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9943230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d99432689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b79133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b7918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b79133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b7911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9942bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9942bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9942a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d993f500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d993f4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b7911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b7911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b7911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d993f4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c (1404 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memor # | ... # `---data was truncated (10240/113039) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638f375d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638f375a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005638f375d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85c8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85c82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85c8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85c8231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638f36f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638f36f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638f36d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638f33870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638f3386dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85c8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85c82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85c82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638f3386cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c (1405 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596fd86715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596fd8640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596fd86789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdff4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdff498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdff4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdff491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596fd7fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596fd7fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596fd7e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596fd4910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596fd490dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdff491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdff491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdff491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596fd490cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c (1406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca targe # | ... # `---data was truncated (10240/53556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9ef2c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9ef2be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9ef2c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe21d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe21d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe21d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe21d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9ef256e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9ef256c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9ef23bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9eeeeb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9eeeeadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe21d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe21d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe21d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9eeeeacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-shifts.c (1407 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-apple-darwin -disable-O0-optnone -target-cpu cortex-a8 -ffreestanding -emit-llvm -w -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c" # | target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "thumbv7-apple-darwin" # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = lshr <8 x i8> %1, splat (i8 5) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_smax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | %vshr_n = ashr <8 x i8> %1, splat (i8 7) # | store <8 x i8> %vshr_n, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vshr_umax(<8 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %__s0, align 8 # | store <8 x i8> zeroinitializer, ptr %ref.tmp, align 8 # | %2 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %2, ptr %__ret, align 8 # | %3 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %3, ptr %tmp, align 8 # | %4 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = lshr <8 x i8> %3, splat (i8 5) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_smax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vsra_n = ashr <8 x i8> %3, splat (i8 7) # | %4 = add <8 x i8> %2, %vsra_n # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i8> @test_shift_vsra_umax(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = add <8 x i8> %2, zeroinitializer # | store <8 x i8> %4, ptr %ref.tmp, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %5, ptr %__ret, align 8 # | %6 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %6, ptr %tmp, align 8 # | %7 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a8" "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp" } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"apcs-gnu"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558db622715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558db62240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558db622789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff497933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff49798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff497933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff49791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558db61bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558db61bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558db61a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558db5e510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558db5e50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff49791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff49791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff49791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558db5e50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c (1408 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc. # | ... # `---data was truncated (10240/101402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e43b6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558e43b5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558e43b6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4388249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43882a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4388249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4388231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e43af5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558e43af5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558e43adab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558e4378a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558e43789dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4388232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43882330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43882330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e43789cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c (1409 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cabdb8815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cabdb850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cabdb8889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86f6505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86f655c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86f6505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86f64ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cabdb1de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cabdb1dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cabdb02b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cabd7b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cabd7b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f86f64eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86f64ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86f64ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cabd7b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c (1410 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vundefined_bf16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf4x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf4x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf4x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf4x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf4x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf4x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16mf2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16mf2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16mf2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16mf2x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16mf2x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16mf2x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16mf2x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m1x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m1x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m1x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vundefined_bf16m1x5() #0 { # | entry: # | ret target("riscv.vector.tuple", , 5) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vundefined_bf16m1x6() #0 { # | entry: # | ret target("riscv.vector.tuple", , 6) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vundefined_bf16m1x7() #0 { # | entry: # | ret target("riscv.vector.tuple", , 7) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vundefined_bf16m1x8() #0 { # | entry: # | ret target("riscv.vector.tuple", , 8) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m2x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vundefined_bf16m2x3() #0 { # | entry: # | ret target("riscv.vector.tuple", , 3) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vundefined_bf16m2x4() #0 { # | entry: # | ret target("riscv.vector.tuple", , 4) poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vundefined_bf16m4x2() #0 { # | entry: # | ret target("riscv.vector.tuple", , 2) poison # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650a1c1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650a1c120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650a1c1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae57831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650a1baae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650a1baac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650a1b8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650a183f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650a183edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650a183ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c (1411 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl # | ... # `---data was truncated (10240/78896) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a1d262515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a1d26220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a1d262589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7108b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7108b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7108b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7108b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a1d25bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a1d25bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a1d259fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a1d224f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a1d224edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7108b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7108b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7108b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a1d224ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c (1412 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/32702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633d225c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633d22590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633d225c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9abf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9abf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9abf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9abf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633d21f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633d21f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633d21d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633d1e860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633d1e85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9abf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9abf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9abf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633d1e85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c (1413 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c (1414 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650c1be415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650c1be10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650c1be489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec3e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec3e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec3e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec3e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650c1b79e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650c1b79c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650c1b5eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650c180e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650c180ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec3e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec3e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec3e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650c180dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c (1415 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641ec5f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641ec5f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641ec5f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25bb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25bb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25bb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25bb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641ec58ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005641ec58ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005641ec56fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641ec21f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641ec21edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25bb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25bb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25bb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641ec21ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c (1416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f47afc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555f47af90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555f47afc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24aec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24aeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24aec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24aec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f47a91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555f47a91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555f47a76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555f477260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555f47725dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f24aec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24aec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24aec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f47725cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-extract.c (1417 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__s0, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %vext = shufflevector <8 x i8> %2, <8 x i8> %3, <8 x i32> # | store <8 x i8> %vext, ptr %ref.tmp, align 8 # | %4 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <8 x i8> %4, ptr %__ret, align 8 # | %5 = load <8 x i8>, ptr %__ret, align 8 # | store <8 x i8> %5, ptr %tmp, align 8 # | %6 = load <8 x i8>, ptr %tmp, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %__s1 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <4 x i16> # | %5 = bitcast <8 x i8> %3 to <4 x i16> # | %vext = shufflevector <4 x i16> %4, <4 x i16> %5, <4 x i32> # | store <4 x i16> %vext, ptr %ref.tmp, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %6, ptr %__ret, align 8 # | %7 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %7, ptr %tmp, align 8 # | %8 = load <4 x i16>, ptr %tmp, align 8 # | ret <4 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %__s1 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <2 x i32> # | %5 = bitcast <8 x i8> %3 to <2 x i32> # | %vext = shufflevector <2 x i32> %4, <2 x i32> %5, <2 x i32> # | store <2 x i32> %vext, ptr %ref.tmp, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp, align 8 # | store <2 x i32> %6, ptr %__ret, align 8 # | %7 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %7, ptr %tmp, align 8 # | %8 = load <2 x i32>, ptr %tmp, align 8 # | ret <2 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | %__ret = alloca <1 x i64>, align 8 # | %__s0 = alloca <1 x i64>, align 8 # | %__s1 = alloca <1 x i64>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__s0, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %1, ptr %__s1, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = load <8 x i8>, ptr %__s1, align 8 # | %4 = bitcast <8 x i8> %2 to <1 x i64> # | %5 = bitcast <8 x i8> %3 to <1 x i64> # | %vext = shufflevector <1 x i64> %4, <1 x i64> %5, <1 x i32> zeroinitializer # | store <1 x i64> %vext, ptr %ref.tmp, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp, align 8 # | store <1 x i64> %6, ptr %__ret, align 8 # | %7 = load <1 x i64>, ptr %__ret, align 8 # | store <1 x i64> %7, ptr %tmp, align 8 # | %8 = load <1 x i64>, ptr %tmp, align 8 # | ret <1 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca <16 x i8>, align 16 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__s0, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %vext = shufflevector <16 x i8> %2, <16 x i8> %3, <16 x i32> # | store <16 x i8> %vext, ptr %ref.tmp, align 16 # | %4 = load <16 x i8>, ptr %ref.tmp, align 16 # | store <16 x i8> %4, ptr %__ret, align 16 # | %5 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %5, ptr %tmp, align 16 # | %6 = load <16 x i8>, ptr %tmp, align 16 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca <8 x i16>, align 16 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__s0, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <8 x i16> # | %5 = bitcast <16 x i8> %3 to <8 x i16> # | %vext = shufflevector <8 x i16> %4, <8 x i16> %5, <8 x i32> # | store <8 x i16> %vext, ptr %ref.tmp, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp, align 16 # | store <8 x i16> %6, ptr %__ret, align 16 # | %7 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %7, ptr %tmp, align 16 # | %8 = load <8 x i16>, ptr %tmp, align 16 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca <4 x i32>, align 16 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__s0, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <4 x i32> # | %5 = bitcast <16 x i8> %3 to <4 x i32> # | %vext = shufflevector <4 x i32> %4, <4 x i32> %5, <4 x i32> # | store <4 x i32> %vext, ptr %ref.tmp, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp, align 16 # | store <4 x i32> %6, ptr %__ret, align 16 # | %7 = load <4 x i32>, ptr %__ret, align 16 # | store <4 x i32> %7, ptr %tmp, align 16 # | %8 = load <4 x i32>, ptr %tmp, align 16 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | %__ret = alloca <2 x i64>, align 16 # | %__s0 = alloca <2 x i64>, align 16 # | %__s1 = alloca <2 x i64>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | store <2 x i64> %0, ptr %__s0, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %1, ptr %__s1, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = load <16 x i8>, ptr %__s1, align 16 # | %4 = bitcast <16 x i8> %2 to <2 x i64> # | %5 = bitcast <16 x i8> %3 to <2 x i64> # | %vext = shufflevector <2 x i64> %4, <2 x i64> %5, <2 x i32> # | store <2 x i64> %vext, ptr %ref.tmp, align 16 # | %6 = load <2 x i64>, ptr %ref.tmp, align 16 # | store <2 x i64> %6, ptr %__ret, align 16 # | %7 = load <2 x i64>, ptr %__ret, align 16 # | store <2 x i64> %7, ptr %tmp, align 16 # | %8 = load <2 x i64>, ptr %tmp, align 16 # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret = alloca <8 x i8>, align 8 # | %__s0 = alloca <8 x i8>, align 8 # | %__s1 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <8 x i8>, align 8 # | store <8 x i8> # | ... # `---data was truncated (10240/29598) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005620e140e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620e140b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005620e140e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7f681bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7f68725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7f681ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7f6803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620e13a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620e13a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005620e1388b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620e10380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005620e1037dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa7f6804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7f68050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7f68050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620e1037cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c (1418 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c (1419 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, ali # | ... # `---data was truncated (10240/63510) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0b124d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0b124a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e0b124d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcc6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcc62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcc6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcc6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0b11e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e0b11e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e0b11c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e0b0e770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e0b0e76dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efcc6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcc62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcc62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0b0e76cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c (1420 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vx_u8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhu_vv_u8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/65883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056255784415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625578410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056255784489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b2ac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b2ac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b2ac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b2ac03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625577d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625577d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625577beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056255746e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056255746ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6b2ac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b2ac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b2ac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056255746dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c (1421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635817a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056358179f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005635817a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefbbc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefbbca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefbbc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefbbc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563581737e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563581737c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056358171cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635813cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005635813cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fefbbc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefbbc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefbbc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635813cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c (1422 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m4_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f16m8_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32f16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32f16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32mf2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m1_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store i64 %offset, ptr %offset.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %dest.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %offset.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2f32.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2f32.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslideup_vx_f32m2_tu( %dest, %src, i64 noundef %offset, i64 noundef %vl) #0 { # | entry: # | %dest.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %offset.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %dest, ptr %dest.addr, ali # | ... # `---data was truncated (10240/280217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607a2ce515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005607a2ce20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005607a2ce589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d36933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d3698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d36933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d3691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607a2c7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607a2c7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607a2c5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607a290f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607a290edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d3691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d3691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d3691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607a290ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c (1423 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c (1424 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056163d24915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056163d2460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056163d24989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f49d3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49d338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f49d3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f49d331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056163d1dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056163d1dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056163d1c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056163ce730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056163ce72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f49d331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49d331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49d331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056163ce72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c (1425 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/306627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6cde5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6cde5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6cde5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c9e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c9e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c9e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c9e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6cddf4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f6cddf4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6cddd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6cda890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6cda88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c9e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c9e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c9e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6cda88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c (1426 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c (1427 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv # | ... # `---data was truncated (10240/47720) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650cf2aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650cf2a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650cf2aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e10d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e10d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e10d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e10d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650cf23fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650cf23fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650cf224b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650ceed40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650ceed3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e10d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e10d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e10d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650ceed3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c (1428 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_u16mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline n # | ... # `---data was truncated (10240/28559) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055849c40215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055849c3ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055849c40289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe42541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4254725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe42541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe425403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055849c397e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055849c397c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055849c37cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055849c02c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055849c02bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe425404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4254050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4254050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055849c02bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c (1429 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c (1430 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df7c14a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df7c1470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df7c14a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7c7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7c775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7c7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7c76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df7c0dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df7c0dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df7c0c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df7bd740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df7bd73dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc7c76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7c76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7c76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df7bd73cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c (1431 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6c067715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6c06740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6c067789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cf0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cf08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cf0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cf0831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6c060ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6c060cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6c05f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6c02a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6c02a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2cf0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cf08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cf08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6c02a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c (1432 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1up.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.add # | ... # `---data was truncated (10240/86739) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c78fa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c78fa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c78fa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d56f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d56f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d56f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d56f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c78f3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c78f3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c78f21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c78bd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c78bd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2d56f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d56f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d56f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c78bd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c (1433 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align # | ... # `---data was truncated (10240/26572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acd951915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055acd95160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055acd951989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f926b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f926b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f926b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f926b403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acd94aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055acd94aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055acd9493b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055acd91430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055acd9142dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f926b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f926b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f926b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acd9142cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c (1434 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560f132f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560f132f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560f132f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa64a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa64a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa64a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa64a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560f1328ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560f1328cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560f13271b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560f12f210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560f12f20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa64a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa64a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa64a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560f12f20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c (1435 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca505a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca5059d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca505a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64a0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64a058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64a0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64a051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca50535e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca50535c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca5051ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca501ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca501c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64a051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64a051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64a051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca501c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c (1436 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c (1437 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c (1438 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i32.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c (1439 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d06ea2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d06ea1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d06ea2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23ce905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23ce95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23ce905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23ce8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d06e9b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d06e9b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d06e99ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d06e64a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d06e649dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23ce8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23ce8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23ce8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d06e649cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c (1440 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c (1441 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056325557915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632555760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056325557989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f34ff849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f34ff8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f34ff849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f34ff831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056325550ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056325550ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005632554f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632551a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005632551a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f34ff832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f34ff8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f34ff8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632551a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c (1442 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600479b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005600479b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005600479b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9d6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9d618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9d6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9d611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056004794ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056004794cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560047931b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600475e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600475e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9d611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9d611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9d611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600475e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c (1443 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tupl # | ... # `---data was truncated (10240/88444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605b8d4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005605b8d410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005605b8d4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06d4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06d4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06d4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06d4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605b8cd9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005605b8cd9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005605b8cbeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005605b896e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005605b896ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f06d4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06d4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06d4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605b896dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c (1444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c28261115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c28260e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c28261189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5001533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f500158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5001533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f500151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2825a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2825a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c28258bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c28223b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c28223add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f500151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f500151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f500151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c28223acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c (1445 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b94ceb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b94ce80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b94ceb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff180e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff180ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff180e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff180e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b94c80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b94c80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b94c65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b949150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b94914dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff180e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff180e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff180e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b94914cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c (1446 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a16d6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a16d640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a16d6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9493d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9493d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9493d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9493d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a16cfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a16cfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a16ce1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a169910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a16990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9493d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9493d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9493d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a16990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c (1447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captu # | ... # `---data was truncated (10240/87308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619d8f3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005619d8f3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619d8f3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3985e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3985ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3985e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3985e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619d8ed2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005619d8ed2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005619d8eb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619d8b670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619d8b66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3985e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3985e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3985e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619d8b66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c (1448 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec3b58915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec3b5860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec3b58989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b53e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b53e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b53e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b53e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec3b51ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec3b51ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec3b503b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec3b1b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec3b1b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b53e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b53e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b53e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec3b1b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c (1449 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c (1450 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a67e0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a67e090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a67e0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0630133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f063018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0630133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f063011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a67da1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a67da1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a67d86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a67a360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a67a35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f063011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f063011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f063011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a67a35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c (1451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056544053f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056544053c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056544053f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6108533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f610858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6108533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f610851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654404d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005654404d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005654404b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654401690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565440168dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f610851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f610851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f610851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565440168cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c (1452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ce0b2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563ce0b220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563ce0b2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe11e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe11e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe11e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe11e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ce0abae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563ce0abac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563ce0a9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563ce074f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563ce074edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe11e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe11e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe11e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ce074ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c (1453 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c (1454 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633afdf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633afdf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633afdf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd644933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd64498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd644933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd64491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633afd8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633afd8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633afd73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633afa230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633afa22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd64491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd64491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd64491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633afa22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c (1455 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei16_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a579d3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a579d2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a579d3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9ab905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9ab95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9ab905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9ab8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a579cc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a579cc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a579cacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a57995c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a57995bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9ab8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9ab8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9ab8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a57995bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c (1456 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c (1457 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c (1458 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602b697615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602b69730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602b697689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc92905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc9295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc92905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc928ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602b690be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602b690bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602b68f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602b65a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005602b659fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc928eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc928ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc928ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602b659fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c (1459 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602fa15115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602fa14e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602fa15189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc5f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc5f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc5f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc5f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602fa0e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602fa0e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602fa0cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602f9d7b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005602f9d7add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc5f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc5f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc5f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602f9d7acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c (1460 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c (1461 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/101576) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d673f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d673f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d673f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3c1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3c198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3c1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3c191b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d6738ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d6738ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d6736fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d6701f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d6701edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3c191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3c191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3c191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d6701ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c (1462 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c (1463 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, # | ... # `---data was truncated (10240/142319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dcf36e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dcf36b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dcf36e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb59a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb59aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb59a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb59a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dcf303e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dcf303c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dcf2e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dcef980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dcef97dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb59a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb59a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb59a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dcef97cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c (1464 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32. # | ... # `---data was truncated (10240/101394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055958291315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595829100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055958291389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00d7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00d7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00d7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00d7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595828a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595828a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055958288db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055958253d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055958253cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f00d7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00d7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00d7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055958253ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c (1465 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c (1466 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563048a6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563048a5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563048a6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dc0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dc0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dc0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dc0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630489f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005630489f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005630489dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056304868c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056304868bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dc0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dc0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dc0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056304868bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll (1467 of 27911) ******************** TEST 'Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenCXX/Output/thinlto_public_type_test_distributed.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/thinlto_public_type_test_distributed.ll # | #0 0x0000555a6e70d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a6e70a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a6e70d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa2a533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa2a58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa2a533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa2a51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a6e6a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a6e6a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a6e687b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a6e3370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a6e336dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa2a51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa2a51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa2a51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a6e336cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c (1468 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055826750a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582675070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055826750a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfc941bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfc94725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfc941ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfc9403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055826749fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055826749fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558267484b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582671340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558267133dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfc9404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfc94050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfc94050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558267133cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c (1469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, # | ... # `---data was truncated (10240/26468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563e1bc415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005563e1bc10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005563e1bc489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f333b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f333b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f333b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f333b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563e1b59e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005563e1b59c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005563e1b3eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005563e17ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005563e17eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f333b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f333b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f333b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563e17edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c (1470 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1up.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1up.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1up_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = # | ... # `---data was truncated (10240/210435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563839f1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563839f160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563839f1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd367533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd36758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd367533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd36751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563839eaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563839eaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563839e93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563839b430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563839b42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd36751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd36751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd36751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563839b42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c (1471 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fd0c5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556fd0c4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556fd0c5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4ac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4ac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4ac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4ac231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fd0be7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556fd0be7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556fd0bccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556fd087c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556fd087bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4ac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4ac2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4ac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fd087bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c (1472 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsleu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a7666d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a7666a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a7666d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa40e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa40e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa40e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa40e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a76602e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a76602c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a765e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a762970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a76296dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa40e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa40e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa40e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a76296cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c (1473 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c (1474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8eea7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8eea720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8eea7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9b5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9b56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9b5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9b5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8eea0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c8eea0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c8ee9efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8ee69f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8ee69edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb9b5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9b56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9b56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8ee69ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c (1475 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/116259) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b92223f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b92223c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b92223f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd88d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd88d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd88d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd88d403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9221d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9221d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9221b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b921e690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b921e68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd88d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd88d4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd88d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b921e68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c (1476 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsa # | ... # `---data was truncated (10240/179511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a6c0fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a6c0fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a6c0fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1fe049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1fe0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1fe049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1fe031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a6c093e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a6c093c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a6c078b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a6bd280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a6bd27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1fe032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1fe0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1fe0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a6bd27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c (1477 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/15211) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d8ea2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d8ea1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d8ea2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabfb61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabfb6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabfb61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabfb603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d8e9b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d8e9b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d8e99cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d8e64c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d8e64bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fabfb604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabfb6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabfb6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d8e64bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c (1478 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_u64m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b2f45315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b2f4500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b2f45389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f864ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f864ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f864ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f864ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b2f3e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b2f3e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b2f3cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b2f07d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b2f07cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f864ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f864ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f864ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b2f07ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c (1479 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d934a2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d934a290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d934a2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28f041bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28f04725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28f041ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28f0403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9349c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9349c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9349a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9346560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d934655dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28f0404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28f04050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28f04050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d934655cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c (1480 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vandn.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c (1481 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c (1482 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056520fcae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056520fcab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056520fcae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2a8333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2a838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2a8333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2a831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056520fc43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056520fc43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056520fc28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056520f8d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056520f8d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2a831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2a831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2a831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056520f8d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c (1483 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32, <8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32, <4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 2, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 2, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = call <8 x half> @llvm.arm.mve.vcmlaq.v8f16(i32 3, <8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = call <4 x float> @llvm.arm.mve.vcmlaq.v4f32(i32 3, <4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmlaq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmlaq_rot90_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %c.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmlaq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmlaq_rot90_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> % # | ... # `---data was truncated (10240/15051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556bd51315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005556bd5100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005556bd51389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff51481bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5148725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff51481ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff514803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556bd4a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005556bd4a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005556bd48db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005556bd13d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005556bd13cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff514804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5148050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5148050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556bd13ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmlaq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c (1484 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(< # | ... # `---data was truncated (10240/11404) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d930d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d930d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d930d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e8bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e8bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e8bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e8bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d9306ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d9306ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d9304fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d92cff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d92cfedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e8bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e8bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e8bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d92cfecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c (1485 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555daf48515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555daf4820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555daf48589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9275449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9275449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9275431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555daf41ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555daf41ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555daf3ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555daf0af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555daf0aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9275432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92754330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555daf0aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c (1486 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564bfb90215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564bfb8ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564bfb90289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb78bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb78bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb78bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb78bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564bfb897e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564bfb897c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564bfb87cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564bfb52c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564bfb52bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb78bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb78bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb78bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564bfb52bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c (1487 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv # | ... # `---data was truncated (10240/75133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e088d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556e088d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556e088d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8130a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8130aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8130a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8130a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e08868e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556e08868c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556e0884db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556e084fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556e084fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8130a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8130a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8130a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e084fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c (1488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604200ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604200aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604200ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007effc5105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007effc515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007effc5105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007effc50ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560420042e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560420042c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560420027b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056041fcd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056041fcd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007effc50eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007effc50ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007effc50ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056041fcd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-3v.c (1489 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-3v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %and.i = and <8 x i16> %2, %3 # | store <8 x i16> %and.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %and.i = and <2 x i32> %2, %3 # | store <2 x i32> %and.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %and.i = and <4 x i32> %2, %3 # | store <4 x i32> %and.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %and.i = and <1 x i64> %2, %3 # | store <1 x i64> %and.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %a.addr = alloca <2 x i64>, align 16 # | %b.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | store <2 x i64> %b, ptr %b.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = load <2 x i64>, ptr %b.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %and.i = and <2 x i64> %2, %3 # | store <2 x i64> %and.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %and.i = and <8 x i8> %2, %3 # | store <8 x i8> %and.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | %b.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | store <16 x i8> %b, ptr %b.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | %1 = load <16 x i8>, ptr %b.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %and.i = and <16 x i8> %2, %3 # | store <16 x i8> %and.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %and.i = and <4 x i16> %2, %3 # | store <4 x i16> %and.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, al # | ... # `---data was truncated (10240/70553) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b4801815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b480150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b4801889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f115b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f115b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f115b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f115b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b47fade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b47fadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b47f92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b47c420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b47c41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f115b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f115b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f115b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b47c41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-3v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c (1490 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c5f1c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555c5f1c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555c5f1c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a05533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a05533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c5f15be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555c5f15bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555c5f140b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555c5edf00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555c5edefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a0551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c5edefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c (1491 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -O2 -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_s64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_u64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f32() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_f64() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_mf8() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) # | define dso_local { , , , } @test_svundef4_bf16() local_unnamed_addr #0 { # | entry: # | ret { , , , } undef # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | !llvm.errno.tbaa = !{!4} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{!5, !6, i64 0} # | !5 = !{!"__libc_errno", !6, i64 0} # | !6 = !{!"int", !7, i64 0} # | !7 = !{!"omnipotent char", !8, i64 0} # | !8 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000055c9ee52015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9ee51d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9ee52089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5db5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5db518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5db5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5db511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9ee4b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9ee4b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9ee49ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9ee14a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9ee149dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5db511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5db511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5db511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9ee149cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c (1492 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c (1493 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfms_f16(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <4 x half>, align 8 # | %__p1.addr.i2 = alloca <4 x half>, align 8 # | %__p2.addr.i3 = alloca <4 x half>, align 8 # | %__ret.i4 = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store <4 x half> %c, ptr %c.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %fneg.i = fneg <4 x half> %4 # | %5 = load <4 x half>, ptr %__p2.addr.i, align 8 # | store <4 x half> %3, ptr %__p0.addr.i1, align 8 # | store <4 x half> %fneg.i, ptr %__p1.addr.i2, align 8 # | store <4 x half> %5, ptr %__p2.addr.i3, align 8 # | %6 = load <8 x i8>, ptr %__p0.addr.i1, align 8 # | %7 = load <8 x i8>, ptr %__p1.addr.i2, align 8 # | %8 = load <8 x i8>, ptr %__p2.addr.i3, align 8 # | %9 = bitcast <8 x i8> %6 to <4 x half> # | %10 = bitcast <8 x i8> %7 to <4 x half> # | %11 = bitcast <8 x i8> %8 to <4 x half> # | %12 = call <4 x half> @llvm.fma.v4f16(<4 x half> %10, <4 x half> %11, <4 x half> %9) # | store <4 x half> %12, ptr %ref.tmp.i, align 8 # | %13 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %13, ptr %__ret.i4, align 8 # | %14 = load <4 x half>, ptr %__ret.i4, align 8 # | store <4 x half> %14, ptr %__ret.i, align 8 # | %15 = load <4 x half>, ptr %__ret.i, align 8 # | ret <4 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %__p0.addr.i1 = alloca <8 x half>, align 16 # | %__p1.addr.i2 = alloca <8 x half>, align 16 # | %__p2.addr.i3 = alloca <8 x half>, align 16 # | %__ret.i4 = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store <8 x half> %c, ptr %c.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <8 x half>, ptr %__p0.addr.i, align 16 # | %4 = load <8 x half>, ptr %__p1.addr.i, align 16 # | %fneg.i = fneg <8 x half> %4 # | %5 = load <8 x half>, ptr %__p2.addr.i, align 16 # | store <8 x half> %3, ptr %__p0.addr.i1, align 16 # | store <8 x half> %fneg.i, ptr %__p1.addr.i2, align 16 # | store <8 x half> %5, ptr %__p2.addr.i3, align 16 # | %6 = load <16 x i8>, ptr %__p0.addr.i1, align 16 # | %7 = load <16 x i8>, ptr %__p1.addr.i2, align 16 # | %8 = load <16 x i8>, ptr %__p2.addr.i3, align 16 # | %9 = bitcast <16 x i8> %6 to <8 x half> # | %10 = bitcast <16 x i8> %7 to <8 x half> # | %11 = bitcast <16 x i8> %8 to <8 x half> # | %12 = call <8 x half> @llvm.fma.v8f16(<8 x half> %10, <8 x half> %11, <8 x half> %9) # | store <8 x half> %12, ptr %ref.tmp.i, align 16 # | %13 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %13, ptr %__ret.i4, align 16 # | %14 = load <8 x half>, ptr %__ret.i4, align 16 # | store <8 x half> %14, ptr %__ret.i, align 16 # | %15 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %15 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vfma_n_f16(<4 x half> noundef %a, <4 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <4 x half>, ptr %__s0, align 8 # | %4 = load <4 x half>, ptr %__s1, align 8 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <4 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %8, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %9 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %3, ptr %__p0.addr.i, align 8 # | store <4 x half> %4, ptr %__p1.addr.i, align 8 # | store <4 x half> %9, ptr %__p2.addr.i, align 8 # | %10 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %13 = bitcast <8 x i8> %10 to <4 x half> # | %14 = bitcast <8 x i8> %11 to <4 x half> # | %15 = bitcast <8 x i8> %12 to <4 x half> # | %16 = call <4 x half> @llvm.fma.v4f16(<4 x half> %14, <4 x half> %15, <4 x half> %13) # | store <4 x half> %16, ptr %ref.tmp.i, align 8 # | %17 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %17, ptr %__ret.i, align 8 # | %18 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %18, ptr %__ret, align 8 # | %19 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %19, ptr %tmp, align 8 # | %20 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %20 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | store half %c, ptr %c.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load <8 x half>, ptr %__s0, align 16 # | %4 = load <8 x half>, ptr %__s1, align 16 # | %5 = load half, ptr %__s2, align 2 # | %vecinit = insertelement <8 x half> poison, half %5, i32 0 # | %6 = load half, ptr %__s2, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %6, i32 1 # | %7 = load half, ptr %__s2, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %7, i32 2 # | %8 = load half, ptr %__s2, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %8, i32 3 # | %9 = load half, ptr %__s2, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %9, i32 4 # | %10 = load half, ptr %__s2, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %10, i32 5 # | %11 = load half, ptr %__s2, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %11, i32 6 # | %12 = load half, ptr %__s2, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %12, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %13 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %3, ptr %__p0.addr.i, align 16 # | store <8 x half> %4, ptr %__p1.addr.i, align 16 # | store <8 x half> %13, ptr %__p2.addr.i, align 16 # | %14 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %15 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %16 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %17 = bitcast <16 x i8> %14 to <8 x half> # | %18 = bitcast <16 x i8> %15 to <8 x half> # | %19 = bitcast <16 x i8> %16 to <8 x half> # | %20 = call <8 x half> @llvm.fma.v8f16(<8 x half> %18, <8 x half> %19, <8 x half> %17) # | store <8 x half> %20, ptr %ref.tmp.i, align 16 # | %21 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %21, ptr %__ret.i, align 16 # | %22 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %22, ptr %__ret, align 16 # | %23 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %23, ptr %tmp, align 16 # | %24 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half # | ... # `---data was truncated (10240/31903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055d9e4f1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9e4f160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9e4f1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7dc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7dc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7dc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7dc031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9e4eaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9e4eaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9e4e93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9e4b430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9e4b42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd7dc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7dc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7dc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9e4b42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c (1494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f73a09315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f73a0900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f73a09389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faab5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faab578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faab5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faab571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f73a028e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f73a028c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f73a00db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f739cbd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f739cbcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faab571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faab571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faab571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f739cbccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c (1495 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560da6f7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560da6f6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560da6f7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2e4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2e438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2e4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2e431b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560da6f06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560da6f06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560da6eebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560da6b9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560da6b9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff2e431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2e431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2e431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560da6b9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c (1496 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e874b415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e874b10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e874b489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cc9e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cc9ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cc9e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cc9e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e87449e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e87449c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e8742eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e870de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e870dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4cc9e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cc9e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cc9e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e870ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c (1497 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 # | ... # `---data was truncated (10240/32570) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65cad515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f65cad20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f65cad589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f29533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f2958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f29533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f2951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65ca6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f65ca6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f65ca4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f65c6ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f65c6fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f2951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f2951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f2951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65c6fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c (1498 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.viota.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota # | ... # `---data was truncated (10240/94681) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fff38915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559fff3860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559fff38989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5083133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f508318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5083133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f508311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fff31ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559fff31ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559fff303b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559ffefb30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559ffefb2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f508311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f508311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f508311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559ffefb2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c (1499 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = a # | ... # `---data was truncated (10240/288050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056304e8ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056304e8c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056304e8ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c61c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c61ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c61c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c61c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056304e85fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056304e85fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056304e844b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056304e4f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056304e4f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c61c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c61c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c61c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056304e4f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c (1500 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/95081) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b04e2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b04e260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b04e2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae8761bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae876725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae8761ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae87603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b04dbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b04dbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b04da3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b04a530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b04a52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae87604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae876050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae876050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b04a52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c (1501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c (1502 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1cda7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1cda7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1cda7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b05f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b05f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b05f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b05f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1cda14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1cda14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1cd9f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1cd6a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1cd6a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3b05f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b05f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b05f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1cd6a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c (1503 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad0550015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ad054fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ad0550089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f52c0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f52c018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f52c0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f52c011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad05495e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ad05495c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ad0547ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ad0512a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ad05129dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f52c011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f52c011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f52c011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad05129cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c (1504 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c (1505 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b3d6d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b3d6d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b3d6d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb13bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb13bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb13bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb13bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b3d66be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b3d66bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b3d650b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b3d3000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b3d2ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb13bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb13bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb13bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b3d2ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-fma.c (1506 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-fma.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a7 -mfloat-abi hard -ffreestanding -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-none-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %accum.addr = alloca <2 x float>, align 8 # | %lhs.addr = alloca <2 x float>, align 8 # | %rhs.addr = alloca <2 x float>, align 8 # | store <2 x float> %accum, ptr %accum.addr, align 8 # | store <2 x float> %lhs, ptr %lhs.addr, align 8 # | store <2 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <2 x float>, ptr %accum.addr, align 8 # | %1 = load <2 x float>, ptr %lhs.addr, align 8 # | %2 = load <2 x float>, ptr %rhs.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store <2 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <8 x i8> %3 to <2 x float> # | %7 = bitcast <8 x i8> %4 to <2 x float> # | %8 = bitcast <8 x i8> %5 to <2 x float> # | %9 = call <2 x float> @llvm.fma.v2f32(<2 x float> %7, <2 x float> %8, <2 x float> %6) # | store <2 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %10, ptr %__ret.i, align 8 # | %11 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %accum.addr = alloca <4 x float>, align 8 # | %lhs.addr = alloca <4 x float>, align 8 # | %rhs.addr = alloca <4 x float>, align 8 # | store <4 x float> %accum, ptr %accum.addr, align 8 # | store <4 x float> %lhs, ptr %lhs.addr, align 8 # | store <4 x float> %rhs, ptr %rhs.addr, align 8 # | %0 = load <4 x float>, ptr %accum.addr, align 8 # | %1 = load <4 x float>, ptr %lhs.addr, align 8 # | %2 = load <4 x float>, ptr %rhs.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store <4 x float> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %6 = bitcast <16 x i8> %3 to <4 x float> # | %7 = bitcast <16 x i8> %4 to <4 x float> # | %8 = bitcast <16 x i8> %5 to <4 x float> # | %9 = call <4 x float> @llvm.fma.v4f32(<4 x float> %7, <4 x float> %8, <4 x float> %6) # | store <4 x float> %9, ptr %ref.tmp.i, align 8 # | %10 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %10, ptr %__ret.i, align 8 # | %11 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <2 x float>, align 8 # | %__p1.addr.i.i = alloca <2 x float>, align 8 # | %__p2.addr.i.i = alloca <2 x float>, align 8 # | %__ret.i.i = alloca <2 x float>, align 8 # | %ref.tmp.i.i = alloca <8 x i8>, align 8 # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <2 x float>, align 8 # | %.compoundliteral.i = alloca <2 x float>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <2 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <2 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <2 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <2 x float> %vecinit.i, float %6, i32 1 # | store <2 x float> %vecinit1.i, ptr %.compoundliteral.i, align 8 # | %7 = load <2 x float>, ptr %.compoundliteral.i, align 8 # | store <2 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <2 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <2 x float> %7, ptr %__p2.addr.i.i, align 8 # | %8 = load <8 x i8>, ptr %__p0.addr.i.i, align 8 # | %9 = load <8 x i8>, ptr %__p1.addr.i.i, align 8 # | %10 = load <8 x i8>, ptr %__p2.addr.i.i, align 8 # | %11 = bitcast <8 x i8> %8 to <2 x float> # | %12 = bitcast <8 x i8> %9 to <2 x float> # | %13 = bitcast <8 x i8> %10 to <2 x float> # | %14 = call <2 x float> @llvm.fma.v2f32(<2 x float> %12, <2 x float> %13, <2 x float> %11) # | store <2 x float> %14, ptr %ref.tmp.i.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i.i, align 8 # | store <2 x float> %15, ptr %__ret.i.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i.i, align 8 # | store <2 x float> %16, ptr %__ret.i, align 8 # | %17 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #0 { # | entry: # | %__p0.addr.i.i = alloca <4 x float>, align 8 # | %__p1.addr.i.i = alloca <4 x float>, align 8 # | %__p2.addr.i.i = alloca <4 x float>, align 8 # | %__ret.i.i = alloca <4 x float>, align 8 # | %ref.tmp.i.i = alloca <16 x i8>, align 8 # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__p2.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 8 # | %.compoundliteral.i = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %n.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %n, ptr %n.addr, align 4 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load float, ptr %n.addr, align 4 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | store float %2, ptr %__p2.addr.i, align 4 # | %3 = load <4 x float>, ptr %__p0.addr.i, align 8 # | %4 = load <4 x float>, ptr %__p1.addr.i, align 8 # | %5 = load float, ptr %__p2.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %5, i32 0 # | %6 = load float, ptr %__p2.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %6, i32 1 # | %7 = load float, ptr %__p2.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %7, i32 2 # | %8 = load float, ptr %__p2.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %8, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 8 # | %9 = load <4 x float>, ptr %.compoundliteral.i, align 8 # | store <4 x float> %3, ptr %__p0.addr.i.i, align 8 # | store <4 x float> %4, ptr %__p1.addr.i.i, align 8 # | store <4 x float> %9, ptr %__p2.addr.i.i, align 8 # | %10 = load <16 x i8>, ptr %__p0.addr.i.i, align 8 # | %11 = load <16 x i8>, ptr %__p1.addr.i.i, align 8 # | %12 = load <16 x i8>, ptr %__p2.addr.i.i, align 8 # | %13 = bitcast <16 x i8> %10 to <4 x float> # | %14 = bitcast <16 x i8> %11 to <4 x float> # | %15 = bitcast <16 x i8> %12 to <4 x float> # | %16 = call <4 x float> @llvm.fma.v4f32(<4 x float> %14, <4 x float> %15, <4 x float> %13) # | store <4 x float> %16, ptr %ref.tmp.i.i, align 8 # | %17 = load <4 x float>, ptr %ref.tmp.i.i, align 8 # | store <4 x float> %17, ptr %__ret.i.i, align 8 # | %18 = load <4 x float>, ptr %__ret.i.i, align 8 # | store <4 x float> %18, ptr %__ret.i, align 8 # | %19 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %19 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a7" "target-features"="+armv7-a,+d32,+dsp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ba44a4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba44a400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba44a4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4a8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4a8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4a8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4a8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba449d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba449d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba449bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba4466d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba4466cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4a8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4a8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4a8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba4466ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-fma.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c (1507 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055896346a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005589634670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055896346a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1f4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1f458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1f4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1f451b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589633ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005589633ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005589633e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589630940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558963093dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1f451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1f451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1f451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558963093cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c (1508 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b607f7715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b607f740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b607f7789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cc7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cc778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cc7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cc771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b607f0ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b607f0cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b607ef1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b607ba10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b607ba0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4cc771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cc771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cc771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b607ba0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c (1509 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056367dc9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056367dc9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056367dc9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe56be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe56bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe56be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe56be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056367dc34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056367dc34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056367dc19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056367d8c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056367d8c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe56be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe56be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe56be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056367d8c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c (1510 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c (1511 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredosum_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | # | ... # `---data was truncated (10240/81304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d26d68515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d26d6820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d26d68589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc244649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2446a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc244649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc244631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d26d61ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d26d61ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d26d5ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d26d2af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d26d2aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc244632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2446330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2446330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d26d2aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c (1512 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c (1513 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf8( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf4( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8mf2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m1( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vx_u8m2( %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabd_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64 # | ... # `---data was truncated (10240/97248) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7ef22e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7ef22b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7ef22e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f465981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46598725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f465981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4659803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7ef1c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b7ef1c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b7ef1a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7eee580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b7eee57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4659804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46598050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46598050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7eee57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c (1514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ec2ddc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ec2dd90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ec2ddc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3799333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f379938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3799333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f379931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ec2d71e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ec2d71c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ec2d56b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564ec2a060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564ec2a05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f379931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f379931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f379931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ec2a05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c (1515 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <1 x double> %c, ptr %c.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %c.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2, align 8 # | %extract = extractelement <1 x double> %5, i32 0 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare double @llvm.fma.f64(double, double, double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca double, align 8 # | %c.addr = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca double, align 8 # | %__s1 = alloca double, align 8 # | %__s2 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | store <2 x double> %c, ptr %c.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store double %1, ptr %__s1, align 8 # | %2 = load <2 x double>, ptr %c.addr, align 16 # | store <2 x double> %2, ptr %__s2, align 16 # | %3 = load double, ptr %__s0, align 8 # | %4 = load double, ptr %__s1, align 8 # | %5 = load <2 x double>, ptr %__s2, align 16 # | %extract = extractelement <2 x double> %5, i32 1 # | %6 = call double @llvm.fma.f64(double %4, double %extract, double %3) # | store double %6, ptr %ref.tmp, align 8 # | %7 = load double, ptr %ref.tmp, align 8 # | store double %7, ptr %__ret, align 8 # | %8 = load double, ptr %__ret, align 8 # | store double %8, ptr %tmp, align 8 # | %9 = load double, ptr %tmp, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca float, align 4 # | %c.addr = alloca <2 x float>, align 8 # | %__ret_443 = alloca float, align 4 # | %__s0_443 = alloca float, align 4 # | %__s1_443 = alloca float, align 4 # | %__s2_443 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca float, align 4 # | %__s1 = alloca float, align 4 # | %__s2 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store float %b, ptr %b.addr, align 4 # | store <2 x float> %c, ptr %c.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_443, align 4 # | %1 = load float, ptr %b.addr, align 4 # | store float %1, ptr %__s1_443, align 4 # | %2 = load <2 x float>, ptr %c.addr, align 8 # | store <2 x float> %2, ptr %__s2_443, align 8 # | %3 = load float, ptr %__s0_443, align 4 # | store float %3, ptr %__s0, align 4 # | %4 = load float, ptr %__s1_443, align 4 # | %fneg = fneg float %4 # | store float %fneg, ptr %__s1, align 4 # | %5 = load <2 x float>, ptr %__s2_443, align 8 # | store <2 x float> %5, ptr %__s2, align 8 # | %6 = load float, ptr %__s0, align 4 # | %7 = load float, ptr %__s1, align 4 # | %8 = load <2 x float>, ptr %__s2, align 8 # | %extract = extractelement <2 x float> %8, i32 1 # | %9 = call float @llvm.fma.f32(float %7, float %extract, float %6) # | store float %9, ptr %ref.tmp, align 4 # | %10 = load float, ptr %ref.tmp, align 4 # | store float %10, ptr %__ret, align 4 # | %11 = load float, ptr %__ret, align 4 # | store float %11, ptr %tmp, align 4 # | %12 = load float, ptr %tmp, align 4 # | store float %12, ptr %__ret_443, align 4 # | %13 = load float, ptr %__ret_443, align 4 # | store float %13, ptr %tmp1, align 4 # | %14 = load float, ptr %tmp1, align 4 # | ret float %14 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.fma.f32(float, float, float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <1 x double> # | %lane = shufflevector <1 x double> %6, <1 x double> %6, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %4 to <1 x double> # | %fmla1 = bitcast <8 x i8> %3 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %7 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %7, ptr %__ret, align 8 # | %8 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %8, ptr %tmp, align 8 # | %9 = load <1 x double>, ptr %tmp, align 8 # | ret <1 x double> %9 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <1 x double>, align 8 # | %__ret_449 = alloca <1 x double>, align 8 # | %__s0_449 = alloca <1 x double>, align 8 # | %__s1_449 = alloca <1 x double>, align 8 # | %__s2_449 = alloca <1 x double>, align 8 # | %__ret = alloca <1 x double>, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %__s1 = alloca <1 x double>, align 8 # | %__s2 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <1 x double>, align 8 # | %tmp3 = alloca <1 x double>, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | store <1 x double> %v, ptr %v.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | store <1 x double> %0, ptr %__s0_449, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_449, align 8 # | %2 = load <1 x double>, ptr %v.addr, align 8 # | store <1 x double> %2, ptr %__s2_449, align 8 # | %3 = load <1 x double>, ptr %__s0_449, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s1_449, align 8 # | %fneg = fneg <1 x double> %4 # | store <1 x double> %fneg, ptr %__s1, align 8 # | %5 = load <1 x double>, ptr %__s2_449, align 8 # | store <1 x double> %5, ptr %__s2, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = load <8 x i8>, ptr %__s1, align 8 # | %8 = load <8 x i8>, ptr %__s2, align 8 # | %9 = bitcast <8 x i8> %8 to <1 x double> # | %lane = shufflevector <1 x double> %9, <1 x double> %9, <1 x i32> zeroinitializer # | %fmla = bitcast <8 x i8> %7 to <1 x double> # | %fmla1 = bitcast <8 x i8> %6 to <1 x double> # | %fmla2 = call <1 x double> @llvm.fma.v1f64(<1 x double> %fmla, <1 x double> %lane, <1 x double> %fmla1) # | store <1 x double> %fmla2, ptr %ref.tmp, align 8 # | %10 = load <1 x double>, ptr %ref.tmp, align 8 # | store <1 x double> %10, ptr %__ret, align 8 # | %11 = load <1 x double>, ptr %__ret, align 8 # | store <1 x double> %11, ptr %tmp, align 8 # | %12 = load <1 x double>, ptr %tmp, align 8 # | store <1 x double> %12, ptr %__ret_449, align 8 # | %13 = load <1 x double>, ptr %__ret_449, align 8 # | store <1 x double> %13, ptr %tmp3, align 8 # | %14 = load <1 x double>, ptr %tmp3, align 8 # | ret <1 x double> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #0 { # | entry: # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %v.addr = alloca <2 x double>, align 16 # | %__ret_460 = alloca <1 x double>, align 8 # | %__s0_460 = alloca <1 x double>, align 8 # | %__s1_460 = alloca <1 x double>, align 8 # | %__s2_460 = alloca <2 x double>, align 16 # | %__ret = alloca <1 x double>, align 8 # | %_ # | ... # `---data was truncated (10240/12799) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055e62396315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6239600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e62396389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd5d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd5d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd5d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd5d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6238f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6238f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6238ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e62358d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e62358cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd5d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd5d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd5d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62358ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c (1516 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vminu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a7688515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a768820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a7688589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9ffa61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9ffa6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9ffa61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9ffa603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a7681ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a7681ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a767ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a764af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a764aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9ffa604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9ffa6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9ffa6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a764aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c (1517 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f74f05315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f74f0500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f74f05389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbe1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbe158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbe1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbe151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f74efe8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f74efe8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f74efcdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f74ec7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f74ec7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcbe151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbe151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbe151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f74ec7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c (1518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"Sma # | ... # `---data was truncated (10240/10293) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055885fe5315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055885fe500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055885fe5389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2520e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2520ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2520e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2520e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055885fde8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055885fde8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055885fdcdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055885fa7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055885fa7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2520e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2520e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2520e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055885fa7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c (1519 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgtu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d12abd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d12aba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d12abd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0f4505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0f455c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0f4505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0f44ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d12a52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d12a52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d12a37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d126e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d126e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb0f44eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0f44ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0f44ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d126e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c (1520 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641604c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641604c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641604c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc08e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc08ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc08e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc08e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056416045ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056416045cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564160441b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641600f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641600f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc08e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc08e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc08e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641600f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c (1521 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df802fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df802f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df802fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd1ccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd1ccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd1ccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd1ccb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df80290e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df80290c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df80275b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df7ff250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df7ff24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd1ccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd1ccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd1ccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df7ff24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c (1522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrol.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056522433215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056522432f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056522433289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe680305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe68035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe680305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6802ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652242c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005652242c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005652242acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565223f5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565223f5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe6802eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6802ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6802ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565223f5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c (1523 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv4bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.mask.nxv8bf16.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, ali # | ... # `---data was truncated (10240/12688) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1393a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e13939e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e1393a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0d1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0d14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0d1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0d1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e139336e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e139336c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e13931bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e138fcb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e138fcadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc0d1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0d14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0d14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e138fcacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c (1524 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c (1525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9b777915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9b77760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9b777989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd15533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd1558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd15533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd1551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9b770ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9b770ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9b76f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9b73a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9b73a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd1551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd1551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd1551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9b73a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c (1526 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055718e61e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055718e61b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055718e61e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3721733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f372178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3721733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f372171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055718e5b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055718e5b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055718e598b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055718e2480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055718e247dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f372171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f372171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f372171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055718e247cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c (1527 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c (1528 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056453444715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645344440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056453444789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5496849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5496849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5496831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645343dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645343dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645343c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645340710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564534070dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5496832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564534070cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c (1529 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056360c03c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056360c0390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056360c03c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f992c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f992c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f992c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f992c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056360bfd1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056360bfd1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056360bfb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056360bc660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056360bc65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f992c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f992c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f992c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056360bc65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c (1530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c76497415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7649710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c76497489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0a3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0a3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0a3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0a3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c764909e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c764909c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c7648eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c76459e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c76459ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc0a3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0a3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0a3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c76459dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c (1531 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c (1532 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulr_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulr.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulr.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbc,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbc1p0_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056420781915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005642078160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056420781989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f3b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f3b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f3b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f3b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642077aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005642077aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564207793b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005642074430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564207442dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f3b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f3b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f3b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564207442cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbc.c -check-prefix=RV32ZBC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c (1533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff. # | ... # `---data was truncated (10240/78156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636b8c1115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005636b8c0e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005636b8c1189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e3f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e3f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e3f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e3f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636b8ba6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005636b8ba6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005636b8b8bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636b883b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005636b883add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e3f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e3f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e3f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636b883acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c (1534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cd87c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561cd87c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561cd87c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dd0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dd08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dd0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dd0831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cd875ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561cd875ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561cd873fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561cd83ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561cd83eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2dd0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dd08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dd08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cd83eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (1535 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.ris # | ... # `---data was truncated (10240/12914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0d322715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b0d32240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b0d322789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9deef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9deef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9deef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9deef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b0d31bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b0d31bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b0d31a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b0d2e510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b0d2e50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9deef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9deef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9deef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b0d2e50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c (1536 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea4b14415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea4b1410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea4b14489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc93a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc93a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc93a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc93a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea4b0d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea4b0d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea4b0beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea4ad6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea4ad6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc93a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc93a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc93a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea4ad6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c (1537 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580791f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580791f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580791f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efce5305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efce535c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efce5305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efce52ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055807918ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055807918cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558079171b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558078e210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558078e20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efce52eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efce52ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efce52ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558078e20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c (1538 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d196f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d196ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d196f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f671c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f671c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f671c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f671c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d19686e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d19686c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d1966bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d1931b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d1931add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f671c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f671c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f671c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d1931acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c (1539 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055977946f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055977946c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055977946f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2813733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f281378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2813733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f281371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559779404e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559779404c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597793e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597790990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559779098dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f281371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f281371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f281371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559779098cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c (1540 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | # | ... # `---data was truncated (10240/12216) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564ed484b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564ed48480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564ed484b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ca2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ca238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ca2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ca231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564ed47e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564ed47e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564ed47c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564ed44750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564ed4474dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ca231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ca231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ca231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564ed4474cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c (1541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e07a9ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e07a9fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e07a9ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd183a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd183aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd183a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd183a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e07a994e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e07a994c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e07a979b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e07a6290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e07a628dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd183a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd183a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd183a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e07a628cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c (1542 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a491f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a491f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a491f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efda9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efda9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efda9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efda9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a4918ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a4918ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a4916fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a48e1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a48e1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efda9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efda9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efda9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a48e1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c (1543 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc89b8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc89b870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc89b8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4120c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4120ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4120c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4120c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc89b1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc89b1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc89b04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc897b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc897b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4120c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4120c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4120c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc897b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c (1544 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e95941815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9594150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e95941889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7208133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f720818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7208133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f720811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9593ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9593adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e959392b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9590420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e959041dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f720811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f720811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f720811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e959041cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c (1545 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i8 @subscript_int8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i8 @subscript_uint8( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <32 x i8> %0, i64 %1 # | ret i8 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i16 @subscript_int16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local zeroext i16 @subscript_uint16( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <16 x i16> %0, i64 %1 # | ret i16 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_int32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local signext i32 @subscript_uint32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x i32> %0, i64 %1 # | ret i32 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_int64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local i64 @subscript_uint64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x i64> %0, i64 %1 # | ret i64 %vecext # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local float @subscript_float32( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <8 x float> %0, i64 %1 # | ret float %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x float> @llvm.vector.extract.v8f32.nxv2f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local double @subscript_float64( noundef %a.coerce, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x double>, align 8 # | %b.addr = alloca i64, align 8 # | %a = call <4 x double> @llvm.vector.extract.v4f64.nxv1f64( %a.coerce, i64 0) # | store <4 x double> %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load <4 x double>, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %vecext = extractelement <4 x double> %0, i64 %1 # | ret double %vecext # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x double> @llvm.vector.extract.v4f64.nxv1f64(, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,4) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000555cea5f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555cea5f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555cea5f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f281e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f281e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f281e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f281e231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cea58be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555cea58bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555cea570b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555cea2200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555cea21fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f281e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f281e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f281e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cea21fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-subscript-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c (1546 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c (1547 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5ad81e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5ad81b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5ad81e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf6a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf6a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf6a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf6a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5ad7b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5ad7b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5ad798b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5ad4480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5ad447dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbf6a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf6a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf6a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5ad447cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c (1548 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea5687d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea5687a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea5687d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb196f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb196f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb196f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb196f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea56812e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea56812c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea567f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea564a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea564a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb196f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb196f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb196f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea564a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c (1549 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c (1550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c (1551 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/284336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f511ede15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f511edb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f511ede89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3376533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f337658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3376533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f337651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f511e73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f511e73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f511e58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f511b080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f511b07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f337651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f337651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f337651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f511b07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c (1552 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32, i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32, i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcaddq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcaddq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcaddq_rot90_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align # | ... # `---data was truncated (10240/39627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f210d6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f210d690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f210d6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c87d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c87d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c87d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c87d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f210d01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f210d01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f210ce6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f2109960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f210995dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c87d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c87d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c87d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f210995cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c (1553 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/ternary.c (1554 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/ternary.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %1, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %1, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmaq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load <8 x half>, ptr %a.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %.splat, <8 x half> %2) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load <4 x float>, ptr %a.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %.splat, <4 x float> %2) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmasq_n_f16(<8 x half> noundef %a, <8 x half> noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fma.v8f16(<8 x half> %1, <8 x half> %2, <8 x half> %.splat) # | ret <8 x half> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmasq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca float, align 4 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store float %c, ptr %c.addr, align 4 # | %0 = load float, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fma.v4f32(<4 x float> %1, <4 x float> %2, <4 x float> %.splat) # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> noundef %a, <8 x half> noundef %b, <8 x half> noundef %c) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %c.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store <8 x half> %c, ptr %c.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load <8 x half>, ptr %c.addr, align 8 # | %2 = fneg <8 x half> %1 # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = call <8 x half> @llvm.fma.v8f16(<8 x half> %0, <8 x half> %2, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %c.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store <4 x float> %c, ptr %c.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load <4 x float>, ptr %c.addr, align 8 # | %2 = fneg <4 x float> %1 # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %2, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef signext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %c, ptr %c.addr, align 2 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %c.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = mul <8 x i16> %0, %.splat # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = add <8 x i16> %2, %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmlaq_n_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i32 noundef %c) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i32 %c, ptr %c.addr, align 4 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %c.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = mul <4 x i32> %0, %.splat # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = add <4 x i32> %2, %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmlaq_n_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i8 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i8 %c, ptr %c.addr, align 1 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %c.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = mul <16 x i8> %0, %.splat # | %3 = load <16 x i8>, ptr %a.addr, align 8 # | %4 = add <16 x i8> %2, %3 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmlaq_n_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %c) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, ali # | ... # `---data was truncated (10240/60411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055722c7c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055722c7c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055722c7c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cfb049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cfb0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cfb049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cfb031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055722c75ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055722c75ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055722c743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055722c3f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055722c3f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6cfb032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cfb0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cfb0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055722c3f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c (1555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cc62cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557cc62cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557cc62cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0bf1105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0bf115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0bf1105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0bf10ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cc6264e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557cc6264c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557cc6249b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557cc5ef90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557cc5ef8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0bf10eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0bf10ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0bf10ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cc5ef8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c (1556 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597e572115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597e571e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597e572189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8196f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8196f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8196f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8196f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597e56b6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597e56b6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597e569bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597e534b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597e534add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8196f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8196f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8196f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597e534acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c (1557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c (1558 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563075b4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563075b450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563075b4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f20aa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f20aa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f20aa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f20aa403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563075adde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563075addc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563075ac2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005630757720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563075771dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f20aa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f20aa4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f20aa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563075771cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c (1559 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c (1560 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff50af615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff50af30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff50af689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67bf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67bf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67bf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67bf11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff50a8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff50a8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff50a70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff507200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff5071fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f67bf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67bf11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67bf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff5071fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c (1561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562b607e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005562b607b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005562b607e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97e6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97e6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97e6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97e6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562b6013e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005562b6013c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005562b5ff8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005562b5ca80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005562b5ca7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97e6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97e6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97e6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562b5ca7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c (1562 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32bf16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c (1563 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %bas # | ... # `---data was truncated (10240/20340) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567ec47c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567ec4790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567ec47c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe902849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9028a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe902849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe902831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567ec411e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567ec411c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567ec3f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567ec0a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005567ec0a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe902832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9028330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9028330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567ec0a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c (1564 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567d6c0615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567d6c030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567d6c0689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a3a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a3a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a3a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a3a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567d6b9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567d6b9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567d6b80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567d68300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005567d682fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a3a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a3a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a3a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567d682fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-cast.c (1565 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-cast.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_s8(<8 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_s8_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | ret <8 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_s8_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_f8_f32(<2 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <2 x float>, align 8 # | store <2 x float> %x, ptr %x.addr, align 8 # | %0 = load <2 x float>, ptr %x.addr, align 8 # | %1 = bitcast <2 x float> %0 to <8 x i8> # | ret <8 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_f32_f8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <8 x i8> %0 to <2 x float> # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_f32(<4 x float> noundef %x) #0 { # | entry: # | %x.addr = alloca <4 x float>, align 16 # | store <4 x float> %x, ptr %x.addr, align 16 # | %0 = load <4 x float>, ptr %x.addr, align 16 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @testq_f32_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @testq_f8_p128(i128 noundef %x) #0 { # | entry: # | %x.addr = alloca i128, align 16 # | store i128 %x, ptr %x.addr, align 16 # | %0 = load i128, ptr %x.addr, align 16 # | %1 = bitcast i128 %0 to <16 x i8> # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @testq_p128_f8(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = bitcast <16 x i8> %0 to i128 # | ret i128 %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg # | #0 0x000055cd3cc1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd3cc120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd3cc1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7a671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd3cbaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd3cbaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd3cb8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd3c83f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd3c83edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa7a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7a671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd3c83ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-cast.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c (1566 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, ha # | ... # `---data was truncated (10240/125649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624f2ce915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624f2ce60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624f2ce989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9893f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9893f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9893f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9893f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624f2c7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624f2c7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624f2c63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624f29130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624f2912dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9893f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9893f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9893f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624f2912cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c (1567 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f32.p0.nxv16i32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c (1568 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.a # | ... # `---data was truncated (10240/41678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652fe7e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005652fe7de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005652fe7e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f939da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f939daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f939da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f939da31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652fe776e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005652fe776c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005652fe75bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005652fe40b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005652fe40add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f939da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f939da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f939da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652fe40acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c (1569 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647b643415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005647b64310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005647b643489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6862133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f686218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6862133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f686211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647b63c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005647b63c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005647b63aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005647b605e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005647b605ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f686211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f686211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f686211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647b605dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c (1570 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d9e00c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d9e0090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d9e00c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e6a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e6a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e6a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e6a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d9dfa1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d9dfa1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d9df86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d9dc360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d9dc35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e6a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e6a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e6a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d9dc35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c (1571 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align # | ... # `---data was truncated (10240/43617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d784b9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d784b8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d784b9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0eb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0eb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0eb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0eb831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d784b26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d784b26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d784b0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7847bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7847badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0eb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0eb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0eb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7847bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c (1572 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fbb1b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555fbb1ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555fbb1b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f7c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f7c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f7c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f7c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fbb146e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555fbb146c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555fbb12bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555fbaddb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555fbaddadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f7c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f7c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f7c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fbaddacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c (1573 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7f395915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7f39560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c7f395989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a8aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a8aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a8aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a8aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7f38eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c7f38eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c7f38d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7f35830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c7f3582dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a8aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a8aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a8aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7f3582cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c (1574 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650f09fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650f09f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650f09fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f177e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f177e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f177e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f177e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650f0990e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650f0990c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650f0975b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650f06250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650f0624dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f177e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f177e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f177e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650f0624cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c (1575 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2095c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e2095bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e2095c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f062cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f062cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f062cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f062ceed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e209557e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e209557c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e20953cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e2091ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e2091ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f062ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f062ceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f062ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2091ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c (1576 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a534f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558a534ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558a534f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd45cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd45cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd45cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd45cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a53487e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558a53487c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558a5346cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558a5311c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558a5311bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd45cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd45cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd45cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a5311bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c (1577 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr # | ... # `---data was truncated (10240/20623) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef3d8b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef3d8ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef3d8b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f451961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45196725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f451961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4519603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef3d846e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef3d846c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef3d82bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef3d4db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef3d4dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4519604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45196050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45196050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef3d4dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c (1578 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp sge <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp uge <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp sge <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a3ea1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558a3ea0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558a3ea1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ff5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ff5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ff5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ff5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a3e9a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558a3e9a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558a3e98ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558a3e63a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558a3e639dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ff5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ff5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ff5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a3e639cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vadc.c (1579 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadciq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vadcq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load ptr, ptr %carry.addr, align 4 # | %4 = load i32, ptr %3, align 4 # | %5 = shl i32 %4, 29 # | %6 = load i16, ptr %p.addr, align 2 # | %7 = zext i16 %6 to i32 # | %8 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %7) # | %9 = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 %5, <4 x i1> %8) # | %10 = extractvalue { <4 x i32>, i32 } %9, 1 # | %11 = lshr i32 %10, 29 # | %12 = and i32 1, %11 # | store i32 %12, ptr %3, align 4 # | %13 = extractvalue { <4 x i32>, i32 } %9, 0 # | ret <4 x i32> %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 536870912) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | %4 = lshr i32 %3, 29 # | %5 = and i32 1, %4 # | %6 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %5, ptr %6, align 4 # | %7 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbcq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry, ptr %carry.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load ptr, ptr %carry.addr, align 4 # | %3 = load i32, ptr %2, align 4 # | %4 = shl i32 %3, 29 # | %5 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> %0, <4 x i32> %1, i32 %4) # | %6 = extractvalue { <4 x i32>, i32 } %5, 1 # | %7 = lshr i32 %6, 29 # | %8 = and i32 1, %7 # | store i32 %8, ptr %2, align 4 # | %9 = extractvalue { <4 x i32>, i32 } %5, 0 # | ret <4 x i32> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsbciq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, ptr noundef %carry_out, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %carry_out.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store ptr %carry_out, ptr %carry_out.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 536870912, <4 x i1> %5) # | %7 = extractvalue { <4 x i32>, i32 } %6, 1 # | %8 = lshr i32 %7, 29 # | %9 = and i32 1, %8 # | %10 = load ptr, ptr %carry_out.addr, align 4 # | store i32 %9, ptr %10, align 4 # | %11 = extractvalue { <4 x i32>, i32 } %6, 0 # | ret <4 x i32> %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, # | ... # `---data was truncated (10240/14775) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625d240215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625d23ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005625d240289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5248533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f524858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5248533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f524851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625d2397e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625d2397c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625d237cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625d202c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625d202bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f524851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f524851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f524851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625d202bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c (1580 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c (1581 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | } # | # | ; Fun # | ... # `---data was truncated (10240/34633) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563626e7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563626e6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563626e7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb0a9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb0a978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb0a9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0a971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563626e05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563626e05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563626deab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563626a9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563626a99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb0a971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0a971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0a971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563626a99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/attr-counted-by-issue200014.c (1582 of 27911) ******************** TEST 'Clang :: CodeGen/attr-counted-by-issue200014.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -O0 -Wno-missing-declarations -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.annotated_flex = type { i64, i8, [0 x i8] } # | # | @gaf = global { i64, i8, [15 x i8] } { i64 10, i8 0, [15 x i8] c"i am very long\00" }, align 8 # | @sink = external global i64, align 8 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_fam(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %2 = ptrtoint ptr %arraydecay to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arraydecay2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 0 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %3 = icmp sgt i64 %flexible_array_member_size, -1 # | %4 = select i1 %3, i64 %flexible_array_member_size, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_subscript(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 2 # | %2 = ptrtoint ptr %arrayidx to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %arrayidx2 = getelementptr inbounds [0 x i8], ptr %fam1, i64 0, i64 2 # | %counted_by.gep = getelementptr inbounds i8, ptr %af, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 2 # | %3 = icmp sgt i64 %result, -1 # | %4 = and i1 true, %3 # | %5 = select i1 %4, i64 %result, i64 0 # | ret i64 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @local_addrof(i64 noundef %n) #0 { # | entry: # | %n.addr = alloca i64, align 8 # | %af = alloca %struct.annotated_flex, align 8 # | store i64 %n, ptr %n.addr, align 8 # | %count = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 0 # | %0 = load i64, ptr %n.addr, align 8 # | store i64 %0, ptr %count, align 8 # | %induce_padding = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 1 # | store i8 0, ptr %induce_padding, align 8 # | %1 = getelementptr i8, ptr %af, i64 9 # | call void @llvm.memset.p0.i64(ptr align 1 %1, i8 0, i64 7, i1 false) # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %2 = ptrtoint ptr %fam to i64 # | store i64 %2, ptr @sink, align 8 # | %fam1 = getelementptr inbounds nuw %struct.annotated_flex, ptr %af, i32 0, i32 2 # | %3 = call i64 @llvm.objectsize.i64.p0(ptr %fam1, i1 false, i1 true, i1 true) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_fam() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %0 = icmp sgt i64 %flexible_array_member_size, -1 # | %1 = select i1 %0, i64 %flexible_array_member_size, i64 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_subscript() #0 { # | entry: # | %counted_by.load = load i64, ptr @gaf, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %0 = icmp sgt i64 %result, -1 # | %1 = and i1 true, %0 # | %2 = select i1 %1, i64 %result, i64 0 # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @global_addrof() #0 { # | entry: # | %0 = call i64 @llvm.objectsize.i64.p0(ptr getelementptr inbounds nuw (i8, ptr @gaf, i64 9), i1 false, i1 true, i1 true) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_fam(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arraydecay = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 0 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %2 = icmp sgt i64 %flexible_array_member_size, -1 # | %3 = select i1 %2, i64 %flexible_array_member_size, i64 0 # | ret i64 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_subscript(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %arrayidx = getelementptr inbounds [0 x i8], ptr %fam, i64 0, i64 3 # | %1 = load ptr, ptr %p.addr, align 8 # | %counted_by.gep = getelementptr inbounds i8, ptr %1, i64 0 # | %counted_by.load = load i64, ptr %counted_by.gep, align 4 # | %flexible_array_member_size = mul nuw i64 %counted_by.load, 1 # | %result = sub nuw i64 %flexible_array_member_size, 3 # | %2 = icmp sgt i64 %result, -1 # | %3 = and i1 true, %2 # | %4 = select i1 %3, i64 %result, i64 0 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @ptr_addrof(ptr noundef %p) #0 { # | entry: # | %p.addr = alloca ptr, align 8 # | store ptr %p, ptr %p.addr, align 8 # | %0 = load ptr, ptr %p.addr, align 8 # | %fam = getelementptr inbounds nuw %struct.annotated_flex, ptr %0, i32 0, i32 2 # | %1 = call i64 @llvm.objectsize.i64.p0(ptr %fam, i1 false, i1 true, i1 true) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fa476cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa476c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa476cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b1a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b1a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b1a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b1a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa47661e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa47661c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa47646b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa472f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa472f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b1a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b1a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b1a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa472f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/attr-counted-by-issue200014.c --check-prefix=FRONTEND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c (1583 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | # | ... # `---data was truncated (10240/19123) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587cfd8215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587cfd7f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587cfd8289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48b6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48b66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48b6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48b6631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587cfd17e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587cfd17c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587cfcfcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587cf9ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587cf9abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48b6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48b66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48b66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587cf9abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c (1584 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfclass.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.mask.nxv16bf16.i64( poison, %1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c (1585 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c (1586 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_571 = alloca float, align 4 # | %__s0_571 = alloca float, align 4 # | %__s1_571 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_571, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_571, align 8 # | %2 = load float, ptr %__s0_571, align 4 # | %3 = load <2 x float>, ptr %__s1_571, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_571, align 4 # | %8 = load float, ptr %__ret_571, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <1 x double>, align 8 # | %__ret_570 = alloca double, align 8 # | %__s0_570 = alloca double, align 8 # | %__s1_570 = alloca <1 x double>, align 8 # | %__ret = alloca double, align 8 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <1 x double> %b, ptr %b.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_570, align 8 # | %1 = load <1 x double>, ptr %b.addr, align 8 # | store <1 x double> %1, ptr %__s1_570, align 8 # | %2 = load double, ptr %__s0_570, align 8 # | %3 = load <1 x double>, ptr %__s1_570, align 8 # | store <1 x double> %3, ptr %__s0, align 8 # | %4 = load <1 x double>, ptr %__s0, align 8 # | %vget_lane = extractelement <1 x double> %4, i32 0 # | store double %vget_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_570, align 8 # | %8 = load double, ptr %__ret_570, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_577 = alloca float, align 4 # | %__s0_577 = alloca float, align 4 # | %__s1_577 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_577, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_577, align 16 # | %2 = load float, ptr %__s0_577, align 4 # | %3 = load <4 x float>, ptr %__s1_577, align 16 # | store <4 x float> %3, ptr %__s0, align 16 # | %4 = load <4 x float>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <4 x float> %4, i32 3 # | store float %vgetq_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | %mul = fmul float %2, %7 # | store float %mul, ptr %__ret_577, align 4 # | %8 = load float, ptr %__ret_577, align 4 # | store float %8, ptr %tmp1, align 4 # | %9 = load float, ptr %tmp1, align 4 # | ret float %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #0 { # | entry: # | %a.addr = alloca double, align 8 # | %b.addr = alloca <2 x double>, align 16 # | %__ret_575 = alloca double, align 8 # | %__s0_575 = alloca double, align 8 # | %__s1_575 = alloca <2 x double>, align 16 # | %__ret = alloca double, align 8 # | %__s0 = alloca <2 x double>, align 16 # | %ref.tmp = alloca double, align 8 # | %tmp = alloca double, align 8 # | %tmp1 = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | store <2 x double> %b, ptr %b.addr, align 16 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__s0_575, align 8 # | %1 = load <2 x double>, ptr %b.addr, align 16 # | store <2 x double> %1, ptr %__s1_575, align 16 # | %2 = load double, ptr %__s0_575, align 8 # | %3 = load <2 x double>, ptr %__s1_575, align 16 # | store <2 x double> %3, ptr %__s0, align 16 # | %4 = load <2 x double>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <2 x double> %4, i32 1 # | store double %vgetq_lane, ptr %ref.tmp, align 8 # | %5 = load double, ptr %ref.tmp, align 8 # | store double %5, ptr %__ret, align 8 # | %6 = load double, ptr %__ret, align 8 # | store double %6, ptr %tmp, align 8 # | %7 = load double, ptr %tmp, align 8 # | %mul = fmul double %2, %7 # | store double %mul, ptr %__ret_575, align 8 # | %8 = load double, ptr %__ret_575, align 8 # | store double %8, ptr %tmp1, align 8 # | %9 = load double, ptr %tmp1, align 8 # | ret double %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x double>, align 8 # | %__p1.addr.i = alloca double, align 8 # | %__ret.i = alloca <1 x double>, align 8 # | %ref.tmp.i = alloca <1 x double>, align 8 # | %a.addr = alloca <1 x double>, align 8 # | %b.addr = alloca double, align 8 # | store <1 x double> %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load <1 x double>, ptr %a.addr, align 8 # | %1 = load double, ptr %b.addr, align 8 # | store <1 x double> %0, ptr %__p0.addr.i, align 8 # | store double %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x double>, ptr %__p0.addr.i, align 8 # | %3 = load double, ptr %__p1.addr.i, align 8 # | %4 = bitcast <1 x double> %2 to double # | %5 = fmul double %4, %3 # | store double %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x double>, ptr %ref.tmp.i, align 8 # | store <1 x double> %6, ptr %__ret.i, align 8 # | %7 = load <1 x double>, ptr %__ret.i, align 8 # | ret <1 x double> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <2 x float>, align 8 # | %__ret_626 = alloca float, align 4 # | %__s0_626 = alloca float, align 4 # | %__s1_626 = alloca <2 x float>, align 8 # | %__ret = alloca float, align 4 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_626, align 4 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %1, ptr %__s1_626, align 8 # | %2 = load float, ptr %__s0_626, align 4 # | %3 = load <2 x float>, ptr %__s1_626, align 8 # | store <2 x float> %3, ptr %__s0, align 8 # | %4 = load <2 x float>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x float> %4, i32 1 # | store float %vget_lane, ptr %ref.tmp, align 4 # | %5 = load float, ptr %ref.tmp, align 4 # | store float %5, ptr %__ret, align 4 # | %6 = load float, ptr %__ret, align 4 # | store float %6, ptr %tmp, align 4 # | %7 = load float, ptr %tmp, align 4 # | store float %2, ptr %__p0.addr.i, align 4 # | store float %7, ptr %__p1.addr.i, align 4 # | %8 = load float, ptr %__p0.addr.i, align 4 # | %9 = load float, ptr %__p1.addr.i, align 4 # | %vmulxs_f32.i = call float @llvm.aarch64.neon.fmulx.f32(float %8, float %9) # | store float %vmulxs_f32.i, ptr %ref.tmp.i, align 4 # | %10 = load float, ptr %ref.tmp.i, align 4 # | store float %10, ptr %__ret.i, align 4 # | %11 = load float, ptr %__ret.i, align 4 # | store float %11, ptr %__ret_626, align 4 # | %12 = load float, ptr %__ret_626, align 4 # | store float %12, ptr %tmp1, align 4 # | %13 = load float, ptr %tmp1, align 4 # | ret float %13 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__p1.addr.i = alloca float, align 4 # | %__ret.i = alloca float, align 4 # | %ref.tmp.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 16 # | %__ret_636 = alloca float, align 4 # | %__s0_636 = alloca float, align 4 # | %__s1_636 = alloca <4 x float>, align 16 # | %__ret = alloca float, align 4 # | %__s0 = alloca <4 x float>, align 16 # | %ref.tmp = alloca float, align 4 # | %tmp = alloca float, align 4 # | %tmp1 = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 16 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__s0_636, align 4 # | %1 = load <4 x float>, ptr %b.addr, align 16 # | store <4 x float> %1, ptr %__s1_636, align 16 # | %2 = load float, ptr %__s0_636, align 4 # | %3 = load <4 x float>, ptr %__s1_636, align 16 # | store <4 x float> %3, ptr % # | ... # `---data was truncated (10240/74804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000559156f5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559156f530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559156f5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8e39b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8e39b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8e39b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8e39b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559156eebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559156eebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559156ed0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559156b800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559156b7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8e39b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8e39b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8e39b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559156b7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-scalar-x-indexed-elem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (1587 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c (1588 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrev8.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e01646815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0164650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e01646889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1706249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17062a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1706249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1706231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0163fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e0163fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e0163e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e0160920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e016091dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1706232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17062330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17062330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e016091cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c (1589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c (1590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c (1591 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/302389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561be45515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561be4520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561be45589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d25933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d2598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d25933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d2591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561be3eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561be3eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561be3cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561be07f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561be07edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d2591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d2591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d2591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561be07ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c (1592 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1 # | ... # `---data was truncated (10240/26772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e3acdb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e3acdaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e3acdb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa823333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa82338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa823333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa82331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e3acd47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e3acd47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e3acd2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e3ac9dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e3ac9dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa82331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa82331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa82331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e3ac9dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c (1593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acb008015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055acb007d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055acb008089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fe1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fe1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fe1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fe1aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acb0015e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055acb0015c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055acafffab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055acafcaa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055acafca9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4fe1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fe1aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fe1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acafca9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c (1594 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc0880e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc0880b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc0880e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc23e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc23e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc23e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc23e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc087a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc087a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc08788b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc084380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc08437dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc23e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc23e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc23e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc08437cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c (1595 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbb3aeb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbb3ae80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbb3aeb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8be5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8be558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8be5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8be551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbb3a80e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbb3a80c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbb3a65b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbb37150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbb3714dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8be551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8be551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8be551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbb3714cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c (1596 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fec432615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fec43230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fec432689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3543333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f354338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3543333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f354331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fec42bbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fec42bbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fec42a0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fec3f500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fec3f4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f354331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f354331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f354331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fec3f4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c (1597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5ea20515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5ea2020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5ea20589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc50f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc50f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc50f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc50f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5ea19ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5ea19ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5ea17fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5e9e2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5e9e2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc50f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc50f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc50f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5e9e2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c (1598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d958e5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d958e4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d958e5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6e9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6e938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6e9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6e931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d958de7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d958de7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d958dccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d958a7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d958a7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6e931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6e931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6e931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d958a7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c (1599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align # | ... # `---data was truncated (10240/39586) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055899e34615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055899e3430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055899e34689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eef231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055899e2dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055899e2dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055899e2c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055899df700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055899df6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8eef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055899df6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c (1600 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_i8m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf8x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e8_v_u8m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, # | ... # `---data was truncated (10240/27986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056510721215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056510720f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056510721289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25c6905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25c695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25c6905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25c68ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651071a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005651071a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056510718cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565106e3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565106e3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25c68eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25c68ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25c68ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565106e3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c (1601 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563f41d9915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563f41d960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563f41d9989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bf0c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bf0ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bf0c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bf0c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563f41d2ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563f41d2ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563f41d13b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563f419c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563f419c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6bf0c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bf0c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bf0c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563f419c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c (1602 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb1cc8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb1cc880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb1cc8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f160d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f160d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f160d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f160d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb1cc20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb1cc20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb1cc05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb1c8b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb1c8b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f160d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f160d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f160d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb1c8b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c (1603 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,instcombine,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.nxv2i32.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ld1.nxv2i32.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_s64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64(, , i64) #3 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_u64( %pg, %bases) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %bases.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store %bases, ptr %bases.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load , ptr %bases.addr, align 16 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv2i32.nxv2i64( %2, %1, i64 0) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.aarch64.sve.ld1.gather.nxv2i32.p0(, ptr, ) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_s64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_s64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64offset_u64( %pg, ptr noundef %base, %offsets) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %offsets.addr = alloca , align 16 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %offsets, ptr %offsets.addr, align 16 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %offsets.addr, align 16 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = call @llvm.aarch64.sve.ld1.gather.nxv2i32.p0( %3, ptr %1, %2) # | %5 = sext %4 to # | ret %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svld1sw_gather_u64base_offset_s64( %pg, %bases, i64 noundef %offset) #0 { # | entry: # | %pg.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c (1604 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efc2a9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055efc2a8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055efc2a9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51b7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51b78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51b7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51b7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efc2a25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055efc2a25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055efc2a0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055efc26ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055efc26b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f51b7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51b78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51b78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efc26b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c (1605 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsra.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsra_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c (1606 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl # | ... # `---data was truncated (10240/27434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559521f1615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559521f130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559521f1689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7389d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7389d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7389d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7389d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559521eabe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559521eabc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559521e90b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559521b400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559521b3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7389d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7389d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7389d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559521b3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c (1607 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_s_w4_u8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a21f75115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a21f74e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a21f75189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e14649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e146a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e14649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e14631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a21f6e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a21f6e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a21f6cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a21f37b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a21f37add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e14632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e146330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e146330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a21f37acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c (1608 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 8 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> nou # | ... # `---data was truncated (10240/28396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine # | #0 0x0000560676c6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560676c610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560676c6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f073c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f073c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f073c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f073c831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560676bf9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560676bf9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560676bdeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056067688e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056067688ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f073c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f073c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f073c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056067688dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c (1609 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618f8b3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005618f8b350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005618f8b3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe738449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7384a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe738449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe738431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618f8acde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005618f8acdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005618f8ab2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005618f87620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005618f8761dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe738432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7384330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7384330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618f8761cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c (1610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr # | ... # `---data was truncated (10240/15320) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055739c79915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055739c7960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055739c79989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01e9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01e9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01e9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01e9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055739c72ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055739c72ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055739c713b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055739c3c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055739c3c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01e9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01e9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01e9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055739c3c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c (1611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf2_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16m1_u32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca # | ... # `---data was truncated (10240/43625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a1b96a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a1b9670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a1b96a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb478333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb47838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb478333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb47831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a1b8ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a1b8ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a1b8e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a1b5940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a1b593dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb47831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb47831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb47831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a1b593cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c (1612 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c (1613 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallbac # | ... # `---data was truncated (10240/66028) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c8e1f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c8e1ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c8e1f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1965333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f196538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1965333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f196531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c8e185e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c8e185c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c8e16ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c8de1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c8de19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f196531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f196531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f196531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c8de19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c (1614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056288867f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056288867c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056288867f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10cb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10cb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10cb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10cb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562888614e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562888614c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005628885f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005628882a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005628882a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f10cb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10cb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10cb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628882a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c (1615 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b61998c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6199890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b61998c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc63df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc63df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc63df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc63df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b619921e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b619921c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b619906b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6195b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6195b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc63df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc63df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc63df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6195b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c (1616 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579ca4f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005579ca4ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005579ca4f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe71c705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe71c75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe71c705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe71c6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579ca487e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579ca487c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579ca46cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579ca11c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005579ca11bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe71c6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe71c6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe71c6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579ca11bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c (1617 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c (1618 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce7784d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce7784a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce7784d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f250cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f250cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f250cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f250cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce777e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce777e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce777c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce774770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce77476dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f250cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f250cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f250cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce77476cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl (1619 of 27911) ******************** TEST 'Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_first -DTYPE=float -DCONST=256.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O0 -cl-std=CL2.0 -triple amdgpu-amd-amdhsa -fno-ident -DKERNEL_NAME=test_kernel_second -DTYPE=int -DCONST=128.0f -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.1.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=globalopt -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.opt.0.bc /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGenOpenCL/Output/amdgpu-enqueue-kernel-linking.cl.tmp.0.bc # | #0 0x00005639b77c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639b77bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639b77c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4458705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f445875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4458705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44586ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639b7757e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639b7757c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639b773cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639b73ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639b73ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f44586eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44586ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44586ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639b73ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c (1620 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32f16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c (1621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab8e16515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ab8e1620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ab8e16589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c29933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c2998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c29933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c2991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab8e0fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ab8e0fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ab8e0dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ab8dd8f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ab8dd8edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c2991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c2991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c2991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab8dd8ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c (1622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c (1623 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632a317915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632a31760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005632a317989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1086733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f108678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1086733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f108671b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632a310ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005632a310ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005632a30f3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632a2da30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005632a2da2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f108671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f108671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f108671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005632a2da2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c (1624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m2( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %2, %1, i64 4) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m4( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %4, %1, i64 4) # | %6 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %5, %2, i64 8) # | %7 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %6, %3, i64 12) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m1_bf16m8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | %v4.addr = alloca , align 2 # | %v5.addr = alloca , align 2 # | %v6.addr = alloca , align 2 # | %v7.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | store %v4, ptr %v4.addr, align 2 # | store %v5, ptr %v5.addr, align 2 # | store %v6, ptr %v6.addr, align 2 # | store %v7, ptr %v7.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = load , ptr %v4.addr, align 2 # | %5 = load , ptr %v5.addr, align 2 # | %6 = load , ptr %v6.addr, align 2 # | %7 = load , ptr %v7.addr, align 2 # | %8 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | %9 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %8, %1, i64 4) # | %10 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %9, %2, i64 8) # | %11 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %10, %3, i64 12) # | %12 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %11, %4, i64 16) # | %13 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %12, %5, i64 20) # | %14 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %13, %6, i64 24) # | %15 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %14, %7, i64 28) # | ret %15 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m4( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %2, %1, i64 8) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m2_bf16m8( %v0, %v1, %v2, %v3) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | %v2.addr = alloca , align 2 # | %v3.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | store %v2, ptr %v2.addr, align 2 # | store %v3, ptr %v3.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = load , ptr %v2.addr, align 2 # | %3 = load , ptr %v3.addr, align 2 # | %4 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, %0, i64 0) # | %5 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %4, %1, i64 8) # | %6 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %5, %2, i64 16) # | %7 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %6, %3, i64 24) # | ret %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcreate_v_bf16m4_bf16m8( %v0, %v1) #0 { # | entry: # | %v0.addr = alloca , align 2 # | %v1.addr = alloca , align 2 # | store %v0, ptr %v0.addr, align 2 # | store %v1, ptr %v1.addr, align 2 # | %0 = load , ptr %v0.addr, align 2 # | %1 = load , ptr %v1.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, %0, i64 0) # | %3 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %2, %1, i64 16) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vcreate_v_bf16mf4x2( %v0, %v1) #0 { # | entry: # | %v0.add # | ... # `---data was truncated (10240/71275) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e83efc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e83efbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e83efc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59d8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59d88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59d8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59d8831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e83ef55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e83ef55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e83ef3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e83ebea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e83ebe9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f59d8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59d88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59d88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e83ebe9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c (1625 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c (1626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f16m8_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei8_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/288058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557933bf715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557933bf40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557933bf789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6a171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557933b8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557933b8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557933b71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579338210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557933820dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6a171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557933820cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c (1627 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 # | ... # `---data was truncated (10240/66065) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ded6ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ded6eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ded6ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9350133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f935018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9350133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f935011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ded683e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ded683c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ded668b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ded3180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ded317dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f935011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f935011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f935011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ded317cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c (1628 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +bf16 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_bf16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_low_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v8i8(<8 x i8> %4) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %5, ptr %__ret.i, align 16 # | %6 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt1_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl1.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcvt2_high_bf16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %ref.tmp.i = alloca <8 x bfloat>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x bfloat> @llvm.aarch64.neon.fp8.cvtl2.v8bf16.v16i8(<16 x i8> %2) # | store <8 x bfloat> %vbfcvt2.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp.i, align 16 # | store <8 x bfloat> %4, ptr %__ret.i, align 16 # | %5 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %4, ptr %__ret.i, align 16 # | %5 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt1_low_f16_mf8_fpm(<16 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <16 x i8>, align 16 # | %fpm.addr = alloca i64, align 8 # | store <16 x i8> %op, ptr %op.addr, align 16 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <16 x i8>, ptr %op.addr, align 16 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | %4 = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %2, i64 0) # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt1.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl1.v8f16.v8i8(<8 x i8> %4) # | store <8 x half> %vbfcvt1.i, ptr %ref.tmp.i, align 16 # | %5 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %5, ptr %__ret.i, align 16 # | %6 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcvt2_f16_mf8_fpm(<8 x i8> %op, i64 noundef %fpm) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca i64, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <8 x half>, align 16 # | %op.addr = alloca <8 x i8>, align 8 # | %fpm.addr = alloca i64, align 8 # | store <8 x i8> %op, ptr %op.addr, align 8 # | store i64 %fpm, ptr %fpm.addr, align 8 # | %0 = load <8 x i8>, ptr %op.addr, align 8 # | %1 = load i64, ptr %fpm.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store i64 %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load i64, ptr %__p1.addr.i, align 8 # | call void @llvm.aarch64.set.fpmr(i64 %3) # | %vbfcvt2.i = call <8 x half> @llvm.aarch64.neon.fp8.cvtl2.v8f16.v8i8(<8 x i8> %2) # | store <8 x half> %vbfcvt2.i, ptr %ref.tmp.i # | ... # `---data was truncated (10240/23350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x0000558967b8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558967b870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558967b8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0150849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01508a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0150849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0150831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558967b1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558967b1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558967b04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589677b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005589677b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0150832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01508330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01508330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589677b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c (1629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555825a9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555825a8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555825a9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9883133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f988318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9883133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f988311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555825a25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555825a25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555825a0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558256ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558256b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f988311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f988311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f988311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558256b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c (1630 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055761f1b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055761f1b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055761f1b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9a3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9a3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9a3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9a3aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055761f14be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055761f14bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055761f130b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055761ede00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055761eddfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9a3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9a3aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9a3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055761eddfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c (1631 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056240f73c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056240f7390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056240f73c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5670305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f567035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5670305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56702ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056240f6d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056240f6d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056240f6b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056240f3660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056240f365dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56702eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56702ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56702ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056240f365cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c (1632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557abaab715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557abaab40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557abaab789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff155333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff15538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff155333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff15531b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557abaa4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557abaa4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557abaa31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557aba6e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557aba6e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff15531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff15531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff15531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aba6e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c (1633 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3e # | ... # `---data was truncated (10240/228857) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581dd2aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005581dd2a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005581dd2aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f044bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f044bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f044bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f044bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581dd23fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005581dd23fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005581dd224b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005581dced40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005581dced3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f044bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f044bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f044bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581dced3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c (1634 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564af221715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564af22140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564af221789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f262b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f262b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f262b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f262b231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564af21ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564af21acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564af2191b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564af1e410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564af1e40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f262b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f262b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f262b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564af1e40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c (1635 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/225205) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564af0ff715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564af0ff40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564af0ff789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f19e8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19e8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f19e8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f19e8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564af0f8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564af0f8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564af0f71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564af0c210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564af0c20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f19e8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19e8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19e8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564af0c20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon-vcombine.c (1636 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon-vcombine.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 16 # | %low.addr = alloca <8 x i8>, align 8 # | %high.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %low, ptr %low.addr, align 8 # | store <8 x i8> %high, ptr %high.addr, align 8 # | %0 = load <8 x i8>, ptr %low.addr, align 8 # | %1 = load <8 x i8>, ptr %high.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <8 x i8> %2, <8 x i8> %3, <16 x i32> # | store <16 x i8> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 16 # | %low.addr = alloca <4 x i16>, align 8 # | %high.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %low, ptr %low.addr, align 8 # | store <4 x i16> %high, ptr %high.addr, align 8 # | %0 = load <4 x i16>, ptr %low.addr, align 8 # | %1 = load <4 x i16>, ptr %high.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x i16> %2, <4 x i16> %3, <8 x i32> # | store <8 x i16> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x i32>, align 16 # | %low.addr = alloca <2 x i32>, align 8 # | %high.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %low, ptr %low.addr, align 8 # | store <2 x i32> %high, ptr %high.addr, align 8 # | %0 = load <2 x i32>, ptr %low.addr, align 8 # | %1 = load <2 x i32>, ptr %high.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <2 x i32> %2, <2 x i32> %3, <4 x i32> # | store <4 x i32> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 16 # | %low.addr = alloca <1 x i64>, align 8 # | %high.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %low, ptr %low.addr, align 8 # | store <1 x i64> %high, ptr %high.addr, align 8 # | %0 = load <1 x i64>, ptr %low.addr, align 8 # | %1 = load <1 x i64>, ptr %high.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <1 x i64> %2, <1 x i64> %3, <2 x i32> # | store <2 x i64> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 16 # | %low.addr = alloca <4 x half>, align 8 # | %high.addr = alloca <4 x half>, align 8 # | store <4 x half> %low, ptr %low.addr, align 8 # | store <4 x half> %high, ptr %high.addr, align 8 # | %0 = load <4 x half>, ptr %low.addr, align 8 # | %1 = load <4 x half>, ptr %high.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x half>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x half>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x half> %2, <4 x half> %3, <8 x i32> # | store <8 x half> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 { # | entry: # | %__p0.addr. # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea365d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea365d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea365d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe264133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe26418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe264133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe26411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea3656ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea3656ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea3654fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea361ff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea361fedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe26411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe26411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe26411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea361fecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon-vcombine.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c (1637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_f16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_i16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e16_v_u16m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df9c74615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df9c7430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df9c74689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57de933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57de98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57de933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57de91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df9c6dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df9c6dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df9c6c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df9c3700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df9c36fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f57de91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57de91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57de91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df9c36fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c (1638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac72f8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac72f890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac72f8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5dc649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5dc6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5dc649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5dc631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac72f21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac72f21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac72f06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac72bb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac72bb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff5dc632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5dc6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5dc6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac72bb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c (1639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr # | ... # `---data was truncated (10240/27541) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056273e54815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056273e5450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056273e54889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1931449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19314a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1931449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1931431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056273e4dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056273e4ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056273e4c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056273e1720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056273e171dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1931432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19314330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19314330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056273e171cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c (1640 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c (1641 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret # | ... # `---data was truncated (10240/25287) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b3880415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b388010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b3880489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad5e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad5e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad5e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad5e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b38799e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b38799c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b3877eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b3842e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b3842ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad5e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad5e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad5e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b3842dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c (1642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055947530e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055947530b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055947530e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99d0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99d098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99d0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99d091b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594752a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594752a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559475288b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559474f380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559474f37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99d091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99d091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99d091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559474f37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c (1643 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tup # | ... # `---data was truncated (10240/11051) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055920d4dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055920d4da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055920d4dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fdcc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fdcc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fdcc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fdcc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055920d472e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055920d472c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055920d457b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055920d1070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055920d106dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9fdcc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fdcc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fdcc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055920d106cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c (1644 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c (1645 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/18595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5e0e8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a5e0e7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a5e0e8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0231249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02312a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0231249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0231231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5e0e16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a5e0e16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a5e0dfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5e0aab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a5e0aaadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0231232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02312330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02312330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5e0aaacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/veorq.c (1646 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/veorq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df1414f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df1414c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df1414f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4b3c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4b3c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4b3c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4b3c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df140e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df140e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df140c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df13d790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df13d78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff4b3c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4b3c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4b3c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df13d78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/veorq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c (1647 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c (1648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, %0, i64 %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 immarg, i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_se_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.nxv8i64.i64.i64(i64 immarg, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.nxv1i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.nxv2i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 3, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.nxv4i64.i64.i64(i64 immarg, , i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xv_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl. # | ... # `---data was truncated (10240/11504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0c7ba615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0c7ba30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0c7ba689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41e1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0c7b3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0c7b3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f0c7b20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0c77d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f0c77cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41e1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0c77cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c (1649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573758ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573758a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005573758ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc47733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc4778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc47733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc4771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557375840e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557375840c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557375825b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573754d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005573754d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcc4771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc4771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc4771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573754d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c (1650 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local signext i32 @test() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0) # | %conv = trunc i64 %0 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055965dad215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055965dacf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055965dad289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd376533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd37658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd376533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd37651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055965da67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055965da67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055965da4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055965d6fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055965d6fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd37651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd37651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd37651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055965d6fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64V /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c (1651 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d45671b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d4567180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d45671b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa72f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa72f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa72f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa72f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4566b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d4566b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d456695b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d4563450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d456344dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa72f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa72f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa72f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d456344cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c (1652 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c (1653 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c (1654 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, %o # | ... # `---data was truncated (10240/70102) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5ff20715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5ff2040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b5ff20789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faacaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faacaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faacaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faacaa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5ff19ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b5ff19cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5ff181b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5fee310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b5fee30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faacaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faacaa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faacaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5fee30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-neon-endianness.c (1655 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-endianness.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8a-arm-none-eabihf -target-cpu generic -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-arm-none-eabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_0(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_1(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_2(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 2 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x4_t_lane_3(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <4 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | store <4 x i32> %0, ptr %__s0, align 8 # | %1 = load <4 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x i32> %1, i32 3 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_0(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 0 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @int32x2_t_lane_1(<2 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i32>, align 8 # | %__ret = alloca i32, align 4 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__s0, align 8 # | %1 = load <2 x i32>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i32> %1, i32 1 # | store i32 %vget_lane, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 0 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @int64x2_t_lane_1(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %__ret = alloca i64, align 8 # | %__s0 = alloca <2 x i64>, align 8 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | store <2 x i64> %0, ptr %__s0, align 8 # | %1 = load <2 x i64>, ptr %__s0, align 8 # | %vget_lane = extractelement <2 x i64> %1, i32 1 # | store i64 %vget_lane, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=instcombine -o - # | #0 0x000055d7bb18515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7bb1820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7bb18589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ba7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ba7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ba7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ba7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7bb11ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7bb11ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7bb0ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7badaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7badaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ba7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ba7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ba7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7badaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-endianness.c --check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c (1656 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( # | ... # `---data was truncated (10240/179185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055651ba4c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055651ba490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055651ba4c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3edf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3edf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3edf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3edf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055651b9e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055651b9e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055651b9c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055651b6760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055651b675dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3edf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3edf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3edf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055651b675cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c (1657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory # | ... # `---data was truncated (10240/69669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622ae87815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005622ae8750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005622ae87889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe358a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe358a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe358a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe358a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622ae80de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005622ae80dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005622ae7f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622ae4a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622ae4a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe358a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe358a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe358a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622ae4a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c (1658 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c (1659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056176a78115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056176a77e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056176a78189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcadb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcadb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcadb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcadb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056176a716e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056176a716c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056176a6fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056176a3ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056176a3aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdcadb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcadb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcadb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056176a3aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c (1660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f370ec515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f370ec20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f370ec589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69b6449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69b64a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69b6449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69b6431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f370e5ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f370e5ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f370e3fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f370aef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f370aeedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f69b6432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69b64330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69b64330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f370aeecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c (1661 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd0004215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd0003f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd0004289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d68d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d68d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d68d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d68d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcfffd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fcfffd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fcfffbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fcffc6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fcffc6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d68d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d68d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d68d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcffc6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c (1662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b93d3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b93d330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b93d3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f857be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f857bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f857be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f857be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b93ccbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b93ccbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b93cb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b939600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b9395fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f857be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f857be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f857be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b9395fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c (1663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bc2ec615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555bc2ec30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555bc2ec689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bc3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bc358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bc3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bc351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bc2e5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555bc2e5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555bc2e40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555bc2af00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555bc2aefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3bc351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bc351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bc351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bc2aefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c (1664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf8x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_u8m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056063903815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005606390350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056063903889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8c2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8c218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8c2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8c211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560638fcde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560638fcdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560638fb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560638c620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560638c61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8c211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8c211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8c211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560638c61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c (1665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d3b1f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d3b1f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d3b1f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f507be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f507bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f507be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f507be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d3b18de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d3b18dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d3b172b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d3ae220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d3ae21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f507be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f507be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f507be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d3ae21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c (1666 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c (1667 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596d868015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596d867d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596d868089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e0b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e0b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e0b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e0b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596d8615e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596d8615c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596d85fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596d82aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596d82a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e0b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e0b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e0b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596d82a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c (1668 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , pt # | ... # `---data was truncated (10240/32402) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4f6b2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4f6b270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b4f6b2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0204905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f020495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0204905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02048ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4f6abfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4f6abfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4f6aa4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4f67540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b4f6753dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02048eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02048ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02048ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4f6753cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c (1669 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005586a653815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005586a65350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005586a653889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d0d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d0d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d0d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d0d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586a64cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005586a64cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005586a64b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005586a61620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005586a6161dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d0d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d0d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d0d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005586a6161cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c (1670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/72143) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e4f68515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564e4f6820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564e4f68589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafa5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafa5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafa5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafa5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e4f61ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564e4f61ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564e4f5ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564e4f2af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564e4f2aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fafa5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafa5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafa5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e4f2aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c (1671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c (1672 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056533f47015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056533f46d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056533f47089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa03f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa03f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa03f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa03eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056533f405e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056533f405c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056533f3eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056533f09a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056533f099dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa03eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa03eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa03eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056533f099cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c (1673 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c49b9c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c49b9be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c49b9c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdc24c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdc24ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdc24c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdc24c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c49b956e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c49b956c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c49b93bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c49b5eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c49b5eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdc24c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdc24c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdc24c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c49b5eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c (1674 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv4i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv4i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_s64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.aarch64.sve.convert.from.svbool.nxv2i1() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) # | declare @llvm.aarch64.sve.ldnf1.nxv2i16.p0(, ptr) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u32( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_u64( %pg, ptr noundef %base) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %3 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %2, ptr %1) # | %4 = sext %3 to # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_s64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u32( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv4i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svldnf1sh_vnum_u64( %pg, ptr noundef %base, i64 noundef %vnum) #0 { # | entry: # | %pg.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vnum.addr = alloca i64, align 8 # | store %pg, ptr %pg.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vnum, ptr %vnum.addr, align 8 # | %0 = load , ptr %pg.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vnum.addr, align 8 # | %3 = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %0) # | %4 = getelementptr , ptr %1, i64 %2 # | %5 = call @llvm.aarch64.sve.ldnf1.nxv2i16.p0( %3, ptr %4) # | %6 = sext %5 to # | ret %6 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sve" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read, inaccessiblemem: readwrite) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056118f7b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056118f7b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056118f7b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2de061bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2de06725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2de061ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2de0603507 abort ./stdlib/abort.c:85:3 # | #7 0x000056118f748e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056118f748c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056118f72db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056118f3dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056118f3dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2de0604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2de06050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2de06050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056118f3dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c (1675 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556781ce815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556781ce50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556781ce889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4911449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f49114a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4911449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4911431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556781c7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556781c7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556781c62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567819120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556781911dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4911432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f49114330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f49114330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556781911cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c (1676 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfm # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564c02f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564c02ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005564c02f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f370d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f370d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f370d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f370d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564c0286e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005564c0286c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005564c026bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005564bff1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005564bff1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f370d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f370d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f370d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564bff1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c (1677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056131dd9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056131dd950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056131dd9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32df105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32df15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32df105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32df0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056131dd2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056131dd2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056131dd12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056131d9c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056131d9c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f32df0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32df0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32df0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056131d9c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c (1678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c (1679 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f16m8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgatherei16_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2f32.i64( %0, % # | ... # `---data was truncated (10240/291999) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613e87b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613e87b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005613e87b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6216933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f621698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6216933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f621691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613e874be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005613e874bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005613e8730b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005613e83e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005613e83dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f621691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f621691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f621691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613e83dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c (1680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c (1681 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpairo_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = # | ... # `---data was truncated (10240/125488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edb80f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055edb80ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055edb80f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18f6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18f6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18f6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18f6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edb8085e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055edb8085c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055edb806ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055edb7d1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055edb7d19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f18f6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18f6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18f6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edb7d19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c (1682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/13593) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f35713815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3571350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f35713889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ce0e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ce0ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ce0e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ce0e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3570cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f3570cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f3570b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f356d620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f356d61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ce0e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ce0e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ce0e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f356d61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c (1683 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %sr # | ... # `---data was truncated (10240/288111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6bd58b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6bd5880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d6bd58b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a1661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a166725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a1661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a16603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6bd520e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d6bd520c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d6bd505b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6bd1b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6bd1b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5a16604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a166050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a166050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6bd1b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c (1684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/76635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d20398215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d20397f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d20398289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda06b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda06b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda06b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda06aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d203917e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d203917c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d2038fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d2035ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d2035abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fda06aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda06aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda06aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2035abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c (1685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e6989215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559e6988f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559e6989289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facd7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facd70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facd7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facd7031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e69827e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559e69827c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559e6980cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559e694bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559e694bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007facd7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facd70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facd70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e694bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c (1686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9f54d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9f54d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9f54d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0272d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0272d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0272d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0272d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9f546de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9f546dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9f5452b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9f51020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9f5101dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0272d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0272d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0272d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9f5101cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c (1687 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575e09e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575e09e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575e09e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb661d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb661d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb661d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb661d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575e097ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575e097ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575e0963b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575e06130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575e0612dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb661d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb661d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb661d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575e0612cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c (1688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | # | ... # `---data was truncated (10240/207749) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056085113b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005608511380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056085113b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7798f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7798f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7798f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7798f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608510d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005608510d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005608510b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560850d650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560850d64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7798f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7798f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7798f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560850d64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c (1689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb9d07c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb9d0790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb9d07c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cd9733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cd978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cd9733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cd971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb9d011e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb9d011c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb9cff6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb9cca60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb9cca5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2cd971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cd971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cd971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb9cca5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c (1690 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x # | ... # `---data was truncated (10240/29267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055799a8a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055799a8a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055799a8a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1831533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f183158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1831533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f183151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055799a83ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055799a83ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055799a823b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055799a4d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055799a4d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f183151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f183151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f183151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055799a4d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-cde-vec.c (1691 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-vec.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1q_u8() #0 { # | entry: # | %0 = call <16 x i8> @llvm.arm.cde.vcx1q(i32 0, i32 1111) # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1q(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_1(<16 x i8> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 1, <16 x i8> %0, i32 1112) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx1qa_2(<4 x i32> noundef %acc) #0 { # | entry: # | %acc.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %acc, ptr %acc.addr, align 8 # | %0 = load <4 x i32>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x i32> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx1qa(i32 0, <16 x i8> %1, i32 1113) # | %3 = bitcast <16 x i8> %2 to <4 x i32> # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx2q_u8(<8 x half> noundef %n) #0 { # | entry: # | %n.addr = alloca <8 x half>, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | %0 = load <8 x half>, ptr %n.addr, align 8 # | %1 = bitcast <8 x half> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 111) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2q(i32 immarg, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2q(<4 x float> noundef %n) #0 { # | entry: # | %n.addr = alloca <4 x float>, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %n.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = call <16 x i8> @llvm.arm.cde.vcx2q(i32 1, <16 x i8> %1, i32 112) # | %3 = bitcast <16 x i8> %2 to <4 x float> # | ret <4 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa(<4 x float> noundef %acc, <2 x i64> noundef %n) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <2 x i64>, align 8 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = bitcast <4 x float> %0 to <16 x i8> # | %2 = load <2 x i64>, ptr %n.addr, align 8 # | %3 = bitcast <2 x i64> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx2qa(i32 0, <16 x i8> %1, <16 x i8> %3, i32 113) # | %5 = bitcast <16 x i8> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx2qa(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3q_u8(<8 x i16> noundef %n, <4 x i32> noundef %m) #0 { # | entry: # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x i32> %m, ptr %m.addr, align 8 # | %0 = load <8 x i16>, ptr %n.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <16 x i8> # | %2 = load <4 x i32>, ptr %m.addr, align 8 # | %3 = bitcast <4 x i32> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 0, <16 x i8> %1, <16 x i8> %3, i32 11) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3q(i32 immarg, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q(<2 x i64> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %n.addr = alloca <2 x i64>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <2 x i64> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <2 x i64>, ptr %n.addr, align 8 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %2 = load <4 x float>, ptr %m.addr, align 8 # | %3 = bitcast <4 x float> %2 to <16 x i8> # | %4 = call <16 x i8> @llvm.arm.cde.vcx3q(i32 1, <16 x i8> %1, <16 x i8> %3, i32 12) # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | ret <2 x i64> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx3qa(<16 x i8> noundef %acc, <8 x i16> noundef %n, <4 x float> noundef %m) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %n.addr = alloca <8 x i16>, align 8 # | %m.addr = alloca <4 x float>, align 8 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store <8 x i16> %n, ptr %n.addr, align 8 # | store <4 x float> %m, ptr %m.addr, align 8 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load <8 x i16>, ptr %n.addr, align 8 # | %2 = bitcast <8 x i16> %1 to <16 x i8> # | %3 = load <4 x float>, ptr %m.addr, align 8 # | %4 = bitcast <4 x float> %3 to <16 x i8> # | %5 = call <16 x i8> @llvm.arm.cde.vcx3qa(i32 1, <16 x i8> %0, <16 x i8> %2, <16 x i8> %4, i32 13) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx3qa(i32 immarg, <16 x i8>, <16 x i8>, <16 x i8>, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcx1q_m(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = call <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> %0, i32 1111, <8 x i1> %3) # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 immarg, <8 x i16>, i32 immarg, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vcx1qa_m(<16 x i8> noundef %acc, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %acc, ptr %acc.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %acc.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = call <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> %0, i32 1112, <16 x i1> %3) # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 immarg, <16 x i8>, i32 immarg, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcx2q_m(<4 x i32> noundef %inactive, <4 x float> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %n.addr, align 8 # | %2 = bitcast <4 x float> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %0, <16 x i8> %2, i32 111, <4 x i1> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcx2qa_m(<4 x float> noundef %acc, <8 x half> noundef %n, i16 noundef zeroext %p) #0 { # | entry: # | %acc.addr = alloca <4 x float>, align 8 # | %n.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %acc, ptr %acc.addr, align 8 # | store <8 x half> %n, ptr %n.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %acc.addr, align 8 # | %1 = load <8 x half>, ptr %n.addr, align 8 # | %2 = bitcast <8 x half> %1 to <16 x i8> # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <16 x i8> %2, i32 112, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, i32 immarg, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vcx3q_m(<2 x i64> noundef %inactive, <4 x float> noundef %n, <16 x i8> noundef %m, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %n.addr = alloca <4 x float>, align 8 # | %m.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | ... # `---data was truncated (10240/13030) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ddc75815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ddc7550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ddc75889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9819d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9819d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9819d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9819d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ddc6ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ddc6edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ddc6d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ddc3820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ddc381dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9819d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9819d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9819d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ddc381cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-vec.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c (1692 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fd203a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fd20370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fd203a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96ef01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96ef0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96ef01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96ef003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fd1fcfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fd1fcfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fd1fb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fd1c640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fd1c63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f96ef004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96ef0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96ef0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fd1c63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c (1693 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c (1694 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c88a73c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c88a7390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c88a73c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfb4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfb458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfb4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfb451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c88a6d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c88a6d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c88a6b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c88a3660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c88a365dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfb451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfb451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfb451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c88a365cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c (1695 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf8x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_u8m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask. # | ... # `---data was truncated (10240/18972) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056147018b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614701880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056147018b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a07249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a072a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a07249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a07231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561470120e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561470120c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561470105b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056146fdb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056146fdb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a07232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a072330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a072330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056146fdb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c (1696 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c (1697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca # | ... # `---data was truncated (10240/14311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b98d04615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b98d0430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b98d04689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa82c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa82c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa82c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa82c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b98cfdbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b98cfdbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b98cfc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b98cc700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b98cc6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa82c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa82c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa82c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b98cc6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c (1698 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff37fa315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff37fa00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff37fa389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9d8649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9d86a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9d8649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9d8631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff37f38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff37f38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff37f1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff37bcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff37bccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9d8632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9d86330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9d86330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff37bcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c (1699 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dedb6fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dedb6fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dedb6fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f656e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f656e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f656e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f656e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dedb692e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dedb692c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dedb677b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dedb3270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dedb326dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f656e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f656e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f656e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dedb326cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c (1700 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmul.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/302397) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d8cd6d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d8cd6a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d8cd6d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c30d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c30d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c30d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c30d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d8cd02e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d8cd02c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d8cce7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d8c9970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d8c996dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c30d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c30d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c30d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d8c996cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c (1701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | # | ... # `---data was truncated (10240/81507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bbad8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555bbad8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555bbad8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4974a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4974aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4974a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4974a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bbad24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555bbad24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555bbad09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555bba9b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555bba9b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4974a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4974a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4974a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bba9b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c (1702 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555797a5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555797a570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555797a5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a59449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a594a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a59449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a59431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557979efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557979efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557979d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557976840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555797683dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8a59432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a594330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a594330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555797683cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c (1703 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a79c95915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a79c9560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a79c95989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb8fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb8fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb8fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb8fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a79c8eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a79c8eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a79c8d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a79c5830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a79c582dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb8fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb8fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb8fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a79c582cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c (1704 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqaddq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqaddq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 # | ... # `---data was truncated (10240/12015) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055feb8d3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055feb8d3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055feb8d3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b34049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b340a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b34049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b34031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055feb8cd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055feb8cd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055feb8cb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055feb89690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055feb8968dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6b34032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b340330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b340330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055feb8968cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c (1705 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c (1706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr % # | ... # `---data was truncated (10240/414517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056274907115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056274906e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056274907189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9136b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9136b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9136b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9136aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562749006e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562749006c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562748febb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562748c9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562748c9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9136aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9136aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9136aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562748c9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c (1707 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564db7cc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564db7cc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564db7cc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0350e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0350ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0350e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0350e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564db7c5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564db7c5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564db7c42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564db78f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564db78f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0350e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0350e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0350e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564db78f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c (1708 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Funct # | ... # `---data was truncated (10240/64950) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1db46115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1db45e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1db46189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0c70e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0c70ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0c70e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0c70e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1db3f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1db3f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1db3dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1db08b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1db08add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0c70e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0c70e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0c70e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1db08acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c (1709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055940962f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055940962c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055940962f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f058b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f058b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f058b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f058b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594095c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594095c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594095a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594092590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559409258dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f058b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f058b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f058b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559409258cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c (1710 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f24c50915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f24c5060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f24c50989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b8fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b8fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b8fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b8fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f24c49ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f24c49ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f24c483b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f24c1330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f24c132dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b8fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b8fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b8fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f24c132cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c (1711 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c (1712 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c (1713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsub_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c (1714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055576729f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055576729c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055576729f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ffdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ffdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ffdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ffdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555767234e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555767234c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555767219b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555766ec90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555766ec8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ffdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ffdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ffdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555766ec8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c (1715 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055717bd7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055717bd710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055717bd7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79b1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055717bd09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055717bd09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055717bceeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055717b99e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055717b99ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f79b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055717b99dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c (1716 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/70979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f37261515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3726120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f37261589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82b5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82b578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82b5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82b571b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3725aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f3725aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f37258fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f37223f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f37223edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f82b571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82b571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82b571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f37223ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c (1717 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056352676d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056352676a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056352676d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4381105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f438115c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4381105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43810ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563526702e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563526702c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005635266e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635263970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563526396dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f43810eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43810ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43810ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563526396cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c (1718 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsgt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c (1719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564af0ed515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564af0ed20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564af0ed589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ecdc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ecdc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ecdc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ecdc03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564af0e6ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564af0e6ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564af0e4fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564af0aff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564af0afedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ecdc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ecdc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ecdc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564af0afecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c (1720 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree n # | ... # `---data was truncated (10240/15237) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7ae64d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7ae64a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7ae64d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6fe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6fe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6fe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6fe31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7ae5e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7ae5e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7ae5c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7ae2770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7ae276dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc6fe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6fe31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6fe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7ae276cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c (1721 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c (1722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e02d6c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e02d6be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e02d6c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3f9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3f92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3f9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3f9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e02d656e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e02d656c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e02d63bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e02d2eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e02d2eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa3f9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3f92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3f92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e02d2eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c (1723 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.add # | ... # `---data was truncated (10240/14453) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a7447415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a744710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a7447489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfa9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfa938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfa9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfa931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a74409e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a74409c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a743eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a7409e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a7409ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfa931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfa931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfa931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a7409dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c (1724 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c (1725 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4db4c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d4db4c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d4db4c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a17e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a17ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a17e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a17e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4db45de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d4db45dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d4db442b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d4db0f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d4db0f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a17e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a17e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a17e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4db0f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c (1726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d4c6c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d4c6c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d4c6c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d98f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d98f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d98f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d98f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d4c658e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d4c658c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d4c63db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d4c2ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d4c2ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d98f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d98f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d98f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d4c2eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c (1727 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/68233) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d09342915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d0934260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d09342989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb01cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb01cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb01cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb01cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0933bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d0933bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d0933a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d0930530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d093052dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb01cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb01cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb01cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d093052cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c (1728 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8( %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( poison, %0, bfloat %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056380eae215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056380eadf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056380eae289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7fc3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7fc378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7fc3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7fc371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056380ea77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056380ea77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056380ea5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056380e70c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056380e70bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7fc371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7fc371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7fc371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056380e70bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c (1729 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556bc51db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556bc51d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556bc51db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55f3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55f32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55f3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55f3231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556bc5170e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556bc5170c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556bc5155b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556bc4e050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556bc4e04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f55f3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55f32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55f32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556bc4e04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c (1730 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, a # | ... # `---data was truncated (10240/18875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec070f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec070f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec070f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5db4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5db4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5db4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5db4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec0708be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec0708bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec07070b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec06d200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec06d1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5db4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5db4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5db4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec06d1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c (1731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640314a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640314a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640314a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02ab133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02ab18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02ab133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02ab11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056403143ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056403143cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564031421b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640310d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640310d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02ab11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02ab11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02ab11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640310d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c (1732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c (1733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005584df54d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005584df54a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005584df54d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f795721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79572725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f795721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7957203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005584df4e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005584df4e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005584df4c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005584df1770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005584df176dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7957204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79572050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79572050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005584df176cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c (1734 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd191a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd1919d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd191a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d95705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d9575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d95705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d956ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd19135e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd19135c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd1911ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd18dca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd18dc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d956eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d956ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d956ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd18dc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c (1735 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vminu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vminu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vminu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c (1736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/64341) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005651d95b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005651d95b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005651d95b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9ec933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9ec98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9ec933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9ec91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005651d9548e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005651d9548c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005651d952db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005651d91dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005651d91dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc9ec91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9ec91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9ec91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005651d91dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c (1737 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/113757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b2cd7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b2cd720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b2cd7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9afc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9afca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9afc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9afc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b2cd0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b2cd0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b2ccefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b2c99f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b2c99edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9afc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9afc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9afc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b2c99ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c (1738 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv1i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d34ea115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d34e9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d34ea189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadd4f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadd4f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadd4f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadd4eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d34e36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d34e36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d34e1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d34acb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d34acadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadd4eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadd4eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadd4eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d34acacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c (1739 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6d091115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6d090e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6d091189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8bd9c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8bd9c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8bd9c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8bd9c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6d08a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6d08a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6d088bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6d053b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6d053add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8bd9c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8bd9c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8bd9c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6d053acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c (1740 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/365431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a944b8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a944b830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a944b8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd749e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd749ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd749e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd749e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a944b1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a944b1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a944b00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9447b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9447afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd749e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd749e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd749e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9447afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c (1741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf1f71415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf1f7110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf1f71489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7743a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7743aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7743a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7743a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf1f6a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf1f6a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf1f68eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf1f33e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf1f33ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7743a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7743a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7743a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf1f33dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c (1742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f40329815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4032950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f40329889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1ec249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1ec2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1ec249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1ec231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f40322de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f40322dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f403212b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f402ec20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f402ec1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1ec232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1ec2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1ec2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f402ec1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c (1743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c (1744 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2babd815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2babd50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2babd889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faeaf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faeaf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faeaf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faeaf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2bab6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2bab6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2bab52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2ba8020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2ba801dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faeaf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faeaf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faeaf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2ba801cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c (1745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597ea3cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597ea3cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597ea3cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae0ef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae0ef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae0ef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae0ef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597ea364e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597ea364c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597ea349b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597e9ff90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597e9ff8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae0ef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae0ef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae0ef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597e9ff8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c (1746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv.vector. # | ... # `---data was truncated (10240/295525) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055683730815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568373050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055683730889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ebf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ebf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ebf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ebf11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055683729de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055683729dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556837282b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556836f320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556836f31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ebf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ebf11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ebf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556836f31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c (1747 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c9a4f3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9a4f390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c9a4f3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8575f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8575f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8575f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8575f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9a4ed1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9a4ed1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9a4eb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9a4b660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9a4b65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8575f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8575f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8575f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9a4b65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c (1748 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.ad # | ... # `---data was truncated (10240/306619) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559be046915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559be04660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559be046989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ff2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ff278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ff2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ff271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559be03fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559be03fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559be03e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559be00930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559be0092dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ff271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ff271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ff271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559be0092cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c (1749 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c (1750 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.ad # | ... # `---data was truncated (10240/225647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055750e3a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055750e39d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055750e3a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b2b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b2b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b2b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b2b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055750e335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055750e335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055750e31ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055750dfca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055750dfc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3b2b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b2b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b2b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055750dfc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c (1751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005654ddea215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005654dde9f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005654ddea289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ae4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ae4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ae4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ae4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654dde37e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005654dde37c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005654dde1cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654ddacc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005654ddacbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ae4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ae4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ae4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654ddacbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c (1752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556deca6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556deca660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556deca6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7663f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7663f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7663f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7663f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dec9fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556dec9fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556dec9e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556dec6930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556dec692dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7663f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7663f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7663f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dec692cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c (1753 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555e0152915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555e015260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555e0152989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7192333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f719238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7192333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f719231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555e014bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555e014bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555e014a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555e011530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555e01152dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f719231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f719231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f719231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555e01152cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c (1754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c (1755 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc99dc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fc99dbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fc99dc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5091049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f50910a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5091049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5091031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc99d55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fc99d55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fc99d3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fc999ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fc999e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5091032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50910330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50910330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc999e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c (1756 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/AArch64/neon/subtraction.c (1757 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/subtraction.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_s8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vsubq_s8(<16 x i8> noundef %v1, <16 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__p1.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v1.addr = alloca <16 x i8>, align 16 # | %v2.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v1, ptr %v1.addr, align 16 # | store <16 x i8> %v2, ptr %v2.addr, align 16 # | %0 = load <16 x i8>, ptr %v1.addr, align 16 # | %1 = load <16 x i8>, ptr %v2.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__p1.addr.i, align 16 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <16 x i8> %2, %3 # | store <16 x i8> %sub.i, ptr %__ret.i, align 16 # | %4 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_s16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vsubq_s16(<8 x i16> noundef %v1, <8 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v1.addr = alloca <8 x i16>, align 16 # | %v2.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %v1, ptr %v1.addr, align 16 # | store <8 x i16> %v2, ptr %v2.addr, align 16 # | %0 = load <8 x i16>, ptr %v1.addr, align 16 # | %1 = load <8 x i16>, ptr %v2.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | %2 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | %3 = load <8 x i16>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <8 x i16> %2, %3 # | store <8 x i16> %sub.i, ptr %__ret.i, align 16 # | %4 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_s32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vsubq_s32(<4 x i32> noundef %v1, <4 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v1.addr = alloca <4 x i32>, align 16 # | %v2.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %v1, ptr %v1.addr, align 16 # | store <4 x i32> %v2, ptr %v2.addr, align 16 # | %0 = load <4 x i32>, ptr %v1.addr, align 16 # | %1 = load <4 x i32>, ptr %v2.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | %2 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | %3 = load <4 x i32>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <4 x i32> %2, %3 # | store <4 x i32> %sub.i, ptr %__ret.i, align 16 # | %4 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_s64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | store <1 x i64> %v2, ptr %v2.addr, align 8 # | %0 = load <1 x i64>, ptr %v1.addr, align 8 # | %1 = load <1 x i64>, ptr %v2.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | %3 = load <1 x i64>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <1 x i64> %2, %3 # | store <1 x i64> %sub.i, ptr %__ret.i, align 8 # | %4 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vsubq_s64(<2 x i64> noundef %v1, <2 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 16 # | %__p1.addr.i = alloca <2 x i64>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v1.addr = alloca <2 x i64>, align 16 # | %v2.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %v1, ptr %v1.addr, align 16 # | store <2 x i64> %v2, ptr %v2.addr, align 16 # | %0 = load <2 x i64>, ptr %v1.addr, align 16 # | %1 = load <2 x i64>, ptr %v2.addr, align 16 # | store <2 x i64> %0, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__p1.addr.i, align 16 # | %2 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | %3 = load <2 x i64>, ptr %__p1.addr.i, align 16 # | %sub.i = sub <2 x i64> %2, %3 # | store <2 x i64> %sub.i, ptr %__ret.i, align 16 # | %4 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vsub_u8(<8 x i8> noundef %v1, <8 x i8> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v1.addr = alloca <8 x i8>, align 8 # | %v2.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v1, ptr %v1.addr, align 8 # | store <8 x i8> %v2, ptr %v2.addr, align 8 # | %0 = load <8 x i8>, ptr %v1.addr, align 8 # | %1 = load <8 x i8>, ptr %v2.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <8 x i8> %2, %3 # | store <8 x i8> %sub.i, ptr %__ret.i, align 8 # | %4 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vsub_u16(<4 x i16> noundef %v1, <4 x i16> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v1.addr = alloca <4 x i16>, align 8 # | %v2.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %v1, ptr %v1.addr, align 8 # | store <4 x i16> %v2, ptr %v2.addr, align 8 # | %0 = load <4 x i16>, ptr %v1.addr, align 8 # | %1 = load <4 x i16>, ptr %v2.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x i16>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <4 x i16> %2, %3 # | store <4 x i16> %sub.i, ptr %__ret.i, align 8 # | %4 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsub_u32(<2 x i32> noundef %v1, <2 x i32> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %v1.addr = alloca <2 x i32>, align 8 # | %v2.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %v1, ptr %v1.addr, align 8 # | store <2 x i32> %v2, ptr %v2.addr, align 8 # | %0 = load <2 x i32>, ptr %v1.addr, align 8 # | %1 = load <2 x i32>, ptr %v2.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | %2 = load <2 x i32>, ptr %__p0.addr.i, align 8 # | %3 = load <2 x i32>, ptr %__p1.addr.i, align 8 # | %sub.i = sub <2 x i32> %2, %3 # | store <2 x i32> %sub.i, ptr %__ret.i, align 8 # | %4 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vsub_u64(<1 x i64> noundef %v1, <1 x i64> noundef %v2) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v1.addr = alloca <1 x i64>, align 8 # | %v2.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %v1, ptr %v1.addr, align 8 # | # | ... # `---data was truncated (10240/170019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x0000557397f7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557397f720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557397f7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe389f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe389f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe389f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe389f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557397f0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557397f0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557397eefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557397b9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557397b9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe389f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe389f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe389f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557397b9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/subtraction.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c (1758 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/14461) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c6888715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c688840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c6888789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81fbe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81fbea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81fbe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81fbe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c6881ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c6881cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c68801b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c684b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c684b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81fbe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81fbe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81fbe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c684b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c (1759 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdiv.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c (1760 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c (1761 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr % # | ... # `---data was truncated (10240/67150) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056285917315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005628591700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056285917389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97d2649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97d26a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97d2649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97d2631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562859108e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562859108c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005628590edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562858d9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562858d9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97d2632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97d26330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97d26330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562858d9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c (1762 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c (1763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8052fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8052f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8052fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe4c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe4c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe4c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe4c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e805291e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e805291c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e805276b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e804f260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e804f25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe4c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe4c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe4c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e804f25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c (1764 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, # | ... # `---data was truncated (10240/28354) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d588ce115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d588cde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d588ce189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efcf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efcf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efcf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efcf5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d588c76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d588c76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d588c5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d58890b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d58890add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efcf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efcf52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efcf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d58890acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c (1765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulh_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c (1766 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c (1767 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 5) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 5) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 18) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, splat (i8 3) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, splat (i16 11) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, splat (i32 7) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = shl <16 x i8> %0, zeroinitializer # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = shl <8 x i16> %0, zeroinitializer # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = shl <4 x i32> %0, zeroinitializer # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 4) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 19) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_s8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = ashr <16 x i8> %0, splat (i8 7) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_s16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = ashr <8 x i16> %0, splat (i16 15) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_s32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = ashr <4 x i32> %0, splat (i32 31) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = lshr <16 x i8> %0, splat (i8 1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = lshr <8 x i16> %0, splat (i16 10) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = lshr <4 x i32> %0, splat (i32 10) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshrq_n_u8_trivial(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | ret <16 x i8> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshrq_n_u16_trivial(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | ret <8 x i16> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshrq_n_u32_trivial(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | ret <4 x i32> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8> %0, i32 6, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16> %0, i32 13, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.shl.imm.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinlin # | ... # `---data was truncated (10240/66359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055567d3f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055567d3ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055567d3f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe60e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe60e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe60e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe60e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055567d385e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055567d385c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055567d36ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055567d01a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055567d019dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe60e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe60e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe60e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055567d019cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c (1768 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = loa # | ... # `---data was truncated (10240/23447) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f52196315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5219600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f52196389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff485649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff485649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff485631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5218f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5218f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5218ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f52158d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f52158cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff485632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4856330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f52158ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c (1769 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/11969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634d213c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005634d21390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005634d213c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4415b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4415b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4415b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4415b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634d20d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005634d20d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005634d20b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005634d1d660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005634d1d65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4415b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4415b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4415b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634d1d65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c (1770 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpairo.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056504911a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650491170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056504911a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fefff133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fefff18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fefff133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fefff11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650490afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650490afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565049094b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565048d440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565048d43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fefff11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fefff11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fefff11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565048d43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c (1771 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %v # | ... # `---data was truncated (10240/23064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cd325d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556cd325a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556cd325d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24bcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24bcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24bcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24bcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cd31f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556cd31f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556cd31d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556cd2e870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556cd2e86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f24bcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24bcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24bcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cd2e86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c (1772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba8133715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba813340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba8133789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3639b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3639b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3639b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3639b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba812cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba812ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba812b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba80f610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba80f60dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3639b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3639b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3639b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba80f60cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c (1773 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %o # | ... # `---data was truncated (10240/223855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055927357a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005592735770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055927357a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d6ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d6ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d6ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d6ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055927350fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055927350fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005592734f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592731a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005592731a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d6ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d6ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d6ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592731a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c (1774 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cce5b1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cce5b0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cce5b1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f682381bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68238725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f682381ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6823803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cce5aa5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cce5aa5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cce5a8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cce573a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cce5739dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6823804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68238050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68238050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cce5739cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c (1775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei8_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/136005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056067dedd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056067deda0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056067dedd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3591449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f35914a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3591449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3591431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056067de72e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056067de72c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056067de57b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056067db070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056067db06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3591432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f35914330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f35914330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056067db06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c (1776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649c18fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005649c18f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005649c18fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97c7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97c76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97c7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97c7631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649c1890e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005649c1890c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005649c1875b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649c15250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649c1524dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97c7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97c76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97c76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649c1524cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c (1777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, al # | ... # `---data was truncated (10240/128416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556091ca115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556091c9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556091ca189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe05a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe05a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe05a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe05a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556091c36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556091c36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556091c1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560918cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560918cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe05a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe05a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe05a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560918cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c (1778 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005560da77215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005560da76f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005560da77289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb424049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4240a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb424049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb424031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005560da707e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005560da707c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005560da6ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005560da39c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005560da39bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb424032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4240330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4240330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005560da39bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c (1779 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv1 # | ... # `---data was truncated (10240/47628) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055609a19515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055609a1920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055609a19589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5569133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f556918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5569133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f556911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055609a12ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055609a12ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055609a10fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556099dbf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556099dbedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f556911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f556911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f556911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556099dbecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c (1780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c (1781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d61cf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d61cf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d61cf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f3c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f3c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f3c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f3c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d61c8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d61c8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d61c73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d619230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d61922dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f3c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f3c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f3c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d61922cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c (1782 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056312a98615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056312a9830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056312a98689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b95133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b9518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b95133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b9511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056312a91be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056312a91bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056312a900b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056312a5b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056312a5afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2b9511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b9511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b9511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056312a5afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c (1783 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m2_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m2_f32m4( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_bf16m4_f32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_bf16m4_f32m8( %v # | ... # `---data was truncated (10240/43948) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f1a53815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f1a5350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f1a53889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8178733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f817878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8178733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f817871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f1a4cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f1a4cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f1a4b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f1a1620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f1a161dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f817871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f817871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f817871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f1a161cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c (1784 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %0, i32 %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %0, i32 %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 %2, <16 x i1> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i32, ptr %b.addr, align 4 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %0, i32 %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %0, i32 %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055951920015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595191fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055951920089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc036e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc036ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc036e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc036e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559519195e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559519195c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055951917ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559518e2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559518e29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc036e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc036e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc036e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559518e29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c (1785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c (1786 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, a # | ... # `---data was truncated (10240/30276) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0ce0f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0ce0ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e0ce0f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09ecf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09ecf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09ecf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09ecf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0ce087e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e0ce087c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e0ce06cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e0cdd1c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e0cdd1bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f09ecf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09ecf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09ecf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0cdd1bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c (1787 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c0d78315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c0d7800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c0d78389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa58bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa58bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa58bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa58bced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c0d718e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c0d718c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c0d6fdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c0d3ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c0d3acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa58bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa58bcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa58bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c0d3accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c (1788 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556887e7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556887e700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556887e7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9458e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9458ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9458e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9458e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556887e08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556887e08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556887dedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556887a9d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556887a9cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9458e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9458e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9458e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556887a9ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c (1789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c (1790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c (1791 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6dafde15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6dafdb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6dafde89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f47f1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f47f12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f47f1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47f1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6daf73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c6daf73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c6daf58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6dac080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c6dac07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f47f1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47f12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47f12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6dac07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c (1792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8 # | ... # `---data was truncated (10240/96911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588c8f1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588c8f140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588c8f1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5306d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5306d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5306d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5306d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588c8eace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588c8eacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588c8e91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588c8b410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588c8b40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5306d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5306d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5306d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588c8b40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c (1793 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b44483215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b44482f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b44483289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1282333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f128238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1282333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f128231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4447c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4447c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4447acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b44445c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b44445bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f128231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f128231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f128231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b44445bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c (1794 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d135ace15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d135acb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d135ace89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ac4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ac4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ac4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ac4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d135a63e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d135a63c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d135a48b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d1356f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d1356f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ac4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ac4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ac4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1356f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c (1795 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf2_vi_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf2.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf2.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569a1ad015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569a1acd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569a1ad089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde3161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde316725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde3161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde31603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569a1a65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569a1a65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569a1a4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569a16fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569a16f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde31604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde316050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde316050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569a16f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c (1796 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5485d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5485d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5485d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa882d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa882d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa882d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa882d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f548569e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f548569c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f54854eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5481fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5481fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa882d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa882d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa882d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5481fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c (1797 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c (1798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc4a31a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc4a3170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc4a31a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf35b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf35b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf35b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf35b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc4a2afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc4a2afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc4a294b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc49f440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc49f43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf35b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf35b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf35b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc49f43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c (1799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055caeee8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055caeee820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055caeee8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03c9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03c918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03c9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03c911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055caeee1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055caeee1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055caeedffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055caeeaaf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055caeeaaedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f03c911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03c911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03c911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055caeeaaecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c (1800 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkc -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmul_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.clmul.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @clmulh_32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.clmulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.clmul.i32(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.clmulh.i32(i32, i32) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkc" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkc1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580e283215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580e282f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580e283289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c41333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c4138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c41333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c4131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580e27c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580e27c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580e27acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580e245c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580e245bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c4131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c4131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c4131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580e245bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkc.c -check-prefix=RV32ZBKC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c (1801 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c (1802 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624412cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624412c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624412cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5686449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56864a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5686449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5686431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562441261e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562441261c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562441246b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562440ef60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562440ef5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5686432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56864330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56864330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562440ef5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c (1803 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9f04d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9f04d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9f04d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fada3849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fada38a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fada3849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fada3831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9f046ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9f046cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9f0451b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9f01010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9f0100dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fada3832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fada38330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fada38330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9f0100cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c (1804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m8_f8e4m3m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c (1805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwsubu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c (1806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055940fd3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055940fd380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055940fd3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa51e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa51e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa51e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa51e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055940fcd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055940fcd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055940fcb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055940f9650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055940f964dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa51e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa51e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa51e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055940f964cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c (1807 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, fl # | ... # `---data was truncated (10240/25099) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8fad7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8fad7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8fad7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6599b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6599b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6599b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6599b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8fad13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c8fad13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c8facf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8fa9a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8fa9a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6599b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6599b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6599b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8fa9a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c (1808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_f16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_i16m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e16_v_u16mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local vo # | ... # `---data was truncated (10240/26928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8fa2da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8fa2d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8fa2da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b2c049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b2c0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b2c049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b2c031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8fa26fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8fa26fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8fa254b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8f9f040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8f9f03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b2c032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b2c0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b2c0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f9f03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c (1809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/66557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055732670115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573266fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055732670189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fe2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fe298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fe2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fe291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557326696e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557326696c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055732667bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055732632b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055732632add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8fe291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fe291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fe291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055732632acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c (1810 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559dadf4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559dadf440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559dadf4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b34733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b3478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b34733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b3471b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559dadedce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559dadedcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559dadec1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559dadb710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559dadb70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b3471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b3471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b3471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559dadb70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/cx-complex-range.c (1811 of 27911) ******************** TEST 'Clang :: CodeGen/cx-complex-range.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %coerce.real, ptr %retval.realp, align 4 # | store float %coerce.imag, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__divsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %call = call <2 x float> @__divsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %coerce.real, ptr %.realp1, align 4 # | store float %coerce.imag, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulf(<2 x float> noundef %a.coerce, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul_ac = fmul float %a.real, %b.real # | %mul_bd = fmul float %a.imag, %b.imag # | %mul_ad = fmul float %a.real, %b.imag # | %mul_bc = fmul float %a.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %a.real, float noundef %a.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %real_mul_phi, ptr %retval.realp, align 4 # | store float %imag_mul_phi, ptr %retval.imagp, align 4 # | %0 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %0 # | } # | # | declare <2 x float> @__mulsc3(float, float, float, float) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %b = alloca { float, float }, align 4 # | %a.addr = alloca ptr, align 8 # | %coerce = alloca { float, float }, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store ptr %a, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %0 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul_ac = fmul float %.real, %b.real # | %mul_bd = fmul float %.imag, %b.imag # | %mul_ad = fmul float %.real, %b.imag # | %mul_bc = fmul float %.imag, %b.real # | %mul_r = fsub float %mul_ac, %mul_bd # | %mul_i = fadd float %mul_ad, %mul_bc # | %isnan_cmp = fcmp uno float %mul_r, %mul_r # | br i1 %isnan_cmp, label %complex_mul_imag_nan, label %complex_mul_cont, !prof !2 # | # | complex_mul_imag_nan: ; preds = %entry # | %isnan_cmp1 = fcmp uno float %mul_i, %mul_i # | br i1 %isnan_cmp1, label %complex_mul_libcall, label %complex_mul_cont, !prof !2 # | # | complex_mul_libcall: ; preds = %complex_mul_imag_nan # | %call = call <2 x float> @__mulsc3(float noundef %.real, float noundef %.imag, float noundef %b.real, float noundef %b.imag) #2 # | store <2 x float> %call, ptr %coerce, align 4 # | %coerce.realp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 0 # | %coerce.real = load float, ptr %coerce.realp, align 4 # | %coerce.imagp = getelementptr inbounds nuw { float, float }, ptr %coerce, i32 0, i32 1 # | %coerce.imag = load float, ptr %coerce.imagp, align 4 # | br label %complex_mul_cont # | # | complex_mul_cont: ; preds = %complex_mul_libcall, %complex_mul_imag_nan, %entry # | %real_mul_phi = phi float [ %mul_r, %entry ], [ %mul_r, %complex_mul_imag_nan ], [ %coerce.real, %complex_mul_libcall ] # | %imag_mul_phi = phi float [ %mul_i, %entry ], [ %mul_i, %complex_mul_imag_nan ], [ %coerce.imag, %complex_mul_libcall ] # | %.realp2 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 0 # | %.imagp3 = getelementptr inbounds nuw { float, float }, ptr %0, i32 0, i32 1 # | store float %real_mul_phi, ptr %.realp2, align 4 # | store float %imag_mul_phi, ptr %.imagp3, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b.coerce0, double noundef %b.coerce1) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b = alloca { double, double }, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | %2 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %2, align 8 # | %3 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %3, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load doub # | ... # `---data was truncated (10240/29171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x0000563d3646d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d3646a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d3646d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1aad049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1aad0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1aad049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1aad031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d36402e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d36402c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d363e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d360970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d36096dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1aad032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1aad0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1aad0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d36096cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c (1812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vclz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bbe9ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560bbe9a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560bbe9ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aa9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aa96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aa9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aa9631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bbe940e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560bbe940c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560bbe925b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560bbe5d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560bbe5d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0aa9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aa96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aa96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bbe5d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c (1813 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c (1814 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmseq.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmseq_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64( %0, # | ... # `---data was truncated (10240/171381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005628d245415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005628d24510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005628d245489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb210b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb210b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb210b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb210b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628d23e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005628d23e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005628d23ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005628d207e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005628d207ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb210b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb210b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb210b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628d207dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c (1815 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629de0d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629de0cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005629de0d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f816df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f816df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f816df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f816df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629de065e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005629de065c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005629de04ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629ddcfa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629ddcf9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f816df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f816df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f816df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629ddcf9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c (1816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9370f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9370ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9370f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c7bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c7bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c7bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c7bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a937087e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a937087c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a93706cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a936d1c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a936d1bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c7bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c7bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c7bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a936d1bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c (1817 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562714d5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562714d560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562714d5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c70849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c708a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c70849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c70831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562714ceee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562714ceec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562714cd3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627149830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562714982dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c70832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c708330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c708330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562714982cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c (1818 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | # | ... # `---data was truncated (10240/23061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1762c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1762bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1762c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbea341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbea34725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbea341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbea3403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f176257e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f176257c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f17623cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f175eec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f175eebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbea3404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbea34050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbea34050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f175eebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c (1819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639ec89515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639ec8920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639ec89589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f10d8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f10d875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f10d8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f10d86ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639ec82ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639ec82ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639ec80fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639ec4bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639ec4bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f10d86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f10d86ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f10d86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639ec4becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c (1820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3953c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3953be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3953c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c15e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c15ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c15e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c15e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c395356e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c395356c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c39533bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c394feb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c394feadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3c15e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c15e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c15e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c394feacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c (1821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64( poison # | ... # `---data was truncated (10240/18569) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630ffdff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630ffdfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005630ffdff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88c3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630ffd94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005630ffd94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005630ffd79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005630ffa290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005630ffa28dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f88c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630ffa28cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c (1822 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624bfbfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624bfbfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624bfbfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2362333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f236238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2362333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f236231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624bfb92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624bfb92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624bfb77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624bf8270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624bf826dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f236231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f236231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f236231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624bf826cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c (1823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005562f80fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005562f80f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005562f80fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63feb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63feb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63feb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63feb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562f8090e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005562f8090c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005562f8075b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005562f7d250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005562f7d24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63feb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63feb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63feb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005562f7d24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c (1824 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclz_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclz.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c (1825 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, a # | ... # `---data was truncated (10240/81515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c6966515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c696620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c6966589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0909d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0909d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0909d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0909ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c695fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c695fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c695dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c6928f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c6928edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0909ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0909cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0909cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c6928ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c (1826 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_ # | ... # `---data was truncated (10240/23574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560865df315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560865df00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560865df389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ed1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ed10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ed1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ed1031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560865d88e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560865d88c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560865d6db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560865a1d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560865a1cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ed1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ed10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ed10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560865a1ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c (1827 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e5m2_e4m3_w4_f8e5m2m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e5m2.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627b9fcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627b9fc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627b9fcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dccb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dccb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dccb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dccb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627b9f60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005627b9f60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005627b9f45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627b9bf50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627b9bf4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2dccb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dccb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dccb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627b9bf4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c (1828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/23487) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a5d67e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557a5d67b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557a5d67e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2953449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29534a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2953449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2953431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a5d613e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557a5d613c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557a5d5f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557a5d2a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557a5d2a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2953432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29534330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29534330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a5d2a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c (1829 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree no # | ... # `---data was truncated (10240/13023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056450ff7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056450ff730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056450ff7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f978521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97852725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f978521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9785203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056450ff0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056450ff0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056450fef0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056450fba00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056450fb9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9785204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97852050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97852050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056450fb9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c (1830 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 # | ... # `---data was truncated (10240/14429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e19b7e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e19b7e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e19b7e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f027bc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f027bc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f027bc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f027bc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e19b77ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e19b77cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e19b761b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e19b4110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e19b410dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f027bc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f027bc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f027bc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e19b410cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c (1831 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c (1832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595743ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595743e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595743ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3351f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3351f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3351f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3351f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559574381e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559574381c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559574366b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595740160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559574015dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3351f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3351f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3351f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559574015cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c (1833 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e409ca615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e409ca30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e409ca689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb399105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb39915c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb399105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3990ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e409c3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e409c3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e409c20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e4098d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e4098cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb3990eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3990ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3990ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e4098cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c (1834 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055564855715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005556485540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055564855789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8a6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8a6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8a6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8a6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556484ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005556484ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005556484d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005556481810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555648180dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff8a6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8a6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8a6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555648180cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c (1835 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056515217415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005651521710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056515217489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f51b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f51b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f51b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f51b6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565152109e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565152109c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005651520eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565151d9e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565151d9ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f51b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f51b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f51b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565151d9dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm_acle.c (1836 of 27911) ******************** TEST 'Clang :: CodeGen/arm_acle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple armv8a-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8a-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dmb() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dsb() #0 { # | entry: # | call void @llvm.arm.dsb(i32 2) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_isb() #0 { # | entry: # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pld() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pldx() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_pli() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_plix() #0 { # | entry: # | call void @llvm.prefetch.p0(ptr null, i32 0, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ror(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 32 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i32, ptr %__x.addr.i, align 4 # | store i32 %4, ptr %retval.i, align 4 # | br label %__ror.exit # | # | if.end.i: ; preds = %entry # | %5 = load i32, ptr %__x.addr.i, align 4 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %shr.i = lshr i32 %5, %6 # | %7 = load i32, ptr %__x.addr.i, align 4 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 32, %8 # | %shl.i = shl i32 %7, %sub.i # | %or.i = or i32 %shr.i, %shl.i # | store i32 %or.i, ptr %retval.i, align 4 # | br label %__ror.exit # | # | __ror.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i32, ptr %retval.i, align 4 # | ret i32 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rorl(i32 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i.i = alloca i32, align 4 # | %__x.addr.i.i = alloca i32, align 4 # | %__y.addr.i.i = alloca i32, align 4 # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load i32, ptr %y.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | store i32 %2, ptr %__x.addr.i.i, align 4 # | store i32 %3, ptr %__y.addr.i.i, align 4 # | %4 = load i32, ptr %__y.addr.i.i, align 4 # | %rem.i.i = urem i32 %4, 32 # | store i32 %rem.i.i, ptr %__y.addr.i.i, align 4 # | %5 = load i32, ptr %__y.addr.i.i, align 4 # | %cmp.i.i = icmp eq i32 %5, 0 # | br i1 %cmp.i.i, label %if.then.i.i, label %if.end.i.i # | # | if.then.i.i: ; preds = %entry # | %6 = load i32, ptr %__x.addr.i.i, align 4 # | store i32 %6, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | if.end.i.i: ; preds = %entry # | %7 = load i32, ptr %__x.addr.i.i, align 4 # | %8 = load i32, ptr %__y.addr.i.i, align 4 # | %shr.i.i = lshr i32 %7, %8 # | %9 = load i32, ptr %__x.addr.i.i, align 4 # | %10 = load i32, ptr %__y.addr.i.i, align 4 # | %sub.i.i = sub i32 32, %10 # | %shl.i.i = shl i32 %9, %sub.i.i # | %or.i.i = or i32 %shr.i.i, %shl.i.i # | store i32 %or.i.i, ptr %retval.i.i, align 4 # | br label %__rorl.exit # | # | __rorl.exit: ; preds = %if.then.i.i, %if.end.i.i # | %11 = load i32, ptr %retval.i.i, align 4 # | ret i32 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_rorll(i64 noundef %x, i32 noundef %y) #0 { # | entry: # | %retval.i = alloca i64, align 8 # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i32, align 4 # | %x.addr = alloca i64, align 8 # | %y.addr = alloca i32, align 4 # | store i64 %x, ptr %x.addr, align 8 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load i64, ptr %x.addr, align 8 # | %1 = load i32, ptr %y.addr, align 4 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__y.addr.i, align 4 # | %rem.i = urem i32 %2, 64 # | store i32 %rem.i, ptr %__y.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %cmp.i = icmp eq i32 %3, 0 # | br i1 %cmp.i, label %if.then.i, label %if.end.i # | # | if.then.i: ; preds = %entry # | %4 = load i64, ptr %__x.addr.i, align 8 # | store i64 %4, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | if.end.i: ; preds = %entry # | %5 = load i64, ptr %__x.addr.i, align 8 # | %6 = load i32, ptr %__y.addr.i, align 4 # | %sh_prom.i = zext i32 %6 to i64 # | %shr.i = lshr i64 %5, %sh_prom.i # | %7 = load i64, ptr %__x.addr.i, align 8 # | %8 = load i32, ptr %__y.addr.i, align 4 # | %sub.i = sub i32 64, %8 # | %sh_prom1.i = zext i32 %sub.i to i64 # | %shl.i = shl i64 %7, %sh_prom1.i # | %or.i = or i64 %shr.i, %shl.i # | store i64 %or.i, ptr %retval.i, align 8 # | br label %__rorll.exit # | # | __rorll.exit: ; preds = %if.then.i, %if.end.i # | %9 = load i64, ptr %retval.i, align 8 # | ret i64 %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clz(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzl(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_clzll(i64 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i64, align 8 # | %t.addr = alloca i64, align 8 # | store i64 %t, ptr %t.addr, align 8 # | %0 = load i64, ptr %t.addr, align 8 # | store i64 %0, ptr %__t.addr.i, align 8 # | %1 = load i64, ptr %__t.addr.i, align 8 # | %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false) # | %3 = trunc i64 %2 to i32 # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls(i32 noundef %t) #0 { # | entry: # | %__t.addr.i = alloca i32, align 4 # | %t.addr = alloca i32, align 4 # | store i32 %t, ptr %t.addr, align 4 # | %0 = load i32, ptr %t.addr, align 4 # | store i32 %0, ptr %__t.addr.i, align 4 # | %1 = load i32, ptr %__t.addr.i, align 4 # | %cls.i = call i32 @llvm.arm.cls(i32 %1) # | ret i32 %cls.i # | } # | # | ; Function Attrs: noinline # | ... # `---data was truncated (10240/86891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056534a7a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056534a79d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056534a7a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabe1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabe18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabe1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabe1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056534a735e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056534a735c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056534a71ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056534a3ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056534a3c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fabe1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabe18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabe18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056534a3c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle.c -check-prefixes=ARM,AArch32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c (1837 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f6827d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f6827a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f6827d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0562449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f05624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0562449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0562431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f68212e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f68212c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f681f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f67ea70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f67ea6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0562432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f05624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f05624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f67ea6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c (1838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotu_vv_u64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotu.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624471a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624471a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624471a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4a3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4a30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4a3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4a3031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056244713de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056244713dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562447122b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562446dd20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562446dd1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa4a3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4a30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4a30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562446dd1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c (1839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff # | ... # `---data was truncated (10240/44185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055842f01b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055842f0180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055842f01b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbacf133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbacf18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbacf133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbacf11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055842efb0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055842efb0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055842ef95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055842ec450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055842ec44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbacf11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbacf11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbacf11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055842ec44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c (1840 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmacc_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b3292015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b3291d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b3292089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdfa0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdfa04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdfa0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdfa0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b328b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b328b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b3289ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b3254a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b32549dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdfa0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdfa04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdfa04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b32549cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c (1841 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055700cf9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055700cf8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055700cf9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd61733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd6178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd61733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd6171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055700cf27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055700cf27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055700cf0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055700cbbc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055700cbbbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd6171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd6171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd6171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055700cbbbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c (1842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbac58d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cbac58a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cbac58d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f19449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f194a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f19449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f19431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbac522e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cbac522c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cbac507b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cbac1b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cbac1b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f19432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f194330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f194330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbac1b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c (1843 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/26976) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d8271915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d827160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d8271989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40ae105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40ae15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40ae105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40ae0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d826aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d826aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d82693b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d823430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d82342dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f40ae0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40ae0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40ae0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d82342cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGenCXX/ctor-globalopt.cpp (1844 of 27911) ******************** TEST 'Clang :: CodeGenCXX/ctor-globalopt.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp -O2 # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.B = type <{ ptr, i32, [4 x i8], %struct.A.base, [4 x i8] }> # | %struct.A.base = type <{ ptr, i32 }> # | # | @b = local_unnamed_addr global %struct.B <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 24), i32 0, [4 x i8] zeroinitializer, %struct.A.base <{ ptr getelementptr inbounds inrange(-24, 8) (i8, ptr @_ZTV1B, i64 56), i32 0 }>, [4 x i8] zeroinitializer }>, align 8 # | @_ZTV1B = external constant { [4 x ptr], [4 x ptr] }, align 8 # | @llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer # | # | !llvm.ident = !{!0} # | !llvm.errno.tbaa = !{!1} # | # | !0 = !{!"clang version 24.0.0"} # | !1 = !{!2, !3, i64 0} # | !2 = !{!"__libc_errno", !3, i64 0} # | !3 = !{!"int", !4, i64 0} # | !4 = !{!"omnipotent char", !5, i64 0} # | !5 = !{!"Simple C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S -passes=globalopt -o - # | #0 0x000055e023ea515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e023ea20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e023ea589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda87b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda87b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda87b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda87b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e023e3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e023e3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e023e1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e023acf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e023acedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fda87b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda87b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda87b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e023acecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/ctor-globalopt.cpp --check-prefix=O1 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c (1845 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf8_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf4_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8mf2_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vx_u8m1_tu( %maskedoff, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vandn.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vandn.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vandn_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | # | ... # `---data was truncated (10240/223129) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a07a8dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a07a8da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a07a8dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3aeb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3aeb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3aeb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3aeaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a07a872e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a07a872c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a07a857b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a07a5070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a07a506dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa3aeaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3aeaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3aeaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a07a506cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/memcmp-inline-builtin-to-asm.c (1846 of 27911) ******************** TEST 'Clang :: CodeGen/memcmp-inline-builtin-to-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | @con_unify_unimap_p1 = global ptr null, align 8 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @con_unify_unimap_q1() #0 { # | entry: # | %p.addr.i = alloca ptr, align 8 # | %q.addr.i = alloca ptr, align 8 # | %size.addr.i = alloca i64, align 8 # | %0 = load ptr, ptr @con_unify_unimap_p1, align 8 # | store ptr %0, ptr %p.addr.i, align 8 # | store ptr @con_unify_unimap_q1, ptr %q.addr.i, align 8 # | store i64 4, ptr %size.addr.i, align 8 # | %1 = load ptr, ptr %p.addr.i, align 8 # | %2 = load ptr, ptr %q.addr.i, align 8 # | %3 = load i64, ptr %size.addr.i, align 8 # | %call.i = call i32 @memcmp(ptr noundef %1, ptr noundef %2, i64 noundef %3) #2 # | ret i32 %call.i # | } # | # | ; Function Attrs: alwaysinline nobuiltin nounwind # | declare i32 @memcmp(ptr noundef, ptr noundef, i64 noundef) #1 # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { alwaysinline nobuiltin nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #2 = { nounwind } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=verify # | #0 0x00005628ea1bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005628ea1ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005628ea1bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6220f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6220f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6220f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6220f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005628ea152e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005628ea152c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005628ea137b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005628e9de70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005628e9de6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6220f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6220f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6220f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005628e9de6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/memcmp-inline-builtin-to-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c (1847 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8m1( %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmerge.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m2( %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca # | ... # `---data was truncated (10240/124506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560cbe18b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560cbe1880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560cbe18b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bc5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bc558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bc5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bc551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560cbe120e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560cbe120c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560cbe105b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560cbddb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560cbddb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5bc551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bc551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bc551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560cbddb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c (1848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m1_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vx_bf16m2_tu( %vd, %vs2, i64 noundef %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8bf16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8bf16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgather_vv_bf16m4_tu( %vd, %vs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c (1849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e5b93ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e5b93aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e5b93ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc07921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0792725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc07921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc079203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e5b9342e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e5b9342c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e5b9327b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e5b8fd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e5b8fd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc079204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0792050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0792050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e5b8fd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c (1850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590d457d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590d457a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590d457d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa246705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa24675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa246705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2466ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005590d4512e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005590d4512c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005590d44f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590d41a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005590d41a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2466eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2466ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2466ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005590d41a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c (1851 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558cd8f1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558cd8f120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558cd8f1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd470733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd47078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd470733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd47071b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cd8eaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558cd8eaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558cd8e8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558cd8b3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558cd8b3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd47071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd47071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd47071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558cd8b3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c (1852 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range # | ... # `---data was truncated (10240/24990) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560139a3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560139a2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560139a3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b7af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b7af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b7af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b7af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005601399c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005601399c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005601399acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056013965c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056013965bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b7af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b7af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b7af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056013965bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c (1853 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t. # | ... # `---data was truncated (10240/15486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e867ea115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e867e9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e867ea189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa7c7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa7c78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa7c7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa7c7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e867e36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e867e36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e867e1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e867acb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e867acadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa7c7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa7c78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa7c78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e867acacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c (1854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsm # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c8c38e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561c8c38b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561c8c38e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f066c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f066c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f066c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f066c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c8c323e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561c8c323c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561c8c308b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561c8bfb80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561c8bfb7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f066c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f066c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f066c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c8bfb7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c (1855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry # | ... # `---data was truncated (10240/14002) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a79fd3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a79fd350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a79fd3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc137a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc137aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc137a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc137a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a79fccde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a79fccdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a79fcb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a79f9620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a79f961dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc137a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc137a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc137a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a79f961cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c (1856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056295484915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629548460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056295484989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f366ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f366cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f366ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f366ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629547dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005629547dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005629547c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629544730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562954472dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f366ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f366ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f366ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562954472cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c (1857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a0edb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a0edaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a0edb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9b8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9b875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9b8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9b86ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a0ed47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a0ed47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a0ed2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a0e9dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a0e9dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb9b86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9b86ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9b86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a0e9dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c (1858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c (1859 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xtheadbb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.ctlz.i32(i32 %0, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.ctlz.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_32(i32 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %not = xor i32 %0, -1 # | %1 = call i32 @llvm.ctlz.i32(i32 %not, i1 false) # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clz_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = call i64 @llvm.ctlz.i64(i64 %0, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.ctlz.i64(i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @clo_64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %not = xor i64 %0, -1 # | %1 = call i64 @llvm.ctlz.i64(i64 %not, i1 false) # | %cast = trunc i64 %1 to i32 # | ret i32 %cast # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xtheadbb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xtheadbb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a779c7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a779c710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a779c7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae5f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae5f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae5f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae5f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a779c09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a779c09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a779beeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a77989e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a77989ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae5f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae5f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae5f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a77989dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c -check-prefix=RV64XTHEADBB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c (1860 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei16_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c (1861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634ebdd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005634ebdcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005634ebdd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa84133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa8418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa84133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa8411b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634ebd65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005634ebd65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005634ebd4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005634eb9fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005634eb9f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa8411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa8411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa8411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634eb9f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c (1862 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask. # | ... # `---data was truncated (10240/28162) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056221db0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056221db000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056221db0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f651aa1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f651aa725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f651aa1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f651aa03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056221da98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056221da98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056221da7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056221d72d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056221d72cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f651aa04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f651aa050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f651aa050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056221d72ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c (1863 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055778ca5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055778ca580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055778ca5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba08d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba08d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba08d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba08d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055778c9f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055778c9f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055778c9d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055778c6850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055778c684dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fba08d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba08d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba08d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055778c684cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c (1864 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; # | ... # `---data was truncated (10240/100289) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fefa7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563fefa6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563fefa7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f156e705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f156e75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f156e705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f156e6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fefa05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563fefa05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563fef9eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563fef69a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563fef699dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f156e6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f156e6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f156e6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fef699cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c (1865 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c223dc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c223dc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c223dc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f784701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78470725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f784701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7847003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c223d5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c223d5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c223d40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2239f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c2239efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7847004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78470050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78470050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2239efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c (1866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, alig # | ... # `---data was truncated (10240/26754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7404b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7404b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c7404b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6309a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6309aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6309a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6309a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c74044de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c74044dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c740432b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7400e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c7400e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6309a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6309a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6309a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7400e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c (1867 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredand.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/94379) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644aef5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644aef550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644aef5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64b6649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64b66a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64b6649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64b6631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644aeeede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644aeeedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644aeed2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644aeb820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644aeb81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64b6632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64b66330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64b66330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644aeb81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c (1868 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @ # | ... # `---data was truncated (10240/60228) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9e1b0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9e1b080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9e1b0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9168d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9168d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9168d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9168d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9e1aa0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9e1aa0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9e1a85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9e17350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9e1734dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9168d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9168d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9168d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9e1734cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c (1869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5) # | ret i64 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvlimax.i64(i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e8m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e16m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32mf2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e32m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m1() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m2() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m4() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2) # | ret i64 %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvlmax_e64m8() #0 { # | entry: # | %0 = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3) # | ret i64 %0 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f522b6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f522b5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f522b6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f2b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f2b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f2b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f2b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f522af6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f522af6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f522adbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f52278b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f52278add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f2b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f2b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f2b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f52278acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c (1870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb5dae315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb5dae00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb5dae389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb224f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb224f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb224f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb224f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb5da78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb5da78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb5da5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb5d70d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb5d70cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb224f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb224f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb224f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb5d70ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c (1871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.v # | ... # `---data was truncated (10240/58683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bcfa2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558bcfa250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558bcfa2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2f5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2f54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2f5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2f5431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bcf9bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558bcf9bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558bcf9a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558bcf6520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558bcf651dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2f5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2f54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2f54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bcf651cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c (1872 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055912e70b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055912e7080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055912e70b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb524849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5248a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb524849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb524831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055912e6a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055912e6a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055912e685b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055912e3350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055912e334dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb524832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5248330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5248330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055912e334cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c (1873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b32acf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b32acf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b32acf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55ddf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55ddf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55ddf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55ddeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b32ac89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b32ac89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b32ac6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b32a91e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b32a91ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f55ddeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55ddeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55ddeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b32a91dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c (1874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558888c7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558888c6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558888c7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81b6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81b68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81b6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81b6831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558888c07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558888c07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558888becb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055888889c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055888889bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81b6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81b68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81b68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055888889bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c (1875 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c33ec7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c33ec6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c33ec7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb468133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb46818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb468133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb46811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c33ec07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c33ec07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c33ebecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c33e89c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c33e89bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb46811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb46811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb46811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c33e89bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c (1876 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = # | ... # `---data was truncated (10240/154509) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555debbbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555debbba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555debbbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f044de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f044dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f044de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f044de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555debb52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555debb52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555debb37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555deb7e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555deb7e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f044de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f044de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f044de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555deb7e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c (1877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , a # | ... # `---data was truncated (10240/98437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617c8b5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005617c8b5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005617c8b5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f672c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f672c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f672c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f672c831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617c8af3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005617c8af3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005617c8ad8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005617c87880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005617c8787dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f672c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f672c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f672c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617c8787cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c (1878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055711d62d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055711d62a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055711d62d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe441305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe44135c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe441305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4412ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055711d5c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055711d5c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055711d5a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055711d2570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055711d256dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe4412eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4412ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4412ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055711d256cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c (1879 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 5, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 immarg, i32 immarg, i32 immarg, i8, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8mf2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m1(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m2(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m4(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u8m8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i8.i32(i32 3, i32 31, i32 31, i8 %0, i32 8, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 6, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 immarg, i32 immarg, i32 immarg, i16, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16mf2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m1(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m2(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m4(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u16m8(i16 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i16, align 2 # | %vl.addr = alloca i32, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i16, ptr %rs1.addr, align 2 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i16.i32(i32 3, i32 31, i32 31, i16 %0, i32 16, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32mf2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 7, i32 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 immarg, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m1(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 0, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m2(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 1, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m4(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 2, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u32m8(i32 noundef %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %vl.addr, align 4 # | call void @llvm.riscv.sf.vc.x.se.i32.i32.i32(i32 3, i32 31, i32 31, i32 %0, i32 32, i32 3, i32 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u8mf8(i8 noundef zeroext %rs1, i32 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i32, align 4 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i32 %vl, ptr %vl.addr, align 4 # | %0 = load i8, ptr %rs1.addr, align 1 # | %1 = load i32, ptr %vl.addr, align 4 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 %0, i32 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | ... # `---data was truncated (10240/66298) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623ec6b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005623ec6ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005623ec6b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbc5705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbc575c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbc5705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbc56ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623ec646e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005623ec646c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005623ec62bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005623ec2db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005623ec2dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffbc56eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbc56ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbc56ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623ec2dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c (1880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_f32m2x3_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c (1881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f95444515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f9544420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f95444589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb17c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb17c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb17c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb17c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9543dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f9543dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f9543bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f95406f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f95406edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb17c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb17c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb17c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f95406ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c (1882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4e41dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4e41da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b4e41dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2b7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2b7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2b7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2b7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4e4172e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4e4172c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4e4157b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4e3e070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b4e3e06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb2b7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2b7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2b7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4e3e06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c (1883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { ta # | ... # `---data was truncated (10240/27858) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055733c26b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055733c2680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055733c26b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bcc049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bcc0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bcc049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bcc031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055733c200e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055733c200c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055733c1e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055733be950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055733be94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bcc032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bcc0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bcc0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055733be94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrnd.c (1884 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrnd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.round.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.round.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.round.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.round.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.floor.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.floor.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.floor.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.floor.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndpq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.ceil.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndpq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.trunc.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.trunc.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndxq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.rint.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.rint.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndxq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.rint.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.rint.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndaq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrinta.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndaq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float>, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vrndmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half> %0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vrintm.predicated.v8f16.v8i1(<8 x half>, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vrndmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1 # | ... # `---data was truncated (10240/26476) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ced42f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ced42ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ced42f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd3781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd378725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd3781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd37803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ced4285e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ced4285c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ced426ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ced3f1a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ced3f19dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd37804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd378050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd378050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ced3f19cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c (1885 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwsub.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c (1886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_tumu( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce1065615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce106530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce1065689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc593a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc593aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc593a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc593a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce105ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce105ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce105d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce102800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce1027fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc593a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc593a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc593a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce1027fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c (1887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055858939e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055858939b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055858939e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99b0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99b02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99b0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99b0231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558589333e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558589333c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558589318b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558588fc80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558588fc7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99b0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99b02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99b02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558588fc7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c (1888 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaaddu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaaddu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaaddu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c (1889 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfvfexp32e,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexp32e0p5"} # | !3 = !{i32 8, !"SmallDataLi # | ... # `---data was truncated (10240/10285) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005571a73c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005571a73c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005571a73c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd780533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd780533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005571a7358e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005571a7358c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005571a733db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005571a6fed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005571a6fecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd78051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005571a6feccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c (1890 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562551cb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562551caf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562551cb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ca2133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ca218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ca2133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ca211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562551c47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562551c47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562551c2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625518dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625518dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ca211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ca211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ca211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625518dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c (1891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c (1892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556d8b7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005556d8b710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005556d8b7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c8a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c8a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c8a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c8a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556d8b09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005556d8b09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005556d8aeeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005556d879e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005556d879ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c8a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c8a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c8a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556d879dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c (1893 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c (1894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7177a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7177a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f7177a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8ae105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8ae15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8ae105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8ae0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f71773de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f71773dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f717722b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f7173d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f7173d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8ae0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8ae0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8ae0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7173d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c (1895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync # | ... # `---data was truncated (10240/62063) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056023d3ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056023d3a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056023d3ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc757849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc757849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc757831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056023d340e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056023d340c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056023d325b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056023cfd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056023cfd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc757832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056023cfd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c (1896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3b65d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3b65d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3b65d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7537c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7537c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7537c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7537c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3b656ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3b656cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3b6551b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3b62010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3b6200dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7537c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7537c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7537c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3b6200cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c (1897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5419d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5419d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5419d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b80133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b8018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b80133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b8011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c54196de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c54196dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c541952b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5416020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c541601dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b8011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b8011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b8011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c541601cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c (1898 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055976565c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597656590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055976565c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0bb505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0bb55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0bb505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0bb4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597655f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597655f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597655d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597652860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559765285dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0bb4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0bb4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0bb4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559765285cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c (1899 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtmq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtmq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtnq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtpq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32, <8 x i16>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtaq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtaq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1( # | ... # `---data was truncated (10240/32505) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f3b41515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562f3b4120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562f3b41589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2383649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23836a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2383649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2383631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f3b3aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562f3b3aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562f3b38fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562f3b03f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562f3b03edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2383632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23836330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23836330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f3b03ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt_anpm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c (1900 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -fclang-abi-compat=latest -target-feature +f32mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,16) # | define dso_local @test_svmmla_f32( %x, %y, %z) #0 { # | entry: # | %x.addr = alloca , align 16 # | %y.addr = alloca , align 16 # | %z.addr = alloca , align 16 # | store %x, ptr %x.addr, align 16 # | store %y, ptr %y.addr, align 16 # | store %z, ptr %z.addr, align 16 # | %0 = load , ptr %x.addr, align 16 # | %1 = load , ptr %y.addr, align 16 # | %2 = load , ptr %z.addr, align 16 # | %3 = call @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32( %0, %1, %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.aarch64.sve.fmmla.nxv4f32.nxv4f32(, , ) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,16) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+sve" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,tailcallelim # | #0 0x000056385f6e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056385f6e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056385f6e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3bfae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3bfae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3bfae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3bfae03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056385f67be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056385f67bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056385f660b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056385f3100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056385f30fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3bfae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3bfae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3bfae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056385f30fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c (1901 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -target-feature +fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_vreinterpret_p8_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__ret.i, align 8 # | %2 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vreinterpret_p64_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <1 x i64>, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__ret.i, align 8 # | %2 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vreinterpret_p16_mf8(<8 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %v.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %v, ptr %v.addr, align 8 # | %0 = load <8 x i8>, ptr %v.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x i16>, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__ret.i, align 8 # | %2 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_p8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i128 @test_vreinterpretq_p128_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca i128, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load i128, ptr %__p0.addr.i, align 16 # | store i128 %1, ptr %__ret.i, align 16 # | %2 = load i128, ptr %__ret.i, align 16 # | ret i128 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_p64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_p16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_u8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_u32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_u64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vreinterpretq_u16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x i16>, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__ret.i, align 16 # | %2 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_s8_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x double> @test_vreinterpretq_f64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x double>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x double>, ptr %__p0.addr.i, align 16 # | store <2 x double> %1, ptr %__ret.i, align 16 # | %2 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vreinterpretq_f32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x float>, ptr %__p0.addr.i, align 16 # | store <4 x float> %1, ptr %__ret.i, align 16 # | %2 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vreinterpretq_f16_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x half>, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__ret.i, align 16 # | %2 = load <8 x half>, ptr %__ret.i, align 16 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vreinterpretq_s32_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <4 x i32>, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__ret.i, align 16 # | %2 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vreinterpretq_s64_mf8(<16 x i8> %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <2 x i64>, ptr %__p0.addr.i, align 16 # | store <2 x i64> %1, ptr %__ret.i, align 16 # | %2 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p8(<16 x i8> noundef %v) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <16 x i8>, align 16 # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | store <16 x i8> %1, ptr %__ret.i, align 16 # | %2 = load <16 x i8>, ptr %__ret.i, align 16 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_vreinterpretq_mf8_p128(i128 noundef %v) #0 { # | entry: # | # | ... # `---data was truncated (10240/32178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,sroa # | #0 0x00005619eae9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005619eae9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619eae9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d25133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d2518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d25133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d2511b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619eae34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005619eae34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005619eae19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619eaac90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619eaac8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d2511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d2511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d2511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619eaac8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c (1902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, % # | ... # `---data was truncated (10240/215941) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005642b179b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005642b17980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005642b179b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd6cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd6cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd6cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd6cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005642b1730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005642b1730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005642b1715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005642b13c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005642b13c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd6cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd6cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd6cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005642b13c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c (1903 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d9b39115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d9b38e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d9b39189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7bf8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7bf875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7bf8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7bf86ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d9b326e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d9b326c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d9b30bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d9afbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d9afbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7bf86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7bf86ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7bf86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d9afbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c (1904 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv1i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c63feee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c63feeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c63feee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feed9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feed90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feed9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feed9031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c63fe83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c63fe83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c63fe68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c63fb180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c63fb17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feed9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feed90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feed90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c63fb17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcvt.c (1905 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = sitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_f16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = uitofp <8 x i16> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = sitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_f32_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = uitofp <4 x i32> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_s16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptosi <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptosi <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_u16_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = fptoui <8 x half> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = fptoui <4 x float> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_s16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 0, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcvtq_m_f16_u16(<8 x half> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = call <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %0, i32 1, <8 x i1> %3, <8 x half> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_s32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcvtq_m_f32_u32(<4 x float> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 1, <4 x i1> %3, <4 x float> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_s16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_s32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %0, i32 0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vcvtq_m_u16_f16(<8 x i16> noundef %inactive, <8 x half> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.vcvt.fp.int.predicated.v8i16.v8f16.v8i1(<8 x half> %0, i32 1, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vcvtq_m_u32_f32(<4 x i32> noundef %inactive, <4 x float> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm # | ... # `---data was truncated (10240/37578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8cef9015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8cef8d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8cef9089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f531f505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f531f55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f531f505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f531f4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8cef25e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c8cef25c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c8cef0ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8cebba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8cebb9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f531f4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f531f4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f531f4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8cebb9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c (1906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056028f34a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056028f3470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056028f34a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f208ad33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f208ad8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f208ad33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f208ad1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056028f2dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056028f2dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056028f2c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056028ef740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056028ef73dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f208ad1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f208ad1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f208ad1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056028ef73cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c (1907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | %1 = fpext bfloat %0 to float # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | %1 = fptrunc float %0 to bfloat # | ret bfloat %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc589e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc589e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc589e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6017305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f601735c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6017305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f60172ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc5897ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc5897ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc5895fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc5860f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc5860edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f60172eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60172ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60172ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc5860ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c (1908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056407de8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056407de890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056407de8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa10781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1078725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa10781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa107803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056407de21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056407de21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056407de06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056407dab60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056407dab5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa107804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1078050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1078050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056407dab5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c (1909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ba79e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ba79e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ba79e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8857333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f885738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8857333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f885731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ba7979e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ba7979c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ba795eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ba760e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ba760ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f885731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f885731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f885731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ba760dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c (1910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d9a94a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d9a9470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d9a94a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf50d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf50d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf50d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf50ced507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d9a8dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d9a8dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d9a8c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d9a5740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d9a573dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf50ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf50cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf50cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d9a573cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm64_vcopy.c (1911 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vcopy.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_336 = alloca <16 x i8>, align 16 # | %__s0_336 = alloca <16 x i8>, align 16 # | %__s2_336 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_336, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_336, align 16 # | %2 = load <16 x i8>, ptr %__s2_336, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_336, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_336, align 16 # | %13 = load <16 x i8>, ptr %__ret_336, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <16 x i8> @test_vcopyq_laneq_u8(<16 x i8> noundef %a1, <16 x i8> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <16 x i8>, align 16 # | %a2.addr = alloca <16 x i8>, align 16 # | %__ret_328 = alloca <16 x i8>, align 16 # | %__s0_328 = alloca <16 x i8>, align 16 # | %__s2_328 = alloca <16 x i8>, align 16 # | %__ret = alloca <16 x i8>, align 16 # | %__s0 = alloca i8, align 1 # | %__ret1 = alloca i8, align 1 # | %__s02 = alloca <16 x i8>, align 16 # | %ref.tmp = alloca i8, align 1 # | %tmp = alloca i8, align 1 # | %__s1 = alloca <16 x i8>, align 16 # | %ref.tmp3 = alloca <16 x i8>, align 16 # | %tmp4 = alloca <16 x i8>, align 16 # | %tmp5 = alloca <16 x i8>, align 16 # | store <16 x i8> %a1, ptr %a1.addr, align 16 # | store <16 x i8> %a2, ptr %a2.addr, align 16 # | %0 = load <16 x i8>, ptr %a1.addr, align 16 # | store <16 x i8> %0, ptr %__s0_328, align 16 # | %1 = load <16 x i8>, ptr %a2.addr, align 16 # | store <16 x i8> %1, ptr %__s2_328, align 16 # | %2 = load <16 x i8>, ptr %__s2_328, align 16 # | store <16 x i8> %2, ptr %__s02, align 16 # | %3 = load <16 x i8>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <16 x i8> %3, i32 13 # | store i8 %vgetq_lane, ptr %ref.tmp, align 1 # | %4 = load i8, ptr %ref.tmp, align 1 # | store i8 %4, ptr %__ret1, align 1 # | %5 = load i8, ptr %__ret1, align 1 # | store i8 %5, ptr %tmp, align 1 # | %6 = load i8, ptr %tmp, align 1 # | store i8 %6, ptr %__s0, align 1 # | %7 = load <16 x i8>, ptr %__s0_328, align 16 # | store <16 x i8> %7, ptr %__s1, align 16 # | %8 = load i8, ptr %__s0, align 1 # | %9 = load <16 x i8>, ptr %__s1, align 16 # | %vset_lane = insertelement <16 x i8> %9, i8 %8, i32 3 # | store <16 x i8> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <16 x i8>, ptr %ref.tmp3, align 16 # | store <16 x i8> %10, ptr %__ret, align 16 # | %11 = load <16 x i8>, ptr %__ret, align 16 # | store <16 x i8> %11, ptr %tmp4, align 16 # | %12 = load <16 x i8>, ptr %tmp4, align 16 # | store <16 x i8> %12, ptr %__ret_328, align 16 # | %13 = load <16 x i8>, ptr %__ret_328, align 16 # | store <16 x i8> %13, ptr %tmp5, align 16 # | %14 = load <16 x i8>, ptr %tmp5, align 16 # | ret <16 x i8> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_s16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_346 = alloca <8 x i16>, align 16 # | %__s0_346 = alloca <8 x i16>, align 16 # | %__s2_346 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_346, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_346, align 16 # | %2 = load <8 x i16>, ptr %__s2_346, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_346, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_346, align 16 # | %13 = load <8 x i16>, ptr %__ret_346, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x i16> @test_vcopyq_laneq_u16(<8 x i16> noundef %a1, <8 x i16> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <8 x i16>, align 16 # | %a2.addr = alloca <8 x i16>, align 16 # | %__ret_334 = alloca <8 x i16>, align 16 # | %__s0_334 = alloca <8 x i16>, align 16 # | %__s2_334 = alloca <8 x i16>, align 16 # | %__ret = alloca <8 x i16>, align 16 # | %__s0 = alloca i16, align 2 # | %__ret1 = alloca i16, align 2 # | %__s02 = alloca <8 x i16>, align 16 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | %__s1 = alloca <8 x i16>, align 16 # | %ref.tmp3 = alloca <8 x i16>, align 16 # | %tmp4 = alloca <8 x i16>, align 16 # | %tmp5 = alloca <8 x i16>, align 16 # | store <8 x i16> %a1, ptr %a1.addr, align 16 # | store <8 x i16> %a2, ptr %a2.addr, align 16 # | %0 = load <8 x i16>, ptr %a1.addr, align 16 # | store <8 x i16> %0, ptr %__s0_334, align 16 # | %1 = load <8 x i16>, ptr %a2.addr, align 16 # | store <8 x i16> %1, ptr %__s2_334, align 16 # | %2 = load <8 x i16>, ptr %__s2_334, align 16 # | store <8 x i16> %2, ptr %__s02, align 16 # | %3 = load <8 x i16>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <8 x i16> %3, i32 7 # | store i16 %vgetq_lane, ptr %ref.tmp, align 2 # | %4 = load i16, ptr %ref.tmp, align 2 # | store i16 %4, ptr %__ret1, align 2 # | %5 = load i16, ptr %__ret1, align 2 # | store i16 %5, ptr %tmp, align 2 # | %6 = load i16, ptr %tmp, align 2 # | store i16 %6, ptr %__s0, align 2 # | %7 = load <8 x i16>, ptr %__s0_334, align 16 # | store <8 x i16> %7, ptr %__s1, align 16 # | %8 = load i16, ptr %__s0, align 2 # | %9 = load <8 x i16>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x i16> %9, i16 %8, i32 3 # | store <8 x i16> %vset_lane, ptr %ref.tmp3, align 16 # | %10 = load <8 x i16>, ptr %ref.tmp3, align 16 # | store <8 x i16> %10, ptr %__ret, align 16 # | %11 = load <8 x i16>, ptr %__ret, align 16 # | store <8 x i16> %11, ptr %tmp4, align 16 # | %12 = load <8 x i16>, ptr %tmp4, align 16 # | store <8 x i16> %12, ptr %__ret_334, align 16 # | %13 = load <8 x i16>, ptr %__ret_334, align 16 # | store <8 x i16> %13, ptr %tmp5, align 16 # | %14 = load <8 x i16>, ptr %tmp5, align 16 # | ret <8 x i16> %14 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x i32> @test_vcopyq_laneq_s32(<4 x i32> noundef %a1, <4 x i32> noundef %a2) #0 { # | entry: # | %a1.addr = alloca <4 x i32>, align 16 # | %a2.addr = alloca <4 x i32>, align 16 # | %__ret_340 = alloca <4 x i32>, align 16 # | %__s0_340 = alloca <4 x i32>, align 16 # | %__s2_340 = alloca <4 x i32>, align 16 # | %__ret = alloca <4 x i32>, align 16 # | %__s0 = alloca i32, align 4 # | %__ret1 = alloca i32, align 4 # | %__s02 = alloca <4 x i32>, align 16 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | %__s1 = alloca <4 x i32>, align 16 # | %ref.tmp3 = alloca <4 x i32>, align 16 # | %tmp4 = alloca <4 x i32>, align 16 # | %tmp5 = alloca <4 x i32>, align 16 # | store <4 x i32> %a1, ptr %a1.addr, align 16 # | store <4 x i32> %a2, ptr %a2.addr, align 16 # | %0 = load <4 x i32>, ptr %a1.addr, align 16 # | store <4 x i32> %0, ptr %__s0_340, align 16 # | %1 = load <4 x i32>, ptr %a2.addr, align 16 # | store <4 x i32> %1, ptr %__s2_340, align 16 # | %2 = load <4 x i32>, ptr %__s2_340, align 16 # | store <4 x i32> %2, ptr %__s02, align 16 # | %3 = load <4 x i32>, ptr %__s02, align 16 # | %vgetq_lane = extractelement <4 x i32> %3, i32 3 # | store i32 %vgetq_lane, ptr %ref.tmp, align 4 # | %4 = load i32, ptr %ref.tmp, align 4 # | store i32 %4, ptr %__ret1, align 4 # | %5 = load i32, ptr %__ret1, align 4 # | store i32 %5, ptr %tmp, align 4 # | %6 = load i32, ptr %tmp, align 4 # | store i32 %6, ptr %__s0, align 4 # | %7 = load <4 x i32> # | ... # `---data was truncated (10240/22011) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558af243715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558af24340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558af243789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd786133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd78618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd786133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd78611b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558af23cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558af23ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558af23b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558af20610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558af2060dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd78611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd78611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd78611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558af2060cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcopy.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c (1912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005630f37c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630f37c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005630f37c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa043505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa04355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa043505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0434ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005630f375be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005630f375bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005630f3740b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005630f33f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005630f33efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0434eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0434ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0434ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005630f33efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c (1913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 # | ... # `---data was truncated (10240/32125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a38180115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3817fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a38180189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6970e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6970ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6970e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6970e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a381796e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a381796c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a38177bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a38142b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a38142add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6970e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6970e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6970e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38142acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c (1914 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d75dfd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d75dfa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d75dfd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f289ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f289aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f289ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f289ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d75d92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d75d92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d75d77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d75a270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d75a26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f289ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f289ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f289ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d75a26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c (1915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmin.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ec531515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ec53120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ec531589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28ce449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28ce4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28ce449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28ce431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ec52aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ec52aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ec528fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ec4f3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ec4f3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28ce432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28ce4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28ce4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ec4f3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c (1916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0e08a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0e089f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0e08a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d5b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d5b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d5b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d5b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0e0837e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0e0837c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f0e081cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0e04cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f0e04cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d5b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d5b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d5b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0e04cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon/vpaddl.c (1917 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/vpaddl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpaddl_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %1) # | store <4 x i16> %vpaddl.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vpaddlq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %1) # | store <8 x i16> %vpaddl.i, ptr %ref.tmp.i, align 16 # | %2 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %2, ptr %__ret.i, align 16 # | %3 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vpaddl_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <4 x i16> # | %vpaddl1.i = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %vpaddl.i) # | store <2 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vpaddlq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <8 x i16> # | %vpaddl1.i = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %vpaddl.i) # | store <4 x i32> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %2, ptr %__ret.i, align 16 # | %3 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <1 x i64> @test_vpaddl_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vpaddl.i = bitcast <8 x i8> %1 to <2 x i32> # | %vpaddl1.i = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %vpaddl.i) # | store <1 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 8 # | %2 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %2, ptr %__ret.i, align 8 # | %3 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_vpaddlq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <2 x i64>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %vpaddl.i = bitcast <16 x i8> %1 to <4 x i32> # | %vpaddl1.i = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %vpaddl.i) # | store <2 x i64> %vpaddl1.i, ptr %ref.tmp.i, align 16 # | %2 = load <2 x i64>, ptr %ref.tmp.i, align 16 # | store <2 x i64> %2, ptr %__ret.i, align 16 # | %3 = load <2 x i64>, ptr %__ret.i, align 16 # | ret <2 x i64> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vpadal_s8(<4 x i16> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <8 x i8>, al # | ... # `---data was truncated (10240/26059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056147f30715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056147f3040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056147f30789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82a7f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82a7f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82a7f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82a7eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056147f29ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056147f29cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056147f281b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056147ef310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056147ef30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f82a7eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82a7eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82a7eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056147ef30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/vpaddl.c --check-prefixes=LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c (1918 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b3e11715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561b3e1140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561b3e11789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dd1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dd1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dd1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dd1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b3e0ace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561b3e0acc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561b3e091b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561b3dd410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561b3dd40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dd1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dd1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dd1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b3dd40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c (1919 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2e # | ... # `---data was truncated (10240/253148) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e958f5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e958f5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e958f5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68f1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68f1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68f1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68f1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e958ef2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e958ef2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e958ed7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e958b870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e958b86dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f68f1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68f1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68f1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e958b86cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c (1920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627a811e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627a811b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627a811e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc246a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc246aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc246a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc246a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627a80b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005627a80b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005627a8098b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627a7d480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627a7d47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc246a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc246a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc246a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627a7d47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c (1921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrev8_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrev8.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrev8.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | d # | ... # `---data was truncated (10240/95223) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d46342b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d4634280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d46342b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6899f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6899f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6899f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6899eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4633c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d4633c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d4633a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d4630550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d463054dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6899eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6899eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6899eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d463054cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-cde-reinterpret.c (1922 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-reinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_s8(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | ret <16 x i8> %0 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_u16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_s32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_u32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x i32> # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_s64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_u64(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <2 x i64> # | ret <2 x i64> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_f16(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x half> # | ret <8 x half> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_f32(<16 x i8> noundef %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %x, ptr %x.addr, align 8 # | %0 = load <16 x i8>, ptr %x.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <4 x float> # | ret <4 x float> %1 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588d4a7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588d4a700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588d4a7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1199d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1199d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1199d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1199d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588d4a08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588d4a08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588d49edb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588d469d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588d469cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1199d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1199d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1199d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588d469ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-reinterpret.c --check-prefixes=CHECK,CHECK-LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c (1923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594926ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594926ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594926ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81d7933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81d798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81d7933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81d791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559492643e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559492643c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559492628b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594922d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594922d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81d791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81d791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81d791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594922d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c (1924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory( # | ... # `---data was truncated (10240/40661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574976dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574976da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574976dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb453e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb453ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb453e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb453e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557497672e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557497672c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557497657b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574973070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557497306dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb453e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb453e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb453e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557497306cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c (1925 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561cb76bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561cb76b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561cb76bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf88d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf88d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf88d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf88d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561cb7651e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561cb7651c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561cb7636b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561cb72e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561cb72e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf88d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf88d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf88d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561cb72e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c (1926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557ad1d0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557ad1d060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557ad1d0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e54049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e540a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e54049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e54031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ad1c9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557ad1c9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557ad1c83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557ad19330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557ad1932dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e54032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e540330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e540330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ad1932cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/fp8-extract.c (1927 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/fp8-extract.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -disable-O0-optnone -Werror -Wall -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_var(<16 x i8> %v, i32 noundef %i) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | %i.addr = alloca i32, align 4 # | store <16 x i8> %v, ptr %v.addr, align 16 # | store i32 %i, ptr %i.addr, align 4 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %1 = load i32, ptr %i.addr, align 4 # | %vecext = extractelement <16 x i8> %0, i32 %1 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | declare void @g(<1 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_cst(<16 x i8> %v) #0 { # | entry: # | %v.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %v, ptr %v.addr, align 16 # | %0 = load <16 x i8>, ptr %v.addr, align 16 # | %vecext = extractelement <16 x i8> %0, i32 3 # | %mfp8ext = insertelement <1 x i8> poison, i8 %vecext, i64 0 # | call void @g(<1 x i8> %mfp8ext) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -p mem2reg,instcombine # | #0 0x000055a093c8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a093c880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a093c8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5d8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5d898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5d8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5d891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a093c20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a093c20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a093c05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a0938b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a0938b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc5d891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5d891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5d891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0938b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/fp8-extract.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c (1928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c1fad015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c1facd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c1fad089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cef649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cef6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cef649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cef631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c1fa65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c1fa65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c1fa4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c1f6fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c1f6f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3cef632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cef6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cef6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c1f6f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c (1929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf8( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf8( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf4( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf4( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8mf2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8mf2( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m1( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vxm_i8m1( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsbc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsbc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsbc_vvm_i8m2( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f6a8d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f6a8cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f6a8d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b17831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f6a867e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f6a867c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f6a84cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f6a4fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f6a4fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f6a4fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c (1930 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , al # | ... # `---data was truncated (10240/13263) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e1906f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557e1906c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557e1906f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40ca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40ca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40ca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40ca91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e19004e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557e19004c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557e18fe9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557e18c990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557e18c98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f40ca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40ca91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40ca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e18c98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c (1931 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab5511f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ab5511c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ab5511f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5722533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f572258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5722533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f572251b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab550b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ab550b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ab55099b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ab54d490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ab54d48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f572251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f572251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f572251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab54d48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c (1932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056154084615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615408430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056154084689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4fdf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4fdf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4fdf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4fdf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615407dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615407dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615407c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615404700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056154046fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa4fdf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4fdf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4fdf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056154046fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c (1933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c (1934 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556456fd315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556456fd00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556456fd389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd2e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd2e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd2e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd2e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556456f68e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556456f68c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556456f4db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556456bfd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556456bfcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbd2e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd2e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd2e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556456bfccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c (1935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c (1936 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c (1937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32f16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_u16mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i16.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_v # | ... # `---data was truncated (10240/29273) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f1ee1815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562f1ee150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562f1ee1889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5061733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f506178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5061733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f506171b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f1edade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562f1edadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562f1ed92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562f1ea420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562f1ea41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f506171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f506171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f506171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f1ea41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c (1938 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055865203f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055865203c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055865203f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea17849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea17849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea17831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558651fd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558651fd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558651fb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558651c690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558651c68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea17832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558651c68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c (1939 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c4f89315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c4f8900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c4f89389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb3d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb3d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb3d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb3d831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c4f828e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c4f828c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c4f80db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c4f4bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c4f4bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb3d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb3d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb3d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c4f4bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-cde-gpr.c (1940 of 27911) ******************** TEST 'Clang :: CodeGen/arm-cde-gpr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +cdecp0 -target-feature +cdecp1 -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1() #0 { # | entry: # | %0 = call i32 @llvm.arm.cde.cx1(i32 0, i32 123) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx1a(i32 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx1a(i32 0, i32 %0, i32 345) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx1a(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1d() #0 { # | entry: # | %0 = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, i32 567) # | %1 = extractvalue { i32, i32 } %0, 1 # | %2 = zext i32 %1 to i64 # | %3 = shl i64 %2, 32 # | %4 = extractvalue { i32, i32 } %0, 0 # | %5 = zext i32 %4 to i64 # | %6 = or i64 %3, %5 # | ret i64 %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1d(i32 immarg, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx1da(i64 noundef %acc) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | store i64 %acc, ptr %acc.addr, align 8 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, i32 %3, i32 %2, i32 789) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx1da(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call i32 @llvm.arm.cde.cx2(i32 0, i32 %0, i32 11) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx2a(i32 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx2a(i32 1, i32 %0, i32 %1, i32 22) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx2a(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2d(i32 noundef %n) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = call { i32, i32 } @llvm.arm.cde.cx2d(i32 1, i32 %0, i32 33) # | %2 = extractvalue { i32, i32 } %1, 1 # | %3 = zext i32 %2 to i64 # | %4 = shl i64 %3, 32 # | %5 = extractvalue { i32, i32 } %1, 0 # | %6 = zext i32 %5 to i64 # | %7 = or i64 %4, %6 # | ret i64 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2d(i32 immarg, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx2da(i64 noundef %acc, i32 noundef %n) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.cde.cx2da(i32 0, i32 %3, i32 %2, i32 %4, i32 44) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx2da(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call i32 @llvm.arm.cde.cx3(i32 0, i32 %0, i32 %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_cx3a(i32 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i32, align 4 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %acc, ptr %acc.addr, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %acc.addr, align 4 # | %1 = load i32, ptr %n.addr, align 4 # | %2 = load i32, ptr %m.addr, align 4 # | %3 = call i32 @llvm.arm.cde.cx3a(i32 1, i32 %0, i32 %1, i32 %2, i32 2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.cde.cx3a(i32 immarg, i32, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3d(i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i32, ptr %n.addr, align 4 # | %1 = load i32, ptr %m.addr, align 4 # | %2 = call { i32, i32 } @llvm.arm.cde.cx3d(i32 1, i32 %0, i32 %1, i32 3) # | %3 = extractvalue { i32, i32 } %2, 1 # | %4 = zext i32 %3 to i64 # | %5 = shl i64 %4, 32 # | %6 = extractvalue { i32, i32 } %2, 0 # | %7 = zext i32 %6 to i64 # | %8 = or i64 %5, %7 # | ret i64 %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3d(i32 immarg, i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_cx3da(i64 noundef %acc, i32 noundef %n, i32 noundef %m) #0 { # | entry: # | %acc.addr = alloca i64, align 8 # | %n.addr = alloca i32, align 4 # | %m.addr = alloca i32, align 4 # | store i64 %acc, ptr %acc.addr, align 8 # | store i32 %n, ptr %n.addr, align 4 # | store i32 %m, ptr %m.addr, align 4 # | %0 = load i64, ptr %acc.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %n.addr, align 4 # | %5 = load i32, ptr %m.addr, align 4 # | %6 = call { i32, i32 } @llvm.arm.cde.cx3da(i32 0, i32 %3, i32 %2, i32 %4, i32 %5, i32 4) # | %7 = extractvalue { i32, i32 } %6, 1 # | %8 = zext i32 %7 to i64 # | %9 = shl i64 %8, 32 # | %10 = extractvalue { i32, i32 } %6, 0 # | %11 = zext i32 %10 to i64 # | %12 = or i64 %9, %11 # | ret i64 %12 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.cde.cx3da(i32 immarg, i32, i32, i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+cdecp0,+cdecp1,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560518ee315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560518ee00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560518ee389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4d5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4d578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4d5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4d571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560518e78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560518e78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560518e5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560518b0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560518b0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe4d571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4d571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4d571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560518b0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-cde-gpr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c (1941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e4694115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e4693e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e4694189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f964a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f964a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f964a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f964a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e468d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e468d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e468bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e4656b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e4656add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f964a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f964a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f964a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e4656acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c (1942 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b9c45015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b9c44d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b9c45089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe93e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe93ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe93e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe93e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b9c3e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b9c3e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b9c3cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b9c07a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b9c079dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbe93e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe93e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe93e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b9c079cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c (1943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.r # | ... # `---data was truncated (10240/53678) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d53b6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d53b5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d53b6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecfe849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecfe8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecfe849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecfe831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d53af5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d53af5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d53adab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d5378a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d53789dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fecfe832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecfe8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecfe8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d53789cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/neon/f16-getset.c (1944 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/f16-getset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %4, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %5 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %5, ptr %__ret, align 8 # | %6 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %6, ptr %tmp, align 8 # | %7 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %1, i32 0 # | %2 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %2, i32 1 # | %3 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %3, i32 2 # | %4 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %4, i32 3 # | %5 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %5, i32 4 # | %6 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %6, i32 5 # | %7 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %7, i32 6 # | %8 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %8, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %9 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %9, ptr %__ret, align 16 # | %10 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %10, ptr %tmp, align 16 # | %11 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_39 = alloca <4 x half>, align 8 # | %__s0_39 = alloca <4 x half>, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_39, align 8 # | %1 = load <4 x half>, ptr %__s0_39, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_39, align 8 # | %7 = load <4 x half>, ptr %__ret_39, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x half>, align 8 # | %__ret_20 = alloca <8 x half>, align 16 # | %__s0_20 = alloca <4 x half>, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <4 x half> %a, ptr %a.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %0, ptr %__s0_20, align 8 # | %1 = load <4 x half>, ptr %__s0_20, align 8 # | store <4 x half> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <4 x half> # | %lane = shufflevector <4 x half> %3, <4 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_20, align 16 # | %7 = load <8 x half>, ptr %__ret_20, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x half> @test_vdup_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_432 = alloca <4 x half>, align 8 # | %__s0_432 = alloca <8 x half>, align 16 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x half>, align 8 # | %tmp1 = alloca <4 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_432, align 16 # | %1 = load <8 x half>, ptr %__s0_432, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <4 x i32> # | store <4 x half> %lane, ptr %ref.tmp, align 8 # | %4 = load <4 x half>, ptr %ref.tmp, align 8 # | store <4 x half> %4, ptr %__ret, align 8 # | %5 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %5, ptr %tmp, align 8 # | %6 = load <4 x half>, ptr %tmp, align 8 # | store <4 x half> %6, ptr %__ret_432, align 8 # | %7 = load <4 x half>, ptr %__ret_432, align 8 # | store <4 x half> %7, ptr %tmp1, align 8 # | %8 = load <4 x half>, ptr %tmp1, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x half> @test_vdupq_laneq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 16 # | %__ret_408 = alloca <8 x half>, align 16 # | %__s0_408 = alloca <8 x half>, align 16 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <8 x half>, align 16 # | %tmp1 = alloca <8 x half>, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %0, ptr %__s0_408, align 16 # | %1 = load <8 x half>, ptr %__s0_408, align 16 # | store <8 x half> %1, ptr %__s0, align 16 # | %2 = load <16 x i8>, ptr %__s0, align 16 # | %3 = bitcast <16 x i8> %2 to <8 x half> # | %lane = shufflevector <8 x half> %3, <8 x half> %3, <8 x i32> # | store <8 x half> %lane, ptr %ref.tmp, align 16 # | %4 = load <8 x half>, ptr %ref.tmp, align 16 # | store <8 x half> %4, ptr %__ret, align 16 # | %5 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %5, ptr %tmp, align 16 # | %6 = load <8 x half>, ptr %tmp, align 16 # | store <8 x half> %6, ptr %__ret_408, align 16 # | %7 = load <8 x half>, ptr %__ret_408, align 16 # | store <8 x half> %7, ptr %tmp1, align 16 # | %8 = load <8 x half>, ptr %tmp1, align 16 # | ret <8 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_lane_f16(<4 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <4 x half>, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca <4 x half>, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <4 x half> %vec, ptr %vec.addr, align 8 # | %0 = load <4 x half>, ptr %vec.addr, align 8 # | store <4 x half> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %__s0, align 8 # | %vget_lane = extractelement <4 x half> %1, i32 3 # | store half %vget_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vduph_laneq_f16(<8 x half> noundef %vec) #0 { # | entry: # | %vec.addr = alloca <8 x half>, align 16 # | %__ret = alloca half, align 2 # | %__s0 = alloca <8 x half>, align 16 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store <8 x half> %vec, ptr %vec.addr, align 16 # | %0 = load <8 x half>, ptr %vec.addr, align 16 # | store <8 x half> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %__s0, align 16 # | %vgetq_lane = extractelement <8 x half> %1, i32 7 # | store half %vgetq_lane, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-s # | ... # `---data was truncated (10240/10414) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055fa45ff815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa45ff50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa45ff889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efee5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efee518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efee5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efee511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa45f8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa45f8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa45f72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa45c220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa45c21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efee511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efee511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efee511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa45c21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/f16-getset.c --check-prefixes=ALL,LLVM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c (1945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c (1946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0161ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0161eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0161ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82b7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82b7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82b7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82b7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c016183e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c016183c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c016168b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c015e180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c015e17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f82b7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82b7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82b7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c015e17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c (1947 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056432aa6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056432aa690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056432aa6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8920b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8920b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8920b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8920b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056432aa01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056432aa01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056432a9e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056432a6960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056432a695dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8920b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8920b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8920b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056432a695cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c (1948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2_tu( %maskedoff, %op1, %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %index.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2_tu( %maskedoff, %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %index.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c (1949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_wx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwaddu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp (1950 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_zt0() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_zt0() #1 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_zt0() #2 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_zt0() #3 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_zt0() #4 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @in_za_zt0() #5 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @out_za_zt0() #6 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @inout_za_zt0() #7 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @preserves_za_zt0() #8 { # | entry: # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @new_za_zt0() #9 { # | entry: # | ret void # | } # | # | attributes #0 = { mustprogress noinline nounwind "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #1 = { mustprogress noinline nounwind "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #2 = { mustprogress noinline nounwind "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #3 = { mustprogress noinline nounwind "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #4 = { mustprogress noinline nounwind "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #5 = { mustprogress noinline nounwind "aarch64_in_za" "aarch64_in_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #6 = { mustprogress noinline nounwind "aarch64_out_za" "aarch64_out_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #7 = { mustprogress noinline nounwind "aarch64_inout_za" "aarch64_inout_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #8 = { mustprogress noinline nounwind "aarch64_preserves_za" "aarch64_preserves_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | attributes #9 = { mustprogress noinline nounwind "aarch64_new_za" "aarch64_new_zt0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sme,+sme2" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636c64da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005636c64d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005636c64da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe34333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe3438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe34333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe3431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636c646fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005636c646fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005636c6454b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636c61040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005636c6103dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe3431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe3431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe3431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636c6103cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x000056018cb5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056018cb550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056018cb5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17d6c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17d6ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17d6c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17d6c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056018caede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056018caedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056018cad2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056018c7820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056018c781dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f17d6c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17d6c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17d6c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056018c781cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c (1951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv1f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv1f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16mf2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16mf2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv2f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv2f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m1( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m1( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv4f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv4f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m2( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m2( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv8f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vx.nxv8f16.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vv_f16m4( %op1, %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %index, ptr %index.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %index.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vv.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgather.vv.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrgather_vx_f16m4( %op1, i64 noundef %index, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %index.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgather.vx.nxv16f16.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwin # | ... # `---data was truncated (10240/273705) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b9441115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b9440e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b9441189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a91533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a9158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a91533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a9151b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b943a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b943a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b9438bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b9403b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b9403add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5a9151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a9151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a9151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b9403acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c (1952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c (1953 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056325274815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632527450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056325274889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81bcf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81bcf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81bcf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81bcf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005632526dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005632526ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005632526c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632523720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563252371dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81bcf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81bcf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81bcf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563252371cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c (1954 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055672d5d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055672d5d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055672d5d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbb8b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbb8b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbb8b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbb8aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055672d56be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055672d56bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055672d550b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055672d2000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055672d1ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffbb8aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbb8aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbb8aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055672d1ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c (1955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv32i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align # | ... # `---data was truncated (10240/14145) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abd10d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055abd10d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055abd10d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc5c4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc5c458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc5c4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc5c451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abd106ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055abd106ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055abd1053b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055abd0d030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055abd0d02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc5c451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc5c451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc5c451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abd0d02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c (1956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8cfacf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8cfacc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8cfacf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6bfe333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6bfe38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6bfe333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6bfe31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8cfa64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8cfa64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8cfa49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8cf6f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8cf6f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6bfe31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6bfe31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6bfe31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8cf6f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c (1957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vremu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vremu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vremu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op # | ... # `---data was truncated (10240/222917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c443a6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c443a690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c443a6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1704933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f170498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1704933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f170491b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c443a01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c443a01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c4439e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4436960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c443695dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f170491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f170491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f170491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c443695cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c (1958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/18641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b08c1e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b08c1e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b08c1e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6a0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6a0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6a0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6a0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b08c17ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b08c17ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b08c163b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b08be130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b08be12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff6a0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6a0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6a0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b08be12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm64_vdupq_n_f64.c (1959 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vdupq_n_f64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x float> @test_vdupq_n_f32(float noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca float, align 4 # | %__ret.i = alloca <4 x float>, align 16 # | %.compoundliteral.i = alloca <4 x float>, align 16 # | %w.addr = alloca float, align 4 # | store float %w, ptr %w.addr, align 4 # | %0 = load float, ptr %w.addr, align 4 # | store float %0, ptr %__p0.addr.i, align 4 # | %1 = load float, ptr %__p0.addr.i, align 4 # | %vecinit.i = insertelement <4 x float> poison, float %1, i32 0 # | %2 = load float, ptr %__p0.addr.i, align 4 # | %vecinit1.i = insertelement <4 x float> %vecinit.i, float %2, i32 1 # | %3 = load float, ptr %__p0.addr.i, align 4 # | %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %3, i32 2 # | %4 = load float, ptr %__p0.addr.i, align 4 # | %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %4, i32 3 # | store <4 x float> %vecinit3.i, ptr %.compoundliteral.i, align 16 # | %5 = load <4 x float>, ptr %.compoundliteral.i, align 16 # | store <4 x float> %5, ptr %__ret.i, align 16 # | %6 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 { # | entry: # | %V.addr = alloca <1 x double>, align 8 # | %__ret_379 = alloca <2 x double>, align 16 # | %__s0_379 = alloca <1 x double>, align 8 # | %__ret = alloca <2 x double>, align 16 # | %__s0 = alloca <1 x double>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <2 x double>, align 16 # | %tmp1 = alloca <2 x double>, align 16 # | store <1 x double> %V, ptr %V.addr, align 8 # | %0 = load <1 x double>, ptr %V.addr, align 8 # | store <1 x double> %0, ptr %__s0_379, align 8 # | %1 = load <1 x double>, ptr %__s0_379, align 8 # | store <1 x double> %1, ptr %__s0, align 8 # | %2 = load <8 x i8>, ptr %__s0, align 8 # | %3 = bitcast <8 x i8> %2 to <1 x double> # | %lane = shufflevector <1 x double> %3, <1 x double> %3, <2 x i32> zeroinitializer # | store <2 x double> %lane, ptr %ref.tmp, align 16 # | %4 = load <2 x double>, ptr %ref.tmp, align 16 # | store <2 x double> %4, ptr %__ret, align 16 # | %5 = load <2 x double>, ptr %__ret, align 16 # | store <2 x double> %5, ptr %tmp, align 16 # | %6 = load <2 x double>, ptr %tmp, align 16 # | store <2 x double> %6, ptr %__ret_379, align 16 # | %7 = load <2 x double>, ptr %__ret_379, align 16 # | store <2 x double> %7, ptr %tmp1, align 16 # | %8 = load <2 x double>, ptr %tmp1, align 16 # | ret <2 x double> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <2 x double> @test_vmovq_n_f64(double noundef %w) #0 { # | entry: # | %__p0.addr.i = alloca double, align 8 # | %__ret.i = alloca <2 x double>, align 16 # | %.compoundliteral.i = alloca <2 x double>, align 16 # | %w.addr = alloca double, align 8 # | store double %w, ptr %w.addr, align 8 # | %0 = load double, ptr %w.addr, align 8 # | store double %0, ptr %__p0.addr.i, align 8 # | %1 = load double, ptr %__p0.addr.i, align 8 # | %vecinit.i = insertelement <2 x double> poison, double %1, i32 0 # | %2 = load double, ptr %__p0.addr.i, align 8 # | %vecinit1.i = insertelement <2 x double> %vecinit.i, double %2, i32 1 # | store <2 x double> %vecinit1.i, ptr %.compoundliteral.i, align 16 # | %3 = load <2 x double>, ptr %.compoundliteral.i, align 16 # | store <2 x double> %3, ptr %__ret.i, align 16 # | %4 = load <2 x double>, ptr %__ret.i, align 16 # | ret <2 x double> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <4 x half>, align 8 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <4 x half>, align 8 # | %tmp = alloca <4 x half>, align 8 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <4 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <4 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <4 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <4 x half> %vecinit2, half %5, i32 3 # | store <4 x half> %vecinit3, ptr %.compoundliteral, align 8 # | %6 = load <4 x half>, ptr %.compoundliteral, align 8 # | store <4 x half> %6, ptr %__ret, align 8 # | %7 = load <4 x half>, ptr %__ret, align 8 # | store <4 x half> %7, ptr %tmp, align 8 # | %8 = load <4 x half>, ptr %tmp, align 8 # | ret <4 x half> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 { # | entry: # | %a1.addr = alloca ptr, align 8 # | %__ret = alloca <8 x half>, align 16 # | %__s0 = alloca half, align 2 # | %.compoundliteral = alloca <8 x half>, align 16 # | %tmp = alloca <8 x half>, align 16 # | store ptr %a1, ptr %a1.addr, align 8 # | %0 = load ptr, ptr %a1.addr, align 8 # | %1 = load half, ptr %0, align 2 # | store half %1, ptr %__s0, align 2 # | %2 = load half, ptr %__s0, align 2 # | %vecinit = insertelement <8 x half> poison, half %2, i32 0 # | %3 = load half, ptr %__s0, align 2 # | %vecinit1 = insertelement <8 x half> %vecinit, half %3, i32 1 # | %4 = load half, ptr %__s0, align 2 # | %vecinit2 = insertelement <8 x half> %vecinit1, half %4, i32 2 # | %5 = load half, ptr %__s0, align 2 # | %vecinit3 = insertelement <8 x half> %vecinit2, half %5, i32 3 # | %6 = load half, ptr %__s0, align 2 # | %vecinit4 = insertelement <8 x half> %vecinit3, half %6, i32 4 # | %7 = load half, ptr %__s0, align 2 # | %vecinit5 = insertelement <8 x half> %vecinit4, half %7, i32 5 # | %8 = load half, ptr %__s0, align 2 # | %vecinit6 = insertelement <8 x half> %vecinit5, half %8, i32 6 # | %9 = load half, ptr %__s0, align 2 # | %vecinit7 = insertelement <8 x half> %vecinit6, half %9, i32 7 # | store <8 x half> %vecinit7, ptr %.compoundliteral, align 16 # | %10 = load <8 x half>, ptr %.compoundliteral, align 16 # | store <8 x half> %10, ptr %__ret, align 16 # | %11 = load <8 x half>, ptr %__ret, align 16 # | store <8 x half> %11, ptr %tmp, align 16 # | %12 = load <8 x half>, ptr %tmp, align 16 # | ret <8 x half> %12 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055895b1b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055895b1af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055895b1b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3868d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3868d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3868d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3868d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055895b147e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055895b147c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055895b12cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055895addc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055895addbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3868d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3868d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3868d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055895addbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vdupq_n_f64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c (1960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i6 # | ... # `---data was truncated (10240/90867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055688e96915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055688e9660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055688e96989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec5ab33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec5ab8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec5ab33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec5ab1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055688e8fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055688e8fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055688e8e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055688e5930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055688e592dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec5ab1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec5ab1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec5ab1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055688e592cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c (1961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c88ce115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555c88cde0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555c88ce189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f31eae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31eae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f31eae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f31eae03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c88c76e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555c88c76c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555c88c5bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555c8890b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555c8890add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f31eae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31eae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31eae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c8890acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c (1962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/47604) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558108ec615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558108ec30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558108ec689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6501f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6501f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6501f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6501f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558108e5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558108e5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558108e40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558108af00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558108aefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6501f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6501f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6501f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558108aefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c (1963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d122dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d122da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d122dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4642a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4642aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4642a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4642a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d12272e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d12272c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d12257b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d11f070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d11f06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4642a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4642a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4642a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d11f06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c (1964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32f16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/71955) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f81922e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f81922b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f81922e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd263d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd263d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd263d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd263ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8191c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f8191c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f8191a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f818e580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f818e57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd263ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd263cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd263cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f818e57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c (1965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c (1966 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/205805) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587f069d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587f069a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587f069d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc009249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0092a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc009249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc009231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587f0632e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587f0632c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587f0617b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587f02c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587f02c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc009232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0092330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0092330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587f02c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c (1967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1fa0a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1fa0a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1fa0a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faadb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faadb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faadb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faadb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1fa038e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1fa038c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1fa01db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1f9ccd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1f9cccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faadb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faadb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faadb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1f9ccccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c (1968 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056061df7615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056061df730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056061df7689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd317b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd317b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd317b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd317b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056061df0be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056061df0bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056061def0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056061dba00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056061db9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd317b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd317b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd317b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056061db9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c (1969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8_tu( %maskedoff, %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i8, ptr %value.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i16, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( %0, %1, i16 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2_tu( %maskedoff, %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, # | ... # `---data was truncated (10240/211231) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f397a615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556f397a30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556f397a689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b48449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b484a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b48449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b48431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f3973be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556f3973bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556f39720b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556f393d00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556f393cfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b48432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b484330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b484330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f393cfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c (1970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmslt.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c (1971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055873f8bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055873f8b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055873f8bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc19f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc19f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc19f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc19f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055873f850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055873f850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055873f835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055873f4e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055873f4e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efc19f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc19f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc19f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055873f4e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c (1972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, # | ... # `---data was truncated (10240/30635) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a3fc5415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a3fc510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a3fc5489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f085ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f085eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f085ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f085ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a3fbe9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a3fbe9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a3fbceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a3f87e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a3f87ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f085ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f085ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f085ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a3f87dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c (1973 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e12cc8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e12cc8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e12cc8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb202933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb20298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb202933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb20291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e12cc23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e12cc23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e12cc08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e12c8b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e12c8b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb20291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb20291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb20291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e12c8b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c (1974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3f500015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3f4ffd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3f500089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd85dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd85dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd85dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd85dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3f4f95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3f4f95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3f4f7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3f4c2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3f4c29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd85dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd85dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd85dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3f4c29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c (1975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredand.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredand_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredand.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005632733de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005632733db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005632733de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23f1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23f1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23f1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23f1c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563273373e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563273373c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563273358b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005632730080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563273007dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23f1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23f1c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23f1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563273007cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c (1976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdiv.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdiv.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdiv_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/222483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056043cb8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056043cb820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056043cb8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7aa1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7aa12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7aa1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7aa1231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056043cb1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056043cb1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056043caffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056043c7af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056043c7aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7aa1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7aa12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7aa12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056043c7aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c (1977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e94095d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e94095a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e94095d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcda733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcda78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcda733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcda71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9408f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9408f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9408d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9405870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e940586dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbcda71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcda71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcda71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e940586cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c (1978 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055801f96d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055801f96a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055801f96d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1fec333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1fec38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1fec333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1fec31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055801f902e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055801f902c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055801f8e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055801f5970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055801f596dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1fec31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1fec31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1fec31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055801f596cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c (1979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8aa78c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8aa7890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8aa78c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb20e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb20e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb20e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb20e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8aa721e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8aa721c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8aa706b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8aa3b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8aa3b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb20e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb20e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb20e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8aa3b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c (1980 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b39622d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b39622a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b39622d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd673049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6730a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd673049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd673031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3961c2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3961c2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3961a7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b395e570b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b395e56dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd673032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6730330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6730330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b395e56cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c (1981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005600b84bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005600b84b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005600b84bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8baa333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8baa38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8baa333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8baa31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005600b8451e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005600b8451c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005600b8436b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600b80e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600b80e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8baa31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8baa31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8baa31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600b80e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c (1982 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c1c8e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c1c8e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c1c8e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7cac733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7cac78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7cac733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7cac71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c1c87ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c1c87cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c1c861b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c1c5110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c1c510dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7cac71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7cac71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7cac71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c1c510cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c (1983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6746f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6746ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6746f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe6aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe6aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe6aac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b674685e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b674685c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b67466ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b67431a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b674319dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe6aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6aac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b674319cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c (1984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | ... # `---data was truncated (10240/24982) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4b8f3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c4b8f330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c4b8f3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc302449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3024a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc302449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc302431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4b8ecbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c4b8ecbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c4b8eb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4b8b600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4b8b5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc302432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3024330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3024330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4b8b5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c (1985 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2(bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load bfloat, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( poison, bfloat %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store % # | ... # `---data was truncated (10240/13308) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560628f2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560628f1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560628f2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2040e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2040ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2040e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2040e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560628eb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560628eb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560628e9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560628b4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560628b4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2040e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2040e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2040e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560628b4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c (1986 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565309a6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565309a6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565309a6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6632449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66324a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6632449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6632431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565309a04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565309a04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005653099e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653096990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565309698dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6632432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66324330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66324330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565309698cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c (1987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c (1988 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c (1989 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovunbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovunbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovuntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqmovn.v16i8.v8i16(<16 x i8> %0, <8 x i16> %1, i32 1, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovuntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqmovn.v8i16.v4i32(<8 x i16> %0, <4 x i32> %1, i32 1, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, i32 0, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, i32 0, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vqmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 1, i32 1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | # | ... # `---data was truncated (10240/17536) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db06ed915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db06ed60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db06ed989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f586c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f586c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f586c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f586c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db06e6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db06e6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db06e53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db06b030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db06b02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f586c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f586c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f586c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db06b02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c (1990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e41cff115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e41cfee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e41cff189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dc4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dc438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dc4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dc431b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e41cf86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e41cf86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e41cf6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e41cc1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e41cc1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1dc431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dc431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dc431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e41cc1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c (1991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.add # | ... # `---data was truncated (10240/15312) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c4e19415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c4e1910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c4e19489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04c6a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04c6aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04c6a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04c6a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c4e129e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c4e129c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c4e10eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c4ddbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c4ddbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f04c6a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04c6a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04c6a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c4ddbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c (1992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055785ccc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055785ccc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055785ccc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32a3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32a3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32a3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32a3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055785cc5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055785cc5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055785cc43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055785c8f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055785c8f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f32a3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32a3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32a3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055785c8f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c (1993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c (1994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564054be715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564054be40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564054be789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3752333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f375238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3752333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f375231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564054b7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564054b7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564054b61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640548110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564054810dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f375231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f375231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f375231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564054810cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c (1995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055759ee3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055759ee330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055759ee3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f21a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f21a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f21a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f21a9231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055759edcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055759edcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055759edb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055759ea600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055759ea5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f21a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f21a92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f21a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055759ea5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c (1996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c (1997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8mf2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vx_u8m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vror.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vror.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vror_vv_u8m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store %v # | ... # `---data was truncated (10240/222307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653a13f315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653a13f00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653a13f389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f675e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f675e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f675e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f675e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653a1388e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005653a1388c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005653a136db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653a101d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005653a101cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f675e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f675e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f675e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653a101ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c (1998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056545b1f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056545b1ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056545b1f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad6131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056545b186e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056545b186c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056545b16bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056545ae1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056545ae1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad6131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056545ae1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c (1999 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e3cf2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e3cf1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e3cf2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa558333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa55838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa558333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa55831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e3ceb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e3ceb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e3ce9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e3cb4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e3cb4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa55831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa55831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa55831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e3cb4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c (2000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602baafc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602baaf90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602baafc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ff4933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ff498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ff4933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ff491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602baa91e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602baa91c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602baa76b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602ba7260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005602ba725dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ff491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ff491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ff491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602ba725cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c (2001 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv2i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_and_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.and = call i32 @llvm.vector.reduce.and.nxv2i32( %0) # | ret i32 %rdx.and # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.and.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_or_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.or = call i32 @llvm.vector.reduce.or.nxv2i32( %0) # | ret i32 %rdx.or # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.or.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_xor_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.xor = call i32 @llvm.vector.reduce.xor.nxv2i32( %0) # | ret i32 %rdx.xor # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.xor.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smax_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_smin_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.smin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.smin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umax_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umax.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umax.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_umin_u32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call i32 @llvm.vector.reduce.umin.nxv2i32( %0) # | ret i32 %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.umin.nxv2i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmax_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmax.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmax.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmin_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.min = call float @llvm.vector.reduce.fmin.nxv2f32( %0) # | ret float %rdx.min # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmin.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fmaximum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.maximum = call float @llvm.vector.reduce.fmaximum.nxv2f32( %0) # | ret float %rdx.maximum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fmaximum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local float @reduce_fminimum_f32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.minimum = call float @llvm.vector.reduce.fminimum.nxv2f32( %0) # | ret float %rdx.minimum # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare float @llvm.vector.reduce.fminimum.nxv2f32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_add_i32_m8( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.add = call i32 @llvm.vector.reduce.add.nxv16i32( %0) # | ret i32 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.add.nxv16i32() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @reduce_add_i64( %a) #0 { # | entry: # | %a.addr = alloca , align 8 # | store %a, ptr %a.addr, align 8 # | %0 = load , ptr %a.addr, align 8 # | %rdx.add = call i64 @llvm.vector.reduce.add.nxv1i64( %0) # | ret i64 %rdx.add # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.vector.reduce.add.nxv1i64() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @reduce_mul_i32( %a) #0 { # | entry: # | %a.addr = alloca , align 4 # | store %a, ptr %a.addr, align 4 # | %0 = load , ptr %a.addr, align 4 # | %rdx.mul = call i32 @llvm.vector.reduce.mul.nxv2i32( %0) # | ret i32 %rdx.mul # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.vector.reduce.mul.nxv2i32() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055cf74b1615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf74b130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf74b1689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8a6733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8a678a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8a6733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8a671b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf74aabe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf74aabc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf74a90b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf747400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf7473fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd8a671cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8a671d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8a671d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf7473fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-builtin-reduce-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c (2002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdf74d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fdf74cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fdf74d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a78a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a78aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a78a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a78a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdf7467e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fdf7467c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fdf744cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fdf70fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fdf70fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9a78a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a78a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a78a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdf70fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c (2003 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv1i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594d629715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594d62940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594d629789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d07333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d0738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d07333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d0731b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594d622ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594d622cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594d6211b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594d5ec10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594d5ec0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d0731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d0731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d0731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594d5ec0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c (2004 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve32x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vx_i8m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local @test_vmulhsu_vv_i8m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr % # | ... # `---data was truncated (10240/66087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556aa671015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556aa670d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556aa671089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe099b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe099b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe099b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe099b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556aa66a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556aa66a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556aa668ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556aa633a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556aa6339dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe099b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe099b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe099b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556aa6339cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c (2005 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, pt # | ... # `---data was truncated (10240/79679) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603f9f1b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603f9f180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603f9f1b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aa0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aa058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aa0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aa051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603f9eb0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005603f9eb0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603f9e95b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005603f9b450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005603f9b44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9aa051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aa051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aa051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603f9b44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c (2006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbb27da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bbb27d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bbb27da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f17ba133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f17ba18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f17ba133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f17ba11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbb276fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bbb276fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bbb2754b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bbb24040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bbb2403dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f17ba11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f17ba11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f17ba11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbb2403cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c (2007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = allo # | ... # `---data was truncated (10240/98179) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596614b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596614ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596614b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56bf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559661445e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559661445c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055966142ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596610da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596610d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596610d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c (2008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf8x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_u8m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/21558) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2e99d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2e99d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c2e99d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72bfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2e9968e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2e9968c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c2e994db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2e95fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c2e95fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2e95fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c (2009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c (2010 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/80500) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6cc14215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6cc13f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6cc14289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5396533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f539658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5396533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f539651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6cc0d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6cc0d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6cc0bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6cbd6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6cbd6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f539651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f539651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f539651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6cbd6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c (2011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dba6af715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dba6af40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dba6af789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2526e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2526ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2526e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2526e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dba6a8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dba6a8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dba6a71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dba67210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dba6720dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2526e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2526e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2526e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dba6720cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c (2012 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i8m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmv.v.v.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmv_v_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmv.v.v.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function A # | ... # `---data was truncated (10240/68067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055882402815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588240250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055882402889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f83049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f830a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f83049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f83031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558823fbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558823fbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558823fa2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558823c520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558823c51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f83032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f830330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f830330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558823c51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c (2013 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, # | ... # `---data was truncated (10240/223801) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639df41d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639df41a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639df41d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9dbc133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9dbc18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9dbc133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9dbc11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639df3b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639df3b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639df397b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639df0470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639df046dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9dbc11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9dbc11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9dbc11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639df046cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c (2014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssubu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssubu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssubu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f0095a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f009570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f0095a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f154bb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f154bb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f154bb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f154baed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f008efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f008efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f008d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f005840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f00583dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f154baeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f154baef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f154baef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f00583cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c (2015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b64ce015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b64cdd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b64ce089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7194449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71944a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7194449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7194431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b64c75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b64c75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b64c5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b6490a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b64909dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7194432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71944330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71944330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b64909cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c (2016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei64_v_f64m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f64.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret voi # | ... # `---data was truncated (10240/102304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055642fdc115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055642fdbe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055642fdc189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8988f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8988f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8988f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8988f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055642fd56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055642fd56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055642fd3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055642f9eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055642f9eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8988f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8988f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8988f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055642f9eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c (2017 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsaddu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsaddu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsaddu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ee269015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ee268d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ee269089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f981a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f981a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f981a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f981a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ee2625e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ee2625c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ee260ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ee22ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ee22b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f981a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f981a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f981a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ee22b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c (2018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8ee66015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8ee65d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8ee66089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89b1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89b14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89b1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89b1431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8ee5f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8ee5f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8ee5dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8ee28a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8ee289dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f89b1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89b14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89b14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8ee289cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c (2019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, a # | ... # `---data was truncated (10240/28358) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055640979315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564097900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055640979389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80ebf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80ebf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80ebf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80ebf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556409728e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556409728c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055640970db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005564093bd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005564093bcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80ebf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80ebf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80ebf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564093bccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c (2020 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e8ffa315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e8ffa00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e8ffa389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb376d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb376d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb376d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb376d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e8ff38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e8ff38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e8ff1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e8fbcd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e8fbccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb376d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb376d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb376d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e8fbcccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c (2021 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = ashr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shl = shl <32 x i8> %0, %1 # | store <32 x i8> %shl, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %shr = lshr <32 x i8> %0, %1 # | store <32 x i8> %shr, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = ashr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shl = shl <16 x i16> %0, %1 # | store <16 x i16> %shl, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %shr = lshr <16 x i16> %0, %1 # | store <16 x i16> %shr, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @lshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %shl = shl <8 x i32> %0, %1 # | store <8 x i32> %shl, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @rshift_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %r # | ... # `---data was truncated (10240/50943) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005652e87c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005652e87c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005652e87c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8422f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8422f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8422f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8422eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652e875ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005652e875ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005652e8743b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005652e83f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005652e83f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8422eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8422eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8422eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652e83f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-shift-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvp-intrinsics.c (2022 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvp-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +experimental-p -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_cls_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %isneg.i = icmp slt i32 %1, 0 # | %not.i = xor i32 %1, -1 # | %2 = select i1 %isneg.i, i32 %not.i, i32 %1 # | %3 = call i32 @llvm.ctlz.i32(i32 %2, i1 false) # | %4 = sub nuw i32 %3, 1 # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_rev_32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %2 = call i32 @llvm.bitreverse.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_slx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rd.addr.i, align 4 # | %4 = load i32, ptr %__rs1.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshl.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_srx_32(i32 noundef %rd, i32 noundef %rs1, i32 noundef %shamt) #0 { # | entry: # | %__rd.addr.i = alloca i32, align 4 # | %__rs1.addr.i = alloca i32, align 4 # | %__shamt.addr.i = alloca i32, align 4 # | %rd.addr = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %shamt.addr = alloca i32, align 4 # | store i32 %rd, ptr %rd.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %shamt, ptr %shamt.addr, align 4 # | %0 = load i32, ptr %rd.addr, align 4 # | %1 = load i32, ptr %rs1.addr, align 4 # | %2 = load i32, ptr %shamt.addr, align 4 # | store i32 %0, ptr %__rd.addr.i, align 4 # | store i32 %1, ptr %__rs1.addr.i, align 4 # | store i32 %2, ptr %__shamt.addr.i, align 4 # | %3 = load i32, ptr %__rs1.addr.i, align 4 # | %4 = load i32, ptr %__rd.addr.i, align 4 # | %5 = load i32, ptr %__shamt.addr.i, align 4 # | %6 = call i32 @llvm.fshr.i32(i32 %3, i32 %4, i32 %5) # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aadd.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_aaddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.aaddu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asub.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_asubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.riscv.asubu.u32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sadd_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.sadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_saddu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.uadd.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssub_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.ssub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ssubu_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %elt.sat.i = call i32 @llvm.usub.sat.i32(i32 %2, i32 %3) # | ret i32 %elt.sat.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs_u32(i32 noundef %a) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | %1 = load i32, ptr %__rs1.addr.i, align 4 # | %elt.abs.i = call i32 @llvm.abs.i32(i32 %1, i1 false) # | ret i32 %elt.abs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_sati_i32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.sati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_usati_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.usati.i32(i32 %0, i32 16) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.usati.i32(i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_mulh_i32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__rs1.addr.i = alloca i32, align 4 # | %__rs2.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__rs1.addr.i, align 4 # | store i32 %1, ptr %__rs2.addr.i, align 4 # | %2 = load i32, ptr %__rs1.addr.i, align 4 # | %3 = load i32, ptr %__rs2.addr.i, align 4 # | %4 = call i32 @llvm.smulh.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function At # | ... # `---data was truncated (10240/1228637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa,instcombine # | #0 0x000055e29a4cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e29a4c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e29a4cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38aa41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38aa4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38aa41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38aa403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e29a461e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e29a461c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e29a446b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e29a0f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e29a0f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f38aa404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38aa4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38aa4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e29a0f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvp-intrinsics.c --check-prefixes=CHECK,RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vshlc.c (2023 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vshlc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_s8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 18) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_s16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 16) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_s32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 4) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_u8(<16 x i8> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.v16i8(<16 x i8> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <16 x i8> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <16 x i8> } %3, 1 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_u16(<8 x i16> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.v8i16(<8 x i16> %2, i32 %1, i32 17) # | %4 = extractvalue { i32, <8 x i16> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <8 x i16> } %3, 1 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_u32(<4 x i32> noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.v4i32(<4 x i32> %2, i32 %1, i32 20) # | %4 = extractvalue { i32, <4 x i32> } %3, 0 # | store i32 %4, ptr %0, align 4 # | %5 = extractvalue { i32, <4 x i32> } %3, 1 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_s8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 29, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_s16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 17, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_s32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <4 x i32>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32> %2, i32 %1, i32 9, <4 x i1> %5) # | %7 = extractvalue { i32, <4 x i32> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <4 x i32> } %6, 1 # | ret <4 x i32> %8 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, <4 x i32> } @llvm.arm.mve.vshlc.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vshlcq_m_u8(<16 x i8> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <16 x i8>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %4) # | %6 = call { i32, <16 x i8> } @llvm.arm.mve.vshlc.predicated.v16i8.v16i1(<16 x i8> %2, i32 %1, i32 21, <16 x i1> %5) # | %7 = extractvalue { i32, <16 x i8> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <16 x i8> } %6, 1 # | ret <16 x i8> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vshlcq_m_u16(<8 x i16> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %b.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = load <8 x i16>, ptr %a.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call { i32, <8 x i16> } @llvm.arm.mve.vshlc.predicated.v8i16.v8i1(<8 x i16> %2, i32 %1, i32 24, <8 x i1> %5) # | %7 = extractvalue { i32, <8 x i16> } %6, 0 # | store i32 %7, ptr %0, align 4 # | %8 = extractvalue { i32, <8 x i16> } %6, 1 # | ret <8 x i16> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vshlcq_m_u32(<4 x i32> noundef %a, ptr noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | # | ... # `---data was truncated (10240/11454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dc84a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dc84a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dc84a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f15e5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15e598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f15e5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f15e591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dc8438e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dc8438c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dc841db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dc80cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dc80ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f15e591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15e591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15e591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dc80cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vshlc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c (2024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c8efe915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c8efe60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c8efe989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe4b4105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe4b415c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe4b4105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4b40ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c8ef7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c8ef7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c8ef63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c8ec130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c8ec12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe4b40eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4b40ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4b40ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c8ec12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (2025 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, # | ... # `---data was truncated (10240/29443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c610f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c610ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c610f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe870e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe870ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe870e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe870e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c61087e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c61087c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c6106cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c60d1c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c60d1bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe870e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe870e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe870e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c60d1bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/WebAssembly/builtins-table-externref.c (2026 of 27911) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-externref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | @const_table = internal addrspace(1) constant [0 x target("wasm.externref")] zeroinitializer, align 1 # | @other_table = internal addrspace(1) global [0 x target("wasm.externref")] zeroinitializer, align 1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.externref") @test_builtin_wasm_table_get_const(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.externref") @llvm.wasm.table.get.externref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.externref") %1 # | } # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.externref(ptr addrspace(1), i32, target("wasm.externref")) #2 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set_const(i32 noundef %index, target("wasm.externref") %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1) # | %2 = load i32, ptr %index.addr, align 4 # | %3 = load target("wasm.externref"), ptr %ref.addr, align 1 # | call void @llvm.wasm.table.set.externref(ptr addrspace(1) @const_table, i32 %2, target("wasm.externref") %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.externref(ptr addrspace(1) @table, target("wasm.externref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.externref(ptr addrspace(1), target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.externref") %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.externref"), align 1 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.externref") %ref, ptr %ref.addr, align 1 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.externref"), ptr %ref.addr, align 1 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.externref(ptr addrspace(1) @table, i32 %0, target("wasm.externref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.externref(ptr addrspace(1), i32, target("wasm.externref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed97ef915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed97ef60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed97ef989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5729c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5729ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5729c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5729c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed97e8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed97e8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed97e73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed97b230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed97b22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5729c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5729c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5729c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed97b22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-externref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c (2027 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c (2028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cab8a2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cab8a200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cab8a2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8d9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8d918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8d9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8d911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cab89b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cab89b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cab899db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cab864d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cab864cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd8d911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8d911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8d911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cab864ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/SystemZ/zvector.c (2029 of 27911) ******************** TEST 'Clang :: CodeGen/SystemZ/zvector.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple s390x-linux-gnu -target-cpu z13 -fzvector -emit-llvm -o - -W -Wall -Werror /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c" # | target datalayout = "E-S64-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" # | target triple = "s390x-unknown-linux-gnu" # | # | @sc2 = global <16 x i8> zeroinitializer, align 8 # | @sc = global <16 x i8> zeroinitializer, align 8 # | @uc2 = global <16 x i8> zeroinitializer, align 8 # | @uc = global <16 x i8> zeroinitializer, align 8 # | @ss2 = global <8 x i16> zeroinitializer, align 8 # | @ss = global <8 x i16> zeroinitializer, align 8 # | @us2 = global <8 x i16> zeroinitializer, align 8 # | @us = global <8 x i16> zeroinitializer, align 8 # | @si2 = global <4 x i32> zeroinitializer, align 8 # | @si = global <4 x i32> zeroinitializer, align 8 # | @ui2 = global <4 x i32> zeroinitializer, align 8 # | @ui = global <4 x i32> zeroinitializer, align 8 # | @sl2 = global <2 x i64> zeroinitializer, align 8 # | @sl = global <2 x i64> zeroinitializer, align 8 # | @ul2 = global <2 x i64> zeroinitializer, align 8 # | @ul = global <2 x i64> zeroinitializer, align 8 # | @slll2 = global <1 x i128> zeroinitializer, align 8 # | @slll = global <1 x i128> zeroinitializer, align 8 # | @ulll2 = global <1 x i128> zeroinitializer, align 8 # | @ulll = global <1 x i128> zeroinitializer, align 8 # | @fd2 = global <2 x double> zeroinitializer, align 8 # | @fd = global <2 x double> zeroinitializer, align 8 # | @bc2 = global <16 x i8> zeroinitializer, align 8 # | @bc = global <16 x i8> zeroinitializer, align 8 # | @bs2 = global <8 x i16> zeroinitializer, align 8 # | @bs = global <8 x i16> zeroinitializer, align 8 # | @bi2 = global <4 x i32> zeroinitializer, align 8 # | @bi = global <4 x i32> zeroinitializer, align 8 # | @bl2 = global <2 x i64> zeroinitializer, align 8 # | @bl = global <2 x i64> zeroinitializer, align 8 # | @blll2 = global <1 x i128> zeroinitializer, align 8 # | @blll = global <1 x i128> zeroinitializer, align 8 # | @cnt = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_assign() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_pos() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | store volatile <16 x i8> %0, ptr @sc, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | store volatile <16 x i8> %1, ptr @uc, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | store volatile <8 x i16> %2, ptr @ss, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | store volatile <8 x i16> %3, ptr @us, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | store volatile <4 x i32> %4, ptr @si, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | store volatile <4 x i32> %5, ptr @ui, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | store volatile <2 x i64> %6, ptr @sl, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | store volatile <2 x i64> %7, ptr @ul, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | store volatile <1 x i128> %8, ptr @slll, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | store volatile <1 x i128> %9, ptr @ulll, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | store volatile <2 x double> %10, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_neg() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %sub = sub <16 x i8> zeroinitializer, %0 # | store volatile <16 x i8> %sub, ptr @sc, align 8 # | %1 = load volatile <8 x i16>, ptr @ss2, align 8 # | %sub1 = sub <8 x i16> zeroinitializer, %1 # | store volatile <8 x i16> %sub1, ptr @ss, align 8 # | %2 = load volatile <4 x i32>, ptr @si2, align 8 # | %sub2 = sub <4 x i32> zeroinitializer, %2 # | store volatile <4 x i32> %sub2, ptr @si, align 8 # | %3 = load volatile <2 x i64>, ptr @sl2, align 8 # | %sub3 = sub <2 x i64> zeroinitializer, %3 # | store volatile <2 x i64> %sub3, ptr @sl, align 8 # | %4 = load volatile <1 x i128>, ptr @slll2, align 8 # | %sub4 = sub <1 x i128> zeroinitializer, %4 # | store volatile <1 x i128> %sub4, ptr @slll, align 8 # | %5 = load volatile <2 x double>, ptr @fd2, align 8 # | %fneg = fneg <2 x double> %5 # | store volatile <2 x double> %fneg, ptr @fd, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_preinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_postinc() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %inc = add <16 x i8> %0, splat (i8 1) # | store volatile <16 x i8> %inc, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %inc1 = add <16 x i8> %1, splat (i8 1) # | store volatile <16 x i8> %inc1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %inc2 = add <8 x i16> %2, splat (i16 1) # | store volatile <8 x i16> %inc2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %inc3 = add <8 x i16> %3, splat (i16 1) # | store volatile <8 x i16> %inc3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %inc4 = add <4 x i32> %4, splat (i32 1) # | store volatile <4 x i32> %inc4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %inc5 = add <4 x i32> %5, splat (i32 1) # | store volatile <4 x i32> %inc5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %inc6 = add <2 x i64> %6, splat (i64 1) # | store volatile <2 x i64> %inc6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %inc7 = add <2 x i64> %7, splat (i64 1) # | store volatile <2 x i64> %inc7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %inc8 = add <1 x i128> %8, splat (i128 1) # | store volatile <1 x i128> %inc8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %inc9 = add <1 x i128> %9, splat (i128 1) # | store volatile <1 x i128> %inc9, ptr @ulll2, align 8 # | %10 = load volatile <2 x double>, ptr @fd2, align 8 # | %inc10 = fadd <2 x double> %10, splat (double 1.000000e+00) # | store volatile <2 x double> %inc10, ptr @fd2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @test_predec() #0 { # | entry: # | %0 = load volatile <16 x i8>, ptr @sc2, align 8 # | %dec = add <16 x i8> %0, splat (i8 -1) # | store volatile <16 x i8> %dec, ptr @sc2, align 8 # | %1 = load volatile <16 x i8>, ptr @uc2, align 8 # | %dec1 = add <16 x i8> %1, splat (i8 -1) # | store volatile <16 x i8> %dec1, ptr @uc2, align 8 # | %2 = load volatile <8 x i16>, ptr @ss2, align 8 # | %dec2 = add <8 x i16> %2, splat (i16 -1) # | store volatile <8 x i16> %dec2, ptr @ss2, align 8 # | %3 = load volatile <8 x i16>, ptr @us2, align 8 # | %dec3 = add <8 x i16> %3, splat (i16 -1) # | store volatile <8 x i16> %dec3, ptr @us2, align 8 # | %4 = load volatile <4 x i32>, ptr @si2, align 8 # | %dec4 = add <4 x i32> %4, splat (i32 -1) # | store volatile <4 x i32> %dec4, ptr @si2, align 8 # | %5 = load volatile <4 x i32>, ptr @ui2, align 8 # | %dec5 = add <4 x i32> %5, splat (i32 -1) # | store volatile <4 x i32> %dec5, ptr @ui2, align 8 # | %6 = load volatile <2 x i64>, ptr @sl2, align 8 # | %dec6 = add <2 x i64> %6, splat (i64 -1) # | store volatile <2 x i64> %dec6, ptr @sl2, align 8 # | %7 = load volatile <2 x i64>, ptr @ul2, align 8 # | %dec7 = add <2 x i64> %7, splat (i64 -1) # | store volatile <2 x i64> %dec7, ptr @ul2, align 8 # | %8 = load volatile <1 x i128>, ptr @slll2, align 8 # | %dec8 = add <1 x i128> %8, splat (i128 -1) # | store volatile <1 x i128> %dec8, ptr @slll2, align 8 # | %9 = load volatile <1 x i128>, ptr @ulll2, align 8 # | %dec # | ... # `---data was truncated (10240/152876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2bc3d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2bc3ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c2bc3d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eeef33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eeef8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eeef33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eeef1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c2bc366e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c2bc366c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c2bc34bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2bbffb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c2bbffadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5eeef1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eeef1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eeef1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c2bbffacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/SystemZ/zvector.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c (2030 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | st # | ... # `---data was truncated (10240/110292) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055824578615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582457830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055824578689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f158c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f158c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f158c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f158c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055824571be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055824571bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558245700b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582453b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582453afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f158c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f158c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f158c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582453afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll (2031 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll >/usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/supports-hot-cold-new.ll.tmp.o # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/supports-hot-cold-new.ll # | #0 0x0000557395ab515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557395ab20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557395ab589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f883b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f883b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f883b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f883b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557395a4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557395a4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557395a2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573956df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005573956dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f883b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f883b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f883b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573956decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c (2032 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg4ei8_v_f64m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tu # | ... # `---data was truncated (10240/99186) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561a800915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561a80060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561a800989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f78449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f78449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f78431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561a7f9ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561a7f9ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561a7f83b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561a7c330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561a7c32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f78432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f784330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561a7c32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c (2033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei8_v_bf16m1x3_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c (2034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c (2035 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vand.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vand.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vand_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055904fd9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055904fd980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055904fd9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb533e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb533ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb533e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb533e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055904fd30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055904fd30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055904fd15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055904f9c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055904f9c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb533e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb533e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb533e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055904f9c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c (2036 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d6811f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d6811c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d6811f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88e8a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88e8a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88e8a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88e8a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d680b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d680b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d68099b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d67d490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d67d48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f88e8a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88e8a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88e8a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d67d48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c (2037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_f32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste32.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_i32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste32_u32(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste32.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed21cad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed21caa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed21cad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f322af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f322af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f322af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f322af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed21c42e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed21c42c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed21c27b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed218d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed218d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f322af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f322af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f322af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed218d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c (2038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566dc79215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566dc78f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566dc79289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfa2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfa22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfa2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfa2231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566dc727e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566dc727c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566dc70cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566dc3bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566dc3bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfa2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfa22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfa22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566dc3bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c (2039 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf8x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_u8m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055774ecb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055774ecae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055774ecb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2484649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24846a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2484649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2484631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055774ec46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055774ec46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055774ec2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055774e8db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055774e8dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2484632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24846330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24846330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055774e8dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c (2040 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a34f75c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a34f7590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a34f75c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4223533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f422358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4223533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f422351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a34f6f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a34f6f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a34f6d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a34f3860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a34f385dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f422351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f422351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f422351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a34f385cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c (2041 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +f16f32dot -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | store <4 x half> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vdot1.i = bitcast <8 x i8> %4 to <4 x half> # | %vdot2.i = bitcast <8 x i8> %5 to <4 x half> # | %vdot3.i = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot.i, <4 x half> %vdot1.i, <4 x half> %vdot2.i) # | store <2 x float> %vdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <4 x float>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %1, ptr %__p1.addr.i, align 16 # | store <8 x half> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vdot1.i = bitcast <16 x i8> %4 to <8 x half> # | %vdot2.i = bitcast <16 x i8> %5 to <8 x half> # | %vdot3.i = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot.i, <8 x half> %vdot1.i, <8 x half> %vdot2.i) # | store <4 x float> %vdot3.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 16 # | store <4 x float> %6, ptr %__ret.i, align 16 # | %7 = load <4 x float>, ptr %__ret.i, align 16 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_lane_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <4 x i32> zeroinitializer # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float>, <4 x half>, <4 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vdot_laneq_f32_f16(<2 x float> noundef %r, <4 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %__s1 = alloca <4 x half>, align 8 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0, align 8 # | %1 = load <4 x half>, ptr %a.addr, align 8 # | store <4 x half> %1, ptr %__s1, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <8 x i8>, ptr %__s0, align 8 # | %4 = load <8 x i8>, ptr %__s1, align 8 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <4 x i32> # | %vdot = bitcast <8 x i8> %3 to <2 x float> # | %vdot1 = bitcast <8 x i8> %4 to <4 x half> # | %vdot2 = call <2 x float> @llvm.aarch64.neon.fdot.v2f32.v4f16(<2 x float> %vdot, <4 x half> %vdot1, <4 x half> %lane) # | store <2 x float> %vdot2, ptr %ref.tmp, align 8 # | %7 = load <2 x float>, ptr %ref.tmp, align 8 # | store <2 x float> %7, ptr %__ret, align 8 # | %8 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %8, ptr %tmp, align 8 # | %9 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %9 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_lane_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <4 x half>, align 8 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <4 x half>, align 8 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %2, ptr %__s2, align 8 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <8 x i8>, ptr %__s2, align 8 # | %6 = bitcast <8 x i8> %5 to <4 x half> # | %lane = shufflevector <4 x half> %6, <4 x half> %6, <8 x i32> zeroinitializer # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float> %vdot, <8 x half> %vdot1, <8 x half> %lane) # | store <4 x float> %vdot2, ptr %ref.tmp, align 16 # | %7 = load <4 x float>, ptr %ref.tmp, align 16 # | store <4 x float> %7, ptr %__ret, align 16 # | %8 = load <4 x float>, ptr %__ret, align 16 # | store <4 x float> %8, ptr %tmp, align 16 # | %9 = load <4 x float>, ptr %tmp, align 16 # | ret <4 x float> %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.aarch64.neon.fdot.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vdotq_laneq_f32_f16(<4 x float> noundef %r, <8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %r.addr = alloca <4 x float>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %__ret = alloca <4 x float>, align 16 # | %__s0 = alloca <4 x float>, align 16 # | %__s1 = alloca <8 x half>, align 16 # | %__s2 = alloca <8 x half>, align 16 # | %ref.tmp = alloca <16 x i8>, align 16 # | %tmp = alloca <4 x float>, align 16 # | store <4 x float> %r, ptr %r.addr, align 16 # | store <8 x half> %a, ptr %a.addr, align 16 # | store <8 x half> %b, ptr %b.addr, align 16 # | %0 = load <4 x float>, ptr %r.addr, align 16 # | store <4 x float> %0, ptr %__s0, align 16 # | %1 = load <8 x half>, ptr %a.addr, align 16 # | store <8 x half> %1, ptr %__s1, align 16 # | %2 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %2, ptr %__s2, align 16 # | %3 = load <16 x i8>, ptr %__s0, align 16 # | %4 = load <16 x i8>, ptr %__s1, align 16 # | %5 = load <16 x i8>, ptr %__s2, align 16 # | %6 = bitcast <16 x i8> %5 to <8 x half> # | %lane = shufflevector <8 x half> %6, <8 x half> %6, <8 x i32> # | %vdot = bitcast <16 x i8> %3 to <4 x float> # | %vdot1 = bitcast <16 x i8> %4 to <8 x half> # | %vdot2 = call <4 x float> @llvm.aa # | ... # `---data was truncated (10240/11256) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,instcombine # | #0 0x000055847a19d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055847a19a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055847a19d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8219333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f821938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8219333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f821931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055847a132e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055847a132c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055847a117b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558479dc70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558479dc6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f821931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f821931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f821931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558479dc6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/f16f32dot-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c (2042 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64 -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u32(<2 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p8(<8 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_p16(<4 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_u64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vreinterpret_bf16_s64(<1 x i64> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <4 x bfloat>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | %1 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__ret.i, align 8 # | %2 = load <4 x bfloat>, ptr %__ret.i, align 8 # | ret <4 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_s32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x float>, align 16 # | store <4 x float> %a, ptr %a.addr, align 16 # | %0 = load <4 x float>, ptr %a.addr, align 16 # | store <4 x float> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u8(<16 x i8> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %a, ptr %a.addr, align 16 # | %0 = load <16 x i8>, ptr %a.addr, align 16 # | store <16 x i8> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u16(<8 x i16> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | %1 = load <8 x bfloat>, ptr %__p0.addr.i, align 16 # | store <8 x bfloat> %1, ptr %__ret.i, align 16 # | %2 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vreinterpretq_bf16_u32(<4 x i32> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | %0 = load # | ... # `---data was truncated (10240/31171) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055bfc5dd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bfc5dcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bfc5dd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff5c9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff5c9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff5c9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5c9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bfc5d65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bfc5d65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bfc5d4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bfc59fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bfc59f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff5c9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5c9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5c9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bfc59f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-reinterpret-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c (2043 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005561e66ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561e66fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561e66ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f843ca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f843caa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f843ca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f843ca31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561e6694e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561e6694c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561e6679b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561e63290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561e6328dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f843ca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f843ca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f843ca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561e6328cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c (2044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_ # | ... # `---data was truncated (10240/11895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e9ed2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e9ed2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e9ed2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18af649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18af6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18af649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18af631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e9ecc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e9ecc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e9eca8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e9e9580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e9e957dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f18af632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18af6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18af6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e9e957cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c (2045 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e221e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e221e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e221e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f97449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f97449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f97431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e2217de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e2217dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e22162b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e21e120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e21e11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f97432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f974330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e21e11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c (2046 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxei32_v_f32m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8f32.p0.nxv8i32.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | ... # `---data was truncated (10240/120907) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559cec54115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559cec53e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559cec54189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcc5a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcc5a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcc5a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcc5a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cec4d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559cec4d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559cec4bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559cec16b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559cec16add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcc5a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcc5a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcc5a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cec16acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c (2047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7ca6d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7ca6cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7ca6d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcca7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcca7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcca7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcca7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7ca665e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e7ca665c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e7ca64ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e7ca2fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e7ca2f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcca7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcca7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcca7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7ca2f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c (2048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i6 # | ... # `---data was truncated (10240/151253) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567442d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567442d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567442d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc643f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc643f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc643f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc643eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556744269e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556744269c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055674424eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556743efe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556743efddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc643eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc643eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc643eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556743efdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c (2049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a38c32215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a38c31f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a38c32289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8826a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8826a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8826a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8826a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a38c2b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a38c2b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a38c29cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a38bf4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a38bf4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8826a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8826a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8826a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a38bf4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c (2050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650cae2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650cae240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650cae2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f119341bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11934725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f119341ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1193403507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650cadbce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650cadbcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650cada1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650caa510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650caa50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1193404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11934050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11934050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650caa50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c (2051 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmin.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmin.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmin_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/97647) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db391af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db391ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db391af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0c3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0c3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0c3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0c3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db39144e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db39144c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db39129b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db38dd90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db38dd8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0c3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0c3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0c3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db38dd8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c (2052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_f16m4_tu( %maske # | ... # `---data was truncated (10240/157777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557557ba315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557557ba00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557557ba389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f391fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f391fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f391fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f391fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557557b38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557557b38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557557b1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575577cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575577ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f391fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f391fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f391fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575577cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c (2053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055897d40815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055897d4050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055897d40889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb61e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb61e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb61e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb61e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055897d39de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055897d39dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055897d382b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055897d0320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055897d031dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb61e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb61e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb61e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055897d031cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c (2054 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af6bbe615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055af6bbe30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055af6bbe689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f846f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f846f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f846f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f846f203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af6bb7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055af6bb7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055af6bb60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af6b8100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af6b80fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f846f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f846f2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f846f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af6b80fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c (2055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055733003b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573300380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055733003b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2927b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2927b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2927b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2927b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055732ffd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055732ffd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055732ffb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055732fc650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055732fc64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2927b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2927b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2927b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055732fc64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c (2056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c22d3415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561c22d310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561c22d3489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85a401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85a40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85a401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85a4003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c22cc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561c22cc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561c22caeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561c2295e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561c2295ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85a4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85a40050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85a40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c2295dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c (2057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec963b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec963b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec963b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f132fe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f132fea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f132fe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f132fe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec9634ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec9634ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec9632fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec95fdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec95fdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f132fe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f132fe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f132fe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec95fdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c (2058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_u32m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf715ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf715c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf715ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c76a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c76aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c76a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c76a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf7155fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf7155fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf71544b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf711f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf711f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c76a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c76a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c76a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf711f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c (2059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei64_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/94227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f373c0315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f373c000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f373c0389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b84d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b84d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b84d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b84d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f373b98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f373b98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f373b7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f37382d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f37382cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b84d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b84d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b84d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f37382ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c (2060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f109b2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f109b230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f109b2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febf5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febf52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febf5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febf5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f109abbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f109abbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f109aa0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1097500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f10974fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007febf5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febf52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febf52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f10974fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c (2061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce47ce715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce47ce40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce47ce789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2caf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2caf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2caf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2caf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce47c7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce47c7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce47c61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce479110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce47910dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd2caf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2caf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2caf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce47910cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c (2062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso # | ... # `---data was truncated (10240/148012) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0c097d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0c097a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0c097d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dc6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dc6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dc6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dc6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0c0912e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0c0912c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f0c08f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0c05a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f0c05a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dc6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dc6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dc6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0c05a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c (2063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562def97e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562def97b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562def97e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5b6d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5b6d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5b6d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5b6d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562def913e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562def913c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562def8f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562def5a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562def5a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5b6d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5b6d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5b6d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562def5a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c (2064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 # | ... # `---data was truncated (10240/67006) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557e20c5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557e20c5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557e20c5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f033fd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f033fd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f033fd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f033fd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557e20bf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557e20bf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557e20bd7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557e208870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557e20886dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f033fd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f033fd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f033fd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557e20886cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c (2065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c (2066 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vas # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6399fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6399fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6399fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7942249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79422a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7942249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7942231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f639993e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f639993c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f639978b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6396280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f639627dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7942232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79422330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79422330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f639627cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c (2067 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c (2068 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f45ca315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f45ca00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f45ca389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8a0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8a038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8a0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8a031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f45c38e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f45c38c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f45c1db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f458cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f458ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd8a031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8a031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8a031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f458cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c (2069 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bf # | ... # `---data was truncated (10240/65202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e250d4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e250d440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e250d4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ac1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ac1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ac1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ac1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e250cdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e250cdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e250cc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e2509710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e250970dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ac1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ac1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ac1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e250970cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/2008-07-17-no-emit-on-error.c (2070 of 27911) ******************** TEST 'Clang :: CodeGen/2008-07-17-no-emit-on-error.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: rm -f /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -DPASS /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2008-07-17-no-emit-on-error.c -emit-llvm-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/2008-07-17-no-emit-on-error.c.tmp1.bc -disable-output # | #0 0x000055d49579215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d49578f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d49579289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9592449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95924a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9592449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9592431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d495727e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d495727c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d49570cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d4953bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d4953bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9592432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95924330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95924330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4953bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c (2071 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1_tu( %maskedoff, %src, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind # | ... # `---data was truncated (10240/77062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c420b9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c420b9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c420b9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f62e0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62e018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f62e0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f62e011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c420b34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c420b34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c420b19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4207c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4207c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f62e011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62e011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62e011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4207c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c (2072 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c (2073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu.c (2074 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_abs(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.abs.i32(i32 %0, i1 true) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.abs.i32(i32, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp sle i32 %0, %1 # | %sle = zext i1 %2 to i32 # | ret i32 %sle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = icmp ule i32 %0, %1 # | %sleu = zext i1 %2 to i32 # | ret i32 %sleu # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = sext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exths = sext i16 %1 to i32 # | ret i32 %exths # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %conv = zext i16 %0 to i32 # | %1 = trunc i32 %conv to i16 # | %exthz = zext i16 %1 to i32 # | ret i32 %exthz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = sext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbs = sext i8 %1 to i32 # | ret i32 %extbs # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %conv = zext i8 %0 to i32 # | %1 = trunc i32 %conv to i8 # | %extbz = zext i8 %1 to i32 # | ret i32 %extbz # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clip(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clip(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call i32 @llvm.riscv.cv.alu.clipu(i32 %0, i32 15) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.clipu(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.addRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.addRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.adduRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subRN(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subuRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.cv.alu.subuRN(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.cv.alu.subuRN(i32, i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xcvalu" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xcvalu1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608c688d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005608c688a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005608c688d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde59249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde592a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde59249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde59231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608c6822e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005608c6822c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005608c6807b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005608c64b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005608c64b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde59232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde592330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde592330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608c64b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c (2075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1_tu( %vd, %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load bfloat, ptr %rs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c (2076 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604b42b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604b42b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604b42b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa22d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa22d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa22d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa22d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604b424ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604b424cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604b4231b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604b3ee10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604b3ee0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa22d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa22d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa22d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604b3ee0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c (2077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vx_u16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccu_vv_u16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.ad # | ... # `---data was truncated (10240/79671) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9fb96215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9fb95f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9fb96289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b47e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b47ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b47e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b47e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9fb8f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9fb8f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9fb8dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9fb58c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9fb58bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3b47e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b47e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b47e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9fb58bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c (2078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv64i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv64i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv32i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv32i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv16i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv16i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv8i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv8i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b16(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv4i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv4i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b32(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv2i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv2i1.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsm_v_b64(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsm.nxv1i1.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsm.nxv1i1.p0.i64(, ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567e5fd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567e5fd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567e5fd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde73449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde734a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde73449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde73431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567e5f6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567e5f6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567e5f53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567e5c030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005567e5c02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde73432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde734330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde734330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567e5c02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c (2079 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vcreate_bf16(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <4 x bfloat>, ptr %__promote, align 8 # | store <4 x bfloat> %1, ptr %__ret, align 8 # | %2 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %2, ptr %tmp, align 8 # | %3 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> noundef %low, <4 x bfloat> noundef %high) #0 { # | entry: # | %__p0.addr.i = alloca <4 x bfloat>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <8 x bfloat>, align 16 # | %low.addr = alloca <4 x bfloat>, align 8 # | %high.addr = alloca <4 x bfloat>, align 8 # | store <4 x bfloat> %low, ptr %low.addr, align 8 # | store <4 x bfloat> %high, ptr %high.addr, align 8 # | %0 = load <4 x bfloat>, ptr %low.addr, align 8 # | %1 = load <4 x bfloat>, ptr %high.addr, align 8 # | store <4 x bfloat> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | %2 = load <4 x bfloat>, ptr %__p0.addr.i, align 8 # | %3 = load <4 x bfloat>, ptr %__p1.addr.i, align 8 # | %shuffle.i = shufflevector <4 x bfloat> %2, <4 x bfloat> %3, <8 x i32> # | store <8 x bfloat> %shuffle.i, ptr %__ret.i, align 16 # | %4 = load <8 x bfloat>, ptr %__ret.i, align 16 # | ret <8 x bfloat> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x bfloat> @test_vset_lane_bf16(bfloat noundef %a, <4 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <4 x bfloat>, align 8 # | %__ret = alloca <4 x bfloat>, align 8 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <4 x bfloat>, align 8 # | %tmp = alloca <4 x bfloat>, align 8 # | store bfloat %a, ptr %a.addr, align 2 # | store <4 x bfloat> %v, ptr %v.addr, align 8 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <4 x bfloat>, ptr %v.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1, align 8 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <4 x bfloat>, ptr %__s1, align 8 # | %vset_lane = insertelement <4 x bfloat> %3, bfloat %2, i32 1 # | store <4 x bfloat> %vset_lane, ptr %ref.tmp, align 8 # | %4 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x bfloat> %4, ptr %__ret, align 8 # | %5 = load <4 x bfloat>, ptr %__ret, align 8 # | store <4 x bfloat> %5, ptr %tmp, align 8 # | %6 = load <4 x bfloat>, ptr %tmp, align 8 # | ret <4 x bfloat> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x bfloat> @test_vsetq_lane_bf16(bfloat noundef %a, <8 x bfloat> noundef %v) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | %v.addr = alloca <8 x bfloat>, align 16 # | %__ret = alloca <8 x bfloat>, align 16 # | %__s0 = alloca bfloat, align 2 # | %__s1 = alloca <8 x bfloat>, align 16 # | %ref.tmp = alloca <8 x bfloat>, align 16 # | %tmp = alloca <8 x bfloat>, align 16 # | store bfloat %a, ptr %a.addr, align 2 # | store <8 x bfloat> %v, ptr %v.addr, align 16 # | %0 = load bfloat, ptr %a.addr, align 2 # | store bfloat %0, ptr %__s0, align 2 # | %1 = load <8 x bfloat>, ptr %v.addr, align 16 # | store <8 x bfloat> %1, ptr %__s1, align 16 # | %2 = load bfloat, ptr %__s0, align 2 # | %3 = load <8 x bfloat>, ptr %__s1, align 16 # | %vset_lane = insertelement <8 x bfloat> %3, bfloat %2, i32 7 # | store <8 x bfloat> %vset_lane, ptr %ref.tmp, align 16 # | %4 = load <8 x bfloat>, ptr %ref.tmp, align 16 # | store <8 x bfloat> %4, ptr %__ret, align 16 # | %5 = load <8 x bfloat>, ptr %__ret, align 16 # | store <8 x bfloat> %5, ptr %tmp, align 16 # | %6 = load <8 x bfloat>, ptr %tmp, align 16 # | ret <8 x bfloat> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ca9d5f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca9d5f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca9d5f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ac1533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ac158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ac1533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ac151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca9d58ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca9d58cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca9d571b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca9d2210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca9d220dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ac151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ac151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ac151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca9d220cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c (2080 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee424eb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee424e80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee424eb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f103e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f103e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f103e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f103e031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee42480e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee42480c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee42465b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee421150b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee42114dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f103e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f103e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f103e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee42114cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c (2081 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsadd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsadd_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e98626715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9862640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e98626789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67c8705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67c875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67c8705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67c86ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9861fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9861fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9861e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e985e910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e985e90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f67c86eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67c86ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67c86ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e985e90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c (2082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbdb3a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bbdb3a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bbdb3a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a56049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a560a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a56049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a56031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbdb339e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bbdb339c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bbdb31eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bbdafce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bbdafcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a56032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a560330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a560330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbdafcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c (2083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, pt # | ... # `---data was truncated (10240/32701) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ce963115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ce962e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ce963189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72bb133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72bb18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72bb133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72bb11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ce95c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ce95c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ce95abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ce925b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ce925add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72bb11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72bb11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72bb11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ce925acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c (2084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f21646715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f2164640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f21646789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ff0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ff038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ff0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ff031b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2163fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f2163fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f2163e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f2160910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f216090dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ff031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ff031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ff031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f216090cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c (2085 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/79861) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d4ca56f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d4ca56c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d4ca56f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f058e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f058e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f058e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f058e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d4ca504e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d4ca504c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d4ca4e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d4ca1990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d4ca198dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f058e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f058e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f058e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d4ca198cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c (2086 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f03c02215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f03c01f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f03c02289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07d3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07d358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07d3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07d351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f03bfb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f03bfb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f03bf9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f03bc4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f03bc4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f07d351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07d351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07d351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f03bc4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c (2087 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4_tu( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f3 # | ... # `---data was truncated (10240/179503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b057f0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b057f0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b057f0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1746e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1746ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1746e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1746e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b057ea2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b057ea2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b057e87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b057b370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b057b36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1746e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1746e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1746e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b057b36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c (2088 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2, # | ... # `---data was truncated (10240/34589) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a9af11e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a9af11b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a9af11e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc27d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc27d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc27d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc27d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a9af0b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a9af0b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a9af098b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a9aed480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a9aed47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc27d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc27d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc27d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a9aed47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c (2089 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadd.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadd.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadd_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556dfa76f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556dfa76c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556dfa76f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1afe533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1afe58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1afe533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1afe51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556dfa704e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556dfa704c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556dfa6e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556dfa3990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556dfa398dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1afe51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1afe51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1afe51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556dfa398cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c (2090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056483dce015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056483dcdd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056483dce089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f57d0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f57d04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f57d0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f57d0431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056483dc75e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056483dc75c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056483dc5ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056483d90a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056483d909dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f57d0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f57d04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f57d04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056483d909cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c (2091 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/22107) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9e945415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9e94510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9e945489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fb9a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fb9aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fb9a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fb9a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9e93e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9e93e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9e93ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9e907e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9e907ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2fb9a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fb9a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fb9a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9e907dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-poly-add.c (2092 of 27911) ******************** TEST 'Clang :: CodeGen/arm-poly-add.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-arm-none-eabi -target-feature +neon -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.2a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i8> @test_vadd_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i8>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <8 x i8>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <8 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | store <8 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <8 x i8>, ptr %ref.tmp.i, align 8 # | store <8 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <8 x i8>, ptr %__ret.i, align 8 # | ret <8 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i16> @test_vadd_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <4 x i16> # | store <4 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <1 x i64> @test_vadd_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <1 x i64>, align 8 # | %__p1.addr.i = alloca <1 x i64>, align 8 # | %__ret.i = alloca <1 x i64>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <1 x i64>, align 8 # | %b.addr = alloca <1 x i64>, align 8 # | store <1 x i64> %a, ptr %a.addr, align 8 # | store <1 x i64> %b, ptr %b.addr, align 8 # | %0 = load <1 x i64>, ptr %a.addr, align 8 # | %1 = load <1 x i64>, ptr %b.addr, align 8 # | store <1 x i64> %0, ptr %__p0.addr.i, align 8 # | store <1 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <8 x i8> %2, %3 # | %5 = bitcast <8 x i8> %4 to <1 x i64> # | store <1 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <1 x i64>, ptr %ref.tmp.i, align 8 # | store <1 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <1 x i64>, ptr %__ret.i, align 8 # | ret <1 x i64> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vaddq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <16 x i8>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <16 x i8>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | store <16 x i8> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | store <16 x i8> %4, ptr %ref.tmp.i, align 8 # | %5 = load <16 x i8>, ptr %ref.tmp.i, align 8 # | store <16 x i8> %5, ptr %__ret.i, align 8 # | %6 = load <16 x i8>, ptr %__ret.i, align 8 # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vaddq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 8 # | %__p1.addr.i = alloca <8 x i16>, align 8 # | %__ret.i = alloca <8 x i16>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | store <8 x i16> %0, ptr %__p0.addr.i, align 8 # | store <8 x i16> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <8 x i16> # | store <8 x i16> %5, ptr %ref.tmp.i, align 8 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 8 # | store <8 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <8 x i16>, ptr %__ret.i, align 8 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vaddq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i64>, align 8 # | %__p1.addr.i = alloca <2 x i64>, align 8 # | %__ret.i = alloca <2 x i64>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = load <2 x i64>, ptr %b.addr, align 8 # | store <2 x i64> %0, ptr %__p0.addr.i, align 8 # | store <2 x i64> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %4 = xor <16 x i8> %2, %3 # | %5 = bitcast <16 x i8> %4 to <2 x i64> # | store <2 x i64> %5, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i64>, ptr %ref.tmp.i, align 8 # | store <2 x i64> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i64>, ptr %__ret.i, align 8 # | ret <2 x i64> %7 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.2-a,+neon,+v8.1a,+v8.2a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005637876d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005637876d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005637876d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c61933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c6198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c61933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c6191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056378766be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056378766bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563787650b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005637873000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005637872ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c6191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c6191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c6191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637872ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-poly-add.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c (2093 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b253fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558b253fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558b253fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d48705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d4875c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d48705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d486ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b25392e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558b25392c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558b25377b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558b250270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558b25026dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d486eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d486ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d486ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b25026cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c (2094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055626ffaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055626ffa70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055626ffaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8d3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8d318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8d3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8d311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055626ff3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055626ff3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055626ff24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055626fbd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055626fbd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc8d311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8d311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8d311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055626fbd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c (2095 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7c466815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7c46650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f7c466889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe91b81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe91b8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe91b81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe91b803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7c45fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f7c45fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f7c45e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f7c42920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f7c4291dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe91b804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe91b8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe91b8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7c4291cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c (2096 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/60334) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e892d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e892d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e892d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa39df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa39df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa39df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa39df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e89269e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e89269c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e8924eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e88efe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e88efddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa39df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa39df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa39df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e88efdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c (2097 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e94deaf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e94deac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e94deaf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd384a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd384aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd384a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd384a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e94de44e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e94de44c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e94de29b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e94dad90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e94dad8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd384a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd384a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd384a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e94dad8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c (2098 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf8_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vx_u8m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhu.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhu_vv_u8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | s # | ... # `---data was truncated (10240/223359) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df2756a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df275670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df2756a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a43533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a4358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a43533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a4351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df274ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df274ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df274e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df271940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df27193dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a4351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a4351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a4351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df27193cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c (2099 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv64i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv64i8.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i8.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_ # | ... # `---data was truncated (10240/15323) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556af570c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556af57090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556af570c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd77661bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7766725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd77661ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd776603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556af56a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556af56a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556af5686b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556af53360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556af5335dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd776604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7766050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7766050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556af5335cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c (2100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c (2101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f21e38c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f21e3890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f21e38c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02b3733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02b378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02b3733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02b371b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f21e321e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f21e321c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f21e306b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f21dfb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f21dfb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02b371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02b371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02b371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f21dfb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c (2102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c (2103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_u32m1x2_m( %mask, # | ... # `---data was truncated (10240/13544) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c5dcb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558c5dcb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558c5dcb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5411249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f54112a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5411249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5411231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c5dc48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558c5dc48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558c5dc2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558c5d8dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558c5d8dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5411232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54112330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54112330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c5d8dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c (2104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d10b7d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d10b7a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d10b7d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7efc533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7efc58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7efc533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7efc51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d10b12e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d10b12c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d10af7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d107a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d107a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7efc51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7efc51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7efc51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d107a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/thinlto_backend_local_name_conflict.ll (2105 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_backend_local_name_conflict.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 8 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -module-hash /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend_local_name_conflict.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend_local_name_conflict.ll.tmp.bc # | #0 0x000055ff534c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff534c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff534c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c91133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c9118a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c91133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c9111b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff5345ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff5345cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff53441b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff530f10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff530f0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c9111cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c9111d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c9111d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff530f0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c (2106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c (2107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055818731215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055818730f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055818731289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cee01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cee0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cee01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cee003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581872a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005581872a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055818728cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558186f3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558186f3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0cee004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cee0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cee0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558186f3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c (2108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6a4d2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6a4d230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6a4d2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61cd105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61cd15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61cd105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61cd0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6a4cbbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6a4cbbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6a4ca0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6a49500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6a494fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61cd0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61cd0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61cd0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6a494fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c (2109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1a82dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1a82d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1a82dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6df9933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6df998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6df9933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6df991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1a8271e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1a8271c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1a8256b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1a7f060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1a7f05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6df991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6df991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6df991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1a7f05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c (2110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/40795) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563fe648415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563fe64810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563fe648489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0dd3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0dd3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0dd3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0dd3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563fe6419e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563fe6419c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563fe63feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563fe60ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563fe60addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0dd3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0dd3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0dd3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563fe60adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c (2111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store tar # | ... # `---data was truncated (10240/30818) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005647e83a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005647e839f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005647e83a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59ae933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59ae98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59ae933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59ae91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647e8337e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005647e8337c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005647e831cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005647e7fcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005647e7fcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f59ae91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59ae91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59ae91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005647e7fcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c (2112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f481d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562f481d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562f481d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8891b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8891b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8891b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8891b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f4816ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562f4816ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562f4814fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562f47dff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562f47dfedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8891b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8891b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8891b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f47dfecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c (2113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c (2114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d8f20615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d8f2030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d8f20689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efe85849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efe858a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efe85849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efe85831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d8f19be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d8f19bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d8f180b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d8ee300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d8ee2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efe85832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efe858330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efe858330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d8ee2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c (2115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564cb6f0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564cb6f070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564cb6f0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1f61249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1f612a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1f61249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1f61231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564cb6e9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564cb6e9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564cb6e84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564cb6b340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564cb6b33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1f61232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1f612330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1f612330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564cb6b33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c (2116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vx_u8m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrol.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrol.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vrol_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.a # | ... # `---data was truncated (10240/97683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c0296115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c0295e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c0296189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2775049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f27750a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2775049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2775031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c028f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c028f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c028dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c0258b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c0258add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2775032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f27750330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f27750330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c0258acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c (2117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558113ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558113a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558113ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcfb1505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcfb155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcfb1505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcfb14ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555811340e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555811340c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555811325b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555810fd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555810fd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcfb14eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcfb14ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcfb14ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555810fd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c (2118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaadd.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaa # | ... # `---data was truncated (10240/99585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c730c1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c730c0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c730c1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dbca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dbcaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dbca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dbca31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c730ba7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c730ba7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c730b8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c73083c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c73083bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4dbca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dbca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dbca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c73083bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c (2119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align # | ... # `---data was truncated (10240/39416) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574327d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574327d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574327d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6313133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f631318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6313133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f631311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055743276ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055743276cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557432751b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574324010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557432400dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f631311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f631311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f631311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557432400cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c (2120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585606ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585606fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585606ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86d0049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86d00a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86d0049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86d0031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558560694e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558560694c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558560679b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585603290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558560328dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f86d0032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86d00330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86d00330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558560328cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c (2121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f394e9315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f394e900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f394e9389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56c2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56c278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56c2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56c271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f394e28e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f394e28c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f394e0db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f394abd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f394abcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56c271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56c271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56c271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f394abccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c (2122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c (2123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d48f6de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d48f6db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d48f6de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa03e905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa03e95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa03e905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa03e8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d48f673e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d48f673c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d48f658b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d48f3080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d48f307dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa03e8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa03e8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa03e8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d48f307cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c (2124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf8( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf4( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8mf2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m1( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vx_u8m2( %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vabdu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabdu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabdu_vv_u8m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align # | ... # `---data was truncated (10240/97506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056468cc4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056468cc400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056468cc4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97ee333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97ee38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97ee333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97ee31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056468cbd8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056468cbd8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056468cbbdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056468c86d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056468c86cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97ee31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97ee31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97ee31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056468c86ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c (2125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xcvalu -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sle(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp sle i32 %2, %3 # | %sle.i = zext i1 %4 to i32 # | ret i32 %sle.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_sleu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = icmp ule i32 %2, %3 # | %sleu.i = zext i1 %4 to i32 # | ret i32 %sleu.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_min(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.smin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_minu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.min.i = call i32 @llvm.umin.i32(i32 %2, i32 %3) # | ret i32 %elt.min.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_max(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.smax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_maxu(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %elt.max.i = call i32 @llvm.umax.i32(i32 %2, i32 %3) # | ret i32 %elt.max.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exths(i16 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = sext i16 %1 to i32 # | %exths.i = sext i16 %1 to i32 # | ret i32 %exths.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_exthz(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i16, align 2 # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %a.addr.i, align 2 # | %1 = load i16, ptr %a.addr.i, align 2 # | %conv.i = zext i16 %1 to i32 # | %exthz.i = zext i16 %1 to i32 # | ret i32 %exthz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbs(i8 noundef signext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = sext i8 %1 to i32 # | %extbs.i = sext i8 %1 to i32 # | ret i32 %extbs.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_extbz(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr.i = alloca i8, align 1 # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | store i8 %0, ptr %a.addr.i, align 1 # | %1 = load i8, ptr %a.addr.i, align 1 # | %conv.i = zext i8 %1 to i32 # | %extbz.i = zext i8 %1 to i32 # | ret i32 %extbz.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clip(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clip(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_clipu(i32 noundef %a) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 0, ptr %b.addr.i, align 4 # | %1 = load i32, ptr %a.addr.i, align 4 # | %2 = load i32, ptr %b.addr.i, align 4 # | %3 = call i32 @llvm.riscv.cv.alu.clipu(i32 %1, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_addRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.addRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_adduRN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %a.addr.i, align 4 # | store i32 %1, ptr %b.addr.i, align 4 # | store i8 0, ptr %shft.addr.i, align 1 # | %2 = load i32, ptr %a.addr.i, align 4 # | %3 = load i32, ptr %b.addr.i, align 4 # | %4 = load i8, ptr %shft.addr.i, align 1 # | %conv.i = zext i8 %4 to i32 # | %5 = call i32 @llvm.riscv.cv.alu.adduRN(i32 %2, i32 %3, i32 %conv.i) # | ret i32 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_alu_subN(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr.i = alloca i32, align 4 # | %b.addr.i = alloca i32, align 4 # | %shft.addr.i = alloca i8, align 1 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | st # | ... # `---data was truncated (10240/15696) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d81fb4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d81fb470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d81fb4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9eb0f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9eb0f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9eb0f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9eb0eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d81fadfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d81fadfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d81fac4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d81f7740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d81f773dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9eb0eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9eb0eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9eb0eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d81f773cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c (2126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f16m8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei16_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i16.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c (2127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005640e61f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640e61f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005640e61f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf8cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf8cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf8cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf8cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005640e618be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005640e618bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005640e6170b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640e5e200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640e5e1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbf8cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf8cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf8cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640e5e1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c (2128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cfe1e6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cfe1e650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cfe1e6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3979b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3979b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3979b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3979aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cfe1dfde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cfe1dfdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cfe1de2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cfe1a920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cfe1a91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3979aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3979aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3979aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cfe1a91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c (2129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Fun # | ... # `---data was truncated (10240/40883) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639ce01e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639ce01b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639ce01e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c7e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c7e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c7e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c7e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639cdfb3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639cdfb3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639cdf98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639cdc480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639cdc47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c7e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c7e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c7e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639cdc47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c (2130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5098a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a50989f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a5098a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb390f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb390f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb390f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb390f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a509837e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a509837c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a50981cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5094cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a5094cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb390f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb390f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb390f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5094cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c (2131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("ri # | ... # `---data was truncated (10240/32023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a9f42415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a9f4210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a9f42489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61fcc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61fcca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61fcc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61fcc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a9f3b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a9f3b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a9f39eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a9f04e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a9f04ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61fcc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61fcc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61fcc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a9f04dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c (2132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv1bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv2bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( %value) #0 { # | entry: # | %value.addr = alloca # | ... # `---data was truncated (10240/12137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dddeb5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dddeb560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dddeb5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d8e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d8e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d8e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d8e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dddeaeee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dddeaeec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dddead3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ddde7830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ddde782dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d8e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d8e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d8e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ddde782cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp (2133 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sme -disable-O0-optnone -Werror -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-none-linux-gnu" # | # | %class.anon = type { i8 } # | # | $_Z15template_functyIiET_S0_ = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_caller() #0 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | declare i32 @normal_callee() #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @streaming_callee() #0 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret i32 %call # | } # | # | declare i32 @streaming_decl() #2 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_caller() #3 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @streaming_compatible_callee() #3 { # | entry: # | %call = call i32 @streaming_compatible_decl() #16 # | ret i32 %call # | } # | # | declare i32 @streaming_compatible_decl() #4 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_caller() #5 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local i32 @locally_streaming_callee() #5 { # | entry: # | %call = call i32 @locally_streaming_caller() #17 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_caller() #6 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @shared_za_callee() #6 { # | entry: # | %call = call i32 @shared_za_decl() #18 # | ret i32 %call # | } # | # | declare i32 @shared_za_decl() #7 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_caller() #8 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @preserves_za_callee() #8 { # | entry: # | %call = call i32 @preserves_za_decl() #19 # | ret i32 %call # | } # | # | declare i32 @preserves_za_decl() #9 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_caller() #10 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @new_za_callee() #10 { # | entry: # | %call = call i32 @private_za_decl() # | ret i32 %call # | } # | # | declare i32 @private_za_decl() #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_caller() #11 { # | entry: # | %call = call i32 @normal_callee() # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee() #12 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | declare i32 @agnostic_za_decl() #13 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local i32 @agnostic_za_callee_live_za() #6 { # | entry: # | %call = call i32 @agnostic_za_decl() #20 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_streaming_compatible_ptrty(ptr noundef %f, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #16 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_shared_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #18 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_preserved_za(ptr noundef %f, i32 noundef %x, i32 noundef %y) #6 { # | entry: # | %f.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %f, ptr %f.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %f.addr, align 8 # | %1 = load i32, ptr %x.addr, align 4 # | %2 = load i32, ptr %y.addr, align 4 # | call void %0(i32 noundef %1, i32 noundef %2) #19 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @test_indirect_streaming_ptrty(ptr noundef %fptr, i32 noundef %x, i32 noundef %y) #12 { # | entry: # | %fptr.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | %y.addr = alloca i32, align 4 # | store ptr %fptr, ptr %fptr.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | store i32 %y, ptr %y.addr, align 4 # | %0 = load ptr, ptr %fptr.addr, align 8 # | %1 = load ptr, ptr %0, align 8 # | %2 = load ptr, ptr %1, align 8 # | %3 = load i32, ptr %x.addr, align 4 # | %4 = load i32, ptr %y.addr, align 4 # | call void %2(i32 noundef %3, i32 noundef %4) #15 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local void @_Z24test_same_type_streamingv() #12 { # | entry: # | call void @_Z10streaming1v() #15 # | call void @_Z10streaming2v() #15 # | call void @_Z20same_type_streaming1v() #15 # | call void @_Z20same_type_streaming2v() #15 # | ret void # | } # | # | declare void @_Z10streaming1v() #2 # | # | declare void @_Z10streaming2v() #2 # | # | declare void @_Z20same_type_streaming1v() #2 # | # | declare void @_Z20same_type_streaming2v() #2 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local noundef i32 @_Z12overloadedfni(i32 noundef %x) #0 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z12overloadedfnf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | ret float %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z13test_overloadi(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @_Z12overloadedfni(i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef float @_Z13test_overloadf(float noundef %x) #12 { # | entry: # | %x.addr = alloca float, align 4 # | store float %x, ptr %x.addr, align 4 # | %0 = load float, ptr %x.addr, align 4 # | %call = call noundef float @_Z12overloadedfnf(float noundef %0) # | ret float %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z11test_lambdai(i32 noundef %x) #12 { # | entry: # | %x.addr = alloca i32, align 4 # | %F = alloca %class.anon, align 1 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %call = call noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %F, i32 noundef %0) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define internal noundef i32 @"_ZZ11test_lambdaiENK3$_0clEi"(ptr noundef nonnull align 1 dereferenceable(1) %this, i32 noundef %x) #0 { # | entry: # | %this.addr = alloca ptr, align 8 # | %x.addr = alloca i32, align 4 # | store ptr %this, ptr %this.addr, align 8 # | store i32 %x, ptr %x.addr, align 4 # | %this1 = load ptr, ptr %this.addr, align 8 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z27test_template_instantiationv() #12 { # | entry: # | %call = call noundef i32 @_Z15template_functyIiET_S0_(i32 noundef 12) #15 # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define linkonce_odr noundef i32 @_Z15template_functyIiET_S0_(i32 noundef %x) #0 comdat { # | entry: # | %x.addr = alloca i32, align 4 # | store i32 %x, ptr %x.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z25locally_streaming_inheritv() #5 { # | entry: # | %call = call i32 @streaming_decl() #15 # | ret void # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define dso_local noundef i32 @_Z4callv() #14 { # | entry: # | ret i32 0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local noundef i32 @_Z22test_variadic_templatev() #6 { # | entry: # | %f.addr.i16 = alloca ptr, align 8 # | %f.addr.i12 = alloca ptr, align 8 # | %other.addr.i13 = alloca ptr, align 8 # | %f.addr.i7 = alloca ptr, align 8 # | %other.addr.i8 = alloca ptr, align 8 # | %other.addr2.i9 = alloca ptr, align 8 # | %f.addr.i1 = alloca ptr, align 8 # | %other.addr.i2 = alloca ptr, align 8 # | %other.addr2.i3 = alloca ptr, align 8 # | %other.addr4.i4 = alloca ptr, align 8 # | %f.addr.i = alloca ptr, align 8 # | %other.addr.i = alloca ptr, align 8 # | %other.addr2.i = alloca ptr, align 8 # | %other.addr4.i = alloca ptr, align 8 # | %other.addr6.i = alloca ptr, align 8 # | store ptr @normal_callee, ptr %f.addr.i, align 8 # | store ptr @streaming_decl, ptr %other.addr.i, align 8 # | store ptr @streaming_compatible_decl # | ... # `---data was truncated (10240/15241) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed0b44615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed0b4430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed0b44689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64c3b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64c3b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64c3b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64c3b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed0b3dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed0b3dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed0b3c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed0b0700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed0b06fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64c3b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64c3b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64c3b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed0b06fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=inline # | #0 0x0000561119e5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561119e530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561119e5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7ffd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7ffd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7ffd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7ffd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561119debe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561119debc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561119dd0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561119a800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561119a7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb7ffd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7ffd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7ffd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561119a7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c (2134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/112825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c6295a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c629570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c6295a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bae41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bae4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bae41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bae403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c628efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c628efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c628d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c625840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c62583dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bae404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bae4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bae4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c62583cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c (2135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b67ed0d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b67ed0a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b67ed0d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3502c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3502ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3502c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3502c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b67eca2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b67eca2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b67ec87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b67e9370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b67e936dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3502c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3502c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3502c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b67e936cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c (2136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd45cf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd45cf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd45cf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff27cd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff27cd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff27cd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff27cced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd45c8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd45c8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd45c73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd459230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd45922dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff27cceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff27ccef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff27ccef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd45922cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c (2137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/22375) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9cbe2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9cbe200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9cbe2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae0e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae0e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae0e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae0e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9cbdb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9cbdb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9cbd9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9cba4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9cba4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae0e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae0e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae0e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9cba4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c (2138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 7, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.ris # | ... # `---data was truncated (10240/18562) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b22e6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b22e5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b22e6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff435f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff435f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff435f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff435f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b22df6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b22df6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b22ddbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b22a8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b22a8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff435f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff435f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff435f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b22a8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c (2139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, # | ... # `---data was truncated (10240/15512) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f478fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f478f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f478fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cde81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cde8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cde81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cde803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f4788fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f4788fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f47874b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f475240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f47523dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0cde804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cde8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cde8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f47523cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c (2140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559590eda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559590ed70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559590eda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba02933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba0298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba02933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba0291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559590e6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559590e6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559590e54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559590b040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559590b03dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fba0291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba0291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba0291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559590b03cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c (2141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.v # | ... # `---data was truncated (10240/23413) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609e29b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609e29b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609e29b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c44c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c44ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c44c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c44c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609e294be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005609e294bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005609e2930b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609e25e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609e25dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c44c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c44c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c44c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609e25dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c (2142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m1x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_i8m2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf8x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv1i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf4x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8ff_v_u8mf2x4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceabeaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ceabea70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ceabeaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e7df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e7df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e7df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e7df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceabe3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ceabe3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ceabe24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ceabad40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ceabad3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7e7df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e7df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e7df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceabad3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c (2143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c (2144 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fcda20d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fcda20a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fcda20d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9e4c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9e4ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9e4c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9e4c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fcda1a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fcda1a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fcda187b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fcd9e370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fcd9e36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc9e4c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9e4c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9e4c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fcd9e36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c (2145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasub.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasub_vv_i8 # | ... # `---data was truncated (10240/99577) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005592477b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005592477b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005592477b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73f1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73f18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73f1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73f1831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055924774ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055924774ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559247733b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592473e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005592473e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f73f1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73f18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73f18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592473e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c (2146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/18353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5b54ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5b54c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b5b54ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fb2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fb298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fb2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fb291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5b545fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b5b545fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5b5444b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5b50f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b5b50f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4fb291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fb291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fb291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5b50f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c (2147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b9713815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b971350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b9713889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc929733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc92978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc929733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc92971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b970cde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b970cdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b970b2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b96d620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b96d61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc92971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc92971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc92971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b96d61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c (2148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055941005515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594100520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055941005589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7310d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7310d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7310d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7310ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055940ffeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055940ffeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055940ffcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055940fc7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055940fc7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7310ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7310cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7310cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055940fc7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c (2149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/87892) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c11bd615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555c11bd30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555c11bd689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f13305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f1335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f13305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f132ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c11b6be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555c11b6bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555c11b50b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555c118000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555c117ffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f132eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f132ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f132ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c117ffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c (2150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c (2151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056389248115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056389247e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056389248189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53d9b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53d9b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53d9b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53d9aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563892416e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563892416c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638923fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638920ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638920aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f53d9aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53d9aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53d9aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638920aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c (2152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055644521615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564452130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055644521689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4eeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4eeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4eeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4eeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564451abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005564451abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556445190b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556444e400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556444e3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc4eeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4eeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4eeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556444e3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c (2153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c (2154 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_f16m4_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c (2155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559837d5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559837d570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559837d5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3313e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3313e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3313e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3313e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559837cefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559837cefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559837cd4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598379840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559837983dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3313e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3313e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3313e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559837983cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/arm-mve-intrinsics/dup.c (2156 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/dup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_n_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %0, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | ret <8 x half> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_n_f32(float noundef %a) #0 { # | entry: # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %0, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | ret <4 x float> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_s8(i8 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_s16(i16 noundef signext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_n_u8(i8 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | store i8 %a, ptr %a.addr, align 1 # | %0 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %0, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | ret <16 x i8> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_n_u16(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %0, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | ret <8 x i16> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %0, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | ret <4 x i32> %.splat # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vdupq_m_n_f16(<8 x half> noundef %inactive, half noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca half, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store half %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load half, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %3, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %4 = load <8 x half>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %.splat, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vdupq_m_n_f32(<4 x float> noundef %inactive, float noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store float %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load float, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %3, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %4 = load <4 x float>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %.splat, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_s8(<16 x i8> noundef %inactive, i8 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef signext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %.splat, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdupq_m_n_s32(<4 x i32> noundef %inactive, i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %3, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %.splat, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdupq_m_n_u8(<16 x i8> noundef %inactive, i8 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i8, ptr %a.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %3, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = select <16 x i1> %2, <16 x i8> %.splat, <16 x i8> %4 # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdupq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i16, ptr %a.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %3, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = select <8 x i1> %2, # | ... # `---data was truncated (10240/17297) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055822e47f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055822e47c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055822e47f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055822e414e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055822e414c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055822e3f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055822e0a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055822e0a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bc6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055822e0a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/dup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c (2157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/13625) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055785d2ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055785d2ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055785d2ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d6d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d6d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d6d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d6d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055785d284e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055785d284c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055785d269b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055785cf190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055785cf18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d6d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d6d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d6d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055785cf18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c (2158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local t # | ... # `---data was truncated (10240/36031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627f706f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627f706c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627f706f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f70c3249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f70c32a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f70c3249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f70c3231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627f7004e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005627f7004c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005627f6fe9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627f6c990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627f6c98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f70c3232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f70c32330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f70c32330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627f6c98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load # | ... # `---data was truncated (10240/26710) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cec418515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cec41820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cec418589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe555a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe555aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe555a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe555a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cec411ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cec411ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cec40ffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cec3daf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cec3daedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe555a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe555a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe555a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cec3daecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c (2160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559317eae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559317eab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559317eae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faea5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faea578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faea5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faea571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559317e43e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559317e43c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559317e28b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559317ad80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559317ad7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faea571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faea571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faea571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559317ad7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vld24.c (2161 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vld24.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | %struct.uint8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint32x4x2_t = type { [2 x <4 x i32>] } # | %struct.int8x16x4_t = type { [4 x <16 x i8>] } # | %struct.uint16x8x2_t = type { [2 x <8 x i16>] } # | %struct.int32x4x2_t = type { [2 x <4 x i32>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.float16x8x2_t @test_vld2q_f16(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr %0) # | %2 = extractvalue { <8 x half>, <8 x half> } %1, 0 # | %3 = insertvalue %struct.float16x8x2_t poison, <8 x half> %2, 0, 0 # | %4 = extractvalue { <8 x half>, <8 x half> } %1, 1 # | %5 = insertvalue %struct.float16x8x2_t %3, <8 x half> %4, 0, 1 # | ret %struct.float16x8x2_t %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc %struct.uint8x16x4_t @test_vld4q_u8(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr %0) # | %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0 # | %3 = insertvalue %struct.uint8x16x4_t poison, <16 x i8> %2, 0, 0 # | %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1 # | %5 = insertvalue %struct.uint8x16x4_t %3, <16 x i8> %4, 0, 1 # | %6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2 # | %7 = insertvalue %struct.uint8x16x4_t %5, <16 x i8> %6, 0, 2 # | %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3 # | %9 = insertvalue %struct.uint8x16x4_t %7, <16 x i8> %8, 0, 3 # | ret %struct.uint8x16x4_t %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_u32(ptr noundef %addr, %struct.uint32x4x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.uint32x4x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.uint32x4x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.uint32x4x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.uint32x4x2_t %value.coerce, 0 # | store [2 x <4 x i32>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.uint32x4x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.uint32x4x2_t %3, 0, 0 # | %5 = extractvalue %struct.uint32x4x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v4i32(ptr %2, <4 x i32> %4, <4 x i32> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i32(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i32, i1 immarg) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v4i32(ptr, <4 x i32>, <4 x i32>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst4q_s8(ptr noundef %addr, %struct.int8x16x4_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.int8x16x4_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.int8x16x4_t, align 8 # | %0 = getelementptr inbounds nuw %struct.int8x16x4_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.int8x16x4_t %value.coerce, 0 # | store [4 x <16 x i8>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 64, i1 false) # | %3 = load %struct.int8x16x4_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.int8x16x4_t %3, 0, 0 # | %5 = extractvalue %struct.int8x16x4_t %3, 0, 1 # | %6 = extractvalue %struct.int8x16x4_t %3, 0, 2 # | %7 = extractvalue %struct.int8x16x4_t %3, 0, 3 # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 0) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 1) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 2) # | call void @llvm.arm.mve.vst4q.p0.v16i8(ptr %2, <16 x i8> %4, <16 x i8> %5, <16 x i8> %6, <16 x i8> %7, i32 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst4q.p0.v16i8(ptr, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @test_vst2q_f16(ptr noundef %addr, %struct.float16x8x2_t %value.coerce) #0 { # | entry: # | %value = alloca %struct.float16x8x2_t, align 8 # | %addr.addr = alloca ptr, align 4 # | %tmp = alloca %struct.float16x8x2_t, align 8 # | %0 = getelementptr inbounds nuw %struct.float16x8x2_t, ptr %value, i32 0, i32 0 # | %1 = extractvalue %struct.float16x8x2_t %value.coerce, 0 # | store [2 x <8 x half>] %1, ptr %0, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %2 = load ptr, ptr %addr.addr, align 4 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %tmp, ptr align 8 %value, i32 32, i1 false) # | %3 = load %struct.float16x8x2_t, ptr %tmp, align 8 # | %4 = extractvalue %struct.float16x8x2_t %3, 0, 0 # | %5 = extractvalue %struct.float16x8x2_t %3, 0, 1 # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 0) # | call void @llvm.arm.mve.vst2q.p0.v8f16(ptr %2, <8 x half> %4, <8 x half> %5, i32 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.arm.mve.vst2q.p0.v8f16(ptr, <8 x half>, <8 x half>, i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc void @load_into_variable(ptr noundef %addr, ptr noundef %values) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %values.addr = alloca ptr, align 4 # | %v = alloca %struct.uint16x8x2_t, align 8 # | %tmp = alloca %struct.uint16x8x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | store ptr %values, ptr %values.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr %0) # | %2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0 # | %3 = insertvalue %struct.uint16x8x2_t poison, <8 x i16> %2, 0, 0 # | %4 = extractvalue { <8 x i16>, <8 x i16> } %1, 1 # | %5 = insertvalue %struct.uint16x8x2_t %3, <8 x i16> %4, 0, 1 # | store %struct.uint16x8x2_t %5, ptr %tmp, align 8 # | call void @llvm.memcpy.p0.p0.i32(ptr align 8 %v, ptr align 8 %tmp, i32 32, i1 false) # | %val = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <8 x i16>], ptr %val, i32 0, i32 0 # | %6 = load <8 x i16>, ptr %arrayidx, align 8 # | %7 = load ptr, ptr %values.addr, align 4 # | %arrayidx1 = getelementptr inbounds <8 x i16>, ptr %7, i32 0 # | store <8 x i16> %6, ptr %arrayidx1, align 8 # | %val2 = getelementptr inbounds nuw %struct.uint16x8x2_t, ptr %v, i32 0, i32 0 # | %arrayidx3 = getelementptr inbounds [2 x <8 x i16>], ptr %val2, i32 0, i32 1 # | %8 = load <8 x i16>, ptr %arrayidx3, align 8 # | %9 = load ptr, ptr %values.addr, align 4 # | %arrayidx4 = getelementptr inbounds <8 x i16>, ptr %9, i32 1 # | store <8 x i16> %8, ptr %arrayidx4, align 8 # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0(ptr) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @extract_one_vector(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %ref.tmp = alloca %struct.int32x4x2_t, align 8 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr %0) # | %2 = extractvalue { <4 x i32>, <4 x i32> } %1, 0 # | %3 = insertvalue %struct.int32x4x2_t poison, <4 x i32> %2, 0, 0 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %1, 1 # | %5 = insertvalue %struct.int32x4x2_t %3, <4 x i32> %4, 0, 1 # | store %struct.int32x4x2_t %5, ptr %ref.tmp, align 8 # | %val = getelementptr inbounds nuw %struct.int32x4x2_t, ptr %ref.tmp, i32 0, i32 0 # | %arrayidx = getelementptr inbounds [2 x <4 x i32>], ptr %val, i32 0, i32 0 # | %6 = load <4 x i32>, ptr %arrayidx, align 8 # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vld2q.v4i32.p0(ptr) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x000055eaa263e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eaa263b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eaa263e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0c3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eaa25d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eaa25d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eaa25b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eaa22680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eaa2267dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eaa2267cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vld24.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c (2162 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, a # | ... # `---data was truncated (10240/424843) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f6178615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f617830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f6178689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f313201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31320725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f313201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3132003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f6171be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f6171bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f61700b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f613b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f613afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3132004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31320050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31320050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f613afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c (2163 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558021f6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558021f690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558021f6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3817849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38178a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3817849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3817831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558021f01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558021f01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558021ee6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558021b960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558021b95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3817832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38178330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38178330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558021b95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c (2164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056328fced15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056328fcea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056328fced89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd87e249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd87e2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd87e249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd87e231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056328fc82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056328fc82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056328fc67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056328f9170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056328f916dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd87e232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd87e2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd87e2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056328f916cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c (2165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4b5fb915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4b5fb60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4b5fb989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4213e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4213ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4213e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4213e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4b5f4ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f4b5f4ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f4b5f33b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4b5be30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4b5be2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4213e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4213e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4213e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4b5be2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c (2166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +v -disable-O0-optnone -emit-llvm -Qn /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i32 @test_vlenb() #0 { # | entry: # | %0 = call i32 @llvm.read_register.i32(metadata !4) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.read_register.i32(metadata) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"vlenb"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -O2 # | #0 0x0000558edb16215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558edb15f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558edb16289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca63b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca63b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca63b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca63b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558edb0f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558edb0f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558edb0dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558edad8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558edad8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca63b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca63b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca63b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558edad8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=RV32 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vsubq.c (2167 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = sub <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = fsub <8 x half> %0, %1 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = sub <4 x i32> %0, %.splat # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsubq_n_f16(<8 x half> noundef %a, half noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca half, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store half %b, ptr %b.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load half, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x half> poison, half %1, i64 0 # | %.splat = shufflevector <8 x half> %.splatinsert, <8 x half> poison, <8 x i32> zeroinitializer # | %2 = fsub <8 x half> %0, %.splat # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsubq_m_n_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, float noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca float, align 4 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load float, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x float> poison, float %1, i64 0 # | %.splat = shufflevector <4 x float> %.splatinsert, <4 x float> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %.splat, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @t # | ... # `---data was truncated (10240/11617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005566df63215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566df62f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566df63289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9e8849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9e88a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9e8849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9e8831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566df5c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566df5c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566df5acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566df25c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566df25bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9e8832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9e88330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9e88330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566df25bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c (2168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055585608c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558560890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055585608c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c9da1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c9da725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c9da1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c9da03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555856021e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555856021c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555856006b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555855cb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555855cb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c9da04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c9da050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c9da050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555855cb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c (2169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, # | ... # `---data was truncated (10240/60217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2b35a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d2b35a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d2b35a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48e5d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48e5d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48e5d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48e5d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2b353ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d2b353ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d2b3523b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d2b31d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d2b31d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48e5d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48e5d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48e5d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2b31d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c (2170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv1i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv2i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv4i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssra.nxv8i8.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/226585) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc39f6815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc39f650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc39f6889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6879133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f687918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6879133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f687911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc39efde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc39efdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc39ee2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc39b920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc39b91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f687911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f687911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f687911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc39b91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c (2171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8( %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load bfloat, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv2bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_m( %mask, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv4bf16.bf16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c (2172 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e65ec3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e65ec2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e65ec3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0a2733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0a278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0a2733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0a271b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e65ebc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e65ebc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e65ebacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e65e85c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e65e85bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0a271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0a271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0a271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e65e85bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c (2173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056276a50c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056276a5090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056276a50c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98a9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98a96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98a9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98a9631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056276a4a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056276a4a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056276a486b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056276a1360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056276a135dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98a9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98a96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98a96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056276a135cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c (2174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3115f215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3115ef0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3115f289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f171af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f171af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f171af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f171af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c311587e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c311587c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c31156cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c31121c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c31121bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f171af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f171af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f171af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c31121bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c (2175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = loa # | ... # `---data was truncated (10240/135111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c136cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c136cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c136cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4e4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4e495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4e4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4e48ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c13664e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c13664c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c13649b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c132f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c132f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff4e48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4e48ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4e48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c132f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c (2176 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c67df9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c67df990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c67df9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6578a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6578aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6578a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6578a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c67df31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c67df31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c67df16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c67dbc60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c67dbc5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6578a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6578a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6578a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c67dbc5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c (2177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cbf086a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cbf08670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cbf086a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e0801bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e080725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e0801ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e08003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cbf07ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cbf07ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cbf07e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cbf04940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cbf0493dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e08004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e080050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e080050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cbf0493cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c (2178 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c (2179 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_v # | ... # `---data was truncated (10240/228865) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ca3be315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563ca3be00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563ca3be389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4b0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4b0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4b0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4b0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ca3b78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563ca3b78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563ca3b5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563ca380d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563ca380cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4b0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4b0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4b0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ca380ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c (2180 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/54488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d82ff515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d82ff20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d82ff589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadaca49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadacaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadaca49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadaca31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d82f8ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d82f8ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d82f6fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d82c1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d82c1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadaca32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadaca330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadaca330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d82c1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c (2181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e87b33315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e87b3300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e87b33389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9978849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99788a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9978849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9978831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e87b2c8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e87b2c8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e87b2adb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e87af5d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e87af5cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9978832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99788330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99788330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e87af5ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c (2182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd8d46215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd8d45f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd8d46289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6cc4733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6cc478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6cc4733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6cc471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd8d3f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd8d3f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd8d3dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd8d08c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd8d08bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6cc471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6cc471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6cc471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd8d08bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c (2183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf8_b64( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf4_b32( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vvm_i8mf2_b16( %op1, %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %borrowin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %borrowin, ptr %borrowin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %borrowin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %borrowin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , # | ... # `---data was truncated (10240/170497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3ecc8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3ecc880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a3ecc8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7184d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7184d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7184d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7184d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ecc20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a3ecc20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a3ecc05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3ec8b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3ec8b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7184d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7184d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7184d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ec8b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c (2184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055968aa4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055968aa440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055968aa4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa3d0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa3d0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa3d0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa3d0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055968a9dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055968a9dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055968a9c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055968a6710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055968a670dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa3d0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa3d0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa3d0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055968a670cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c (2185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64( poison, %0, i32 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32.i64(, , i32, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvt_x_x_v_i64m2( %src, i64 # | ... # `---data was truncated (10240/29175) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7a9c8615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7a9c830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7a9c8689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f123fc1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f123fc725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f123fc1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f123fc03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7a9c1be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7a9c1bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7a9c00b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7a98b00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7a98afdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f123fc04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f123fc050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f123fc050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7a98afcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c (2186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i16 # | ... # `---data was truncated (10240/84971) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f64b2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f64b230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f64b2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb2e649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb2e6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb2e649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb2e631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f64abbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f64abbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f64aa0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f647500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f6474fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb2e632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb2e6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb2e6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f6474fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c (2187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056494ea6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056494ea640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056494ea6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb46d133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb46d18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb46d133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb46d11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056494e9fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056494e9fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056494e9e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056494e6910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056494e690dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb46d11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb46d11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb46d11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056494e690cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c (2188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.t # | ... # `---data was truncated (10240/12089) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564dee33f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564dee33c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564dee33f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6519049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65190a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6519049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6519031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564dee2d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564dee2d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564dee2b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564dedf690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564dedf68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6519032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65190330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65190330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564dedf68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c (2189 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesbfhcvt -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_fcvt_s_bf16(bfloat noundef %bf) #0 { # | entry: # | %bf.addr.i = alloca bfloat, align 2 # | %bf.addr = alloca bfloat, align 2 # | store bfloat %bf, ptr %bf.addr, align 2 # | %0 = load bfloat, ptr %bf.addr, align 2 # | store bfloat %0, ptr %bf.addr.i, align 2 # | %1 = load bfloat, ptr %bf.addr.i, align 2 # | %2 = fpext bfloat %1 to float # | ret float %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_fcvt_bf16_s(float noundef %sf) #0 { # | entry: # | %sf.addr.i = alloca float, align 4 # | %sf.addr = alloca float, align 4 # | store float %sf, ptr %sf.addr, align 4 # | %0 = load float, ptr %sf.addr, align 4 # | store float %0, ptr %sf.addr.i, align 4 # | %1 = load float, ptr %sf.addr.i, align 4 # | %2 = fptrunc float %1 to bfloat # | ret bfloat %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+f,+i,+xandesbfhcvt,+zicsr" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff0227115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff0226e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff0227189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f68da733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f68da78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f68da733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f68da71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff02206e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff02206c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff021ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff01e9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff01e9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f68da71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f68da71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f68da71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff01e9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c (2190 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %3 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %4 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %5 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %6, ptr %__ret.i, align 8 # | %7 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %1, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %3 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %4 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %5 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %6, ptr %__ret.i, align 8 # | %7 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_lane_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <4 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <4 x bfloat>, align 8 # | %__ret_810 = alloca <2 x float>, align 8 # | %__s0_810 = alloca <2 x float>, align 8 # | %__s1_810 = alloca <4 x bfloat>, align 8 # | %__s2_810 = alloca <4 x bfloat>, align 8 # | %ref.tmp = alloca <2 x float>, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__s0 = alloca <2 x float>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x float>, align 8 # | %tmp2 = alloca <2 x float>, align 8 # | store <2 x float> %r, ptr %r.addr, align 8 # | store <4 x bfloat> %a, ptr %a.addr, align 8 # | store <4 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %r.addr, align 8 # | store <2 x float> %0, ptr %__s0_810, align 8 # | %1 = load <4 x bfloat>, ptr %a.addr, align 8 # | store <4 x bfloat> %1, ptr %__s1_810, align 8 # | %2 = load <4 x bfloat>, ptr %b.addr, align 8 # | store <4 x bfloat> %2, ptr %__s2_810, align 8 # | %3 = load <2 x float>, ptr %__s0_810, align 8 # | %4 = load <4 x bfloat>, ptr %__s1_810, align 8 # | %5 = load <2 x float>, ptr %__s2_810, align 8 # | store <2 x float> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x float> # | %lane = shufflevector <2 x float> %7, <2 x float> %7, <2 x i32> zeroinitializer # | store <2 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x float>, ptr %ref.tmp1, align 8 # | store <2 x float> %8, ptr %__ret, align 8 # | %9 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %9, ptr %tmp, align 8 # | %10 = load <2 x float>, ptr %tmp, align 8 # | store <2 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <4 x bfloat>, ptr %ref.tmp, align 8 # | store <2 x float> %3, ptr %__p0.addr.i, align 8 # | store <4 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <4 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <8 x i8> %12 to <2 x float> # | %vbfdot1.i = bitcast <8 x i8> %13 to <4 x bfloat> # | %vbfdot2.i = bitcast <8 x i8> %14 to <4 x bfloat> # | %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %vbfdot.i, <4 x bfloat> %vbfdot1.i, <4 x bfloat> %vbfdot2.i) # | store <2 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %15, ptr %__ret.i, align 8 # | %16 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %16, ptr %__ret_810, align 8 # | %17 = load <2 x float>, ptr %__ret_810, align 8 # | store <2 x float> %17, ptr %tmp2, align 8 # | %18 = load <2 x float>, ptr %tmp2, align 8 # | ret <2 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vbfdotq_laneq_f32(<4 x float> noundef %r, <8 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <8 x bfloat>, align 8 # | %__p2.addr.i = alloca <8 x bfloat>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <8 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_812 = alloca <4 x float>, align 8 # | %__s0_812 = alloca <4 x float>, align 8 # | %__s1_812 = alloca <8 x bfloat>, align 8 # | %__s2_812 = alloca <8 x bfloat>, align 8 # | %ref.tmp = alloca <4 x float>, align 8 # | %__ret = alloca <4 x float>, align 8 # | %__s0 = alloca <4 x float>, align 8 # | %ref.tmp1 = alloca <16 x i8>, align 8 # | %tmp = alloca <4 x float>, align 8 # | %tmp2 = alloca <4 x float>, align 8 # | store <4 x float> %r, ptr %r.addr, align 8 # | store <8 x bfloat> %a, ptr %a.addr, align 8 # | store <8 x bfloat> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %r.addr, align 8 # | store <4 x float> %0, ptr %__s0_812, align 8 # | %1 = load <8 x bfloat>, ptr %a.addr, align 8 # | store <8 x bfloat> %1, ptr %__s1_812, align 8 # | %2 = load <8 x bfloat>, ptr %b.addr, align 8 # | store <8 x bfloat> %2, ptr %__s2_812, align 8 # | %3 = load <4 x float>, ptr %__s0_812, align 8 # | %4 = load <8 x bfloat>, ptr %__s1_812, align 8 # | %5 = load <4 x float>, ptr %__s2_812, align 8 # | store <4 x float> %5, ptr %__s0, align 8 # | %6 = load <16 x i8>, ptr %__s0, align 8 # | %7 = bitcast <16 x i8> %6 to <4 x float> # | %lane = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> # | store <4 x float> %lane, ptr %ref.tmp1, align 8 # | %8 = load <4 x float>, ptr %ref.tmp1, align 8 # | store <4 x float> %8, ptr %__ret, align 8 # | %9 = load <4 x float>, ptr %__ret, align 8 # | store <4 x float> %9, ptr %tmp, align 8 # | %10 = load <4 x float>, ptr %tmp, align 8 # | store <4 x float> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x bfloat>, ptr %ref.tmp, align 8 # | store <4 x float> %3, ptr %__p0.addr.i, align 8 # | store <8 x bfloat> %4, ptr %__p1.addr.i, align 8 # | store <8 x bfloat> %11, ptr %__p2.addr.i, align 8 # | %12 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vbfdot.i = bitcast <16 x i8> %12 to <4 x float> # | %vbfdot1.i = bitcast <16 x i8> %13 to <8 x bfloat> # | %vbfdot2.i = bitcast <16 x i8> %14 to <8 x bfloat> # | %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %vbfdot.i, <8 x bfloat> %vbfdot1.i, <8 x bfloat> %vbfdot2.i) # | store <4 x float> %vbfdot3.i, ptr %ref.tmp.i, align 8 # | %15 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %15, ptr %__ret.i, align 8 # | %16 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %16, ptr %__ret_812, align 8 # | %17 = load <4 x float>, ptr %__ret_812, align 8 # | store <4 x float> %17, ptr %tmp2, align 8 # | %18 = load <4 x float>, ptr %tmp2, align 8 # | ret <4 x float> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vbfdot_laneq_f32(<2 x float> noundef %r, <4 x bfloat> noundef %a, <8 x bfloat> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <4 x bfloat>, align 8 # | %__p2.addr.i = alloca <4 x bfloat>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x float>, align 8 # | %a.addr = alloca <4 x bfloat>, align 8 # | %b.addr = alloca <8 x bfloat>, align 8 # | %__ret_814 = alloca <2 x float>, al # | ... # `---data was truncated (10240/54174) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000056041894e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056041894b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056041894e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd378333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd37838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd378333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd37831b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604188e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604188e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604188c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604185780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560418577dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd37831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd37831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd37831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560418577cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c (2191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b2bde1915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2bde160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b2bde1989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6877d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6877d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6877d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6877d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b2bddaee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b2bddaec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2bdd93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b2bda430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b2bda42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6877d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6877d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6877d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b2bda42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c (2192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564196a3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564196a320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564196a3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9787c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9787ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9787c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9787c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641969cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005641969cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005641969afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056419665f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056419665edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9787c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9787c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9787c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056419665ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c (2193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c558c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c558c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c558c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7162f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7162f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7162f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7162eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c5585ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c5585ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c5583fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c554ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c554eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7162eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7162eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7162eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c554eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c (2194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr # | ... # `---data was truncated (10240/29202) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055982564715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005598256440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055982564789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa37d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa37d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa37d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa37d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598255dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598255dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598255c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598252710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559825270dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa37d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa37d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa37d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559825270cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c (2195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_f32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_i32m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i32.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse32_v_u32m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i32.p0.i64( %1, ptr %0, # | ... # `---data was truncated (10240/28346) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565467b4615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565467b430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565467b4689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b57133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b5718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b57133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b5711b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565467adbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565467adbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565467ac0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654677700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056546776fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b5711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b5711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b5711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056546776fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c (2196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055864925615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005586492530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055864925689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f804db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f804db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f804db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f804db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005586491ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005586491ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005586491d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558648e800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558648e7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f804db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f804db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f804db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558648e7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c (2197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_i16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf4x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_u16m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df7753b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df775380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df7753b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ee2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ee298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ee2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ee291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df774d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df774d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df774b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df771650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df77164dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ee291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ee291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ee291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df77164cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c (2198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/76627) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c1dfad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c1dfaa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c1dfad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85c021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85c02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85c021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85c0203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c1df42e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c1df42c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c1df27b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c1dbd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c1dbd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85c0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85c02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85c02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c1dbd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c (2199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a544df215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a544def0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a544df289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7be2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7be298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7be2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7be291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a544d87e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a544d87c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a544d6cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a544a1c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a544a1bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7be291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7be291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7be291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a544a1bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c (2200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c (2201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) # # | ... # `---data was truncated (10240/26584) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aaa35d115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aaa35ce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aaa35d189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1897e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1897ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1897e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1897e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aaa3566e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aaa3566c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aaa354bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aaa31fb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aaa31fadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1897e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1897e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1897e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aaa31facc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c (2202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c (2203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056463e43415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056463e4310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056463e43489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffacae1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffacae725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffacae1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffacae03507 abort ./stdlib/abort.c:85:3 # | #7 0x000056463e3c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056463e3c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056463e3aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056463e05e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056463e05ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffacae04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffacae050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffacae050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056463e05dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c (2204 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vdivu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdivu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdivu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056027e58215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056027e57f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056027e58289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e78333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e7838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e78333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e7831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056027e517e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056027e517c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056027e4fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056027e1ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056027e1abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5e7831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e7831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e7831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056027e1abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c (2205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d07f1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d07f140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d07f1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4146e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4146e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4146e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4146e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d07eace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d07eacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d07e91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d07b410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d07b40dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4146e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4146e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4146e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d07b40cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c (2206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u64m4x2_u64m4(target("riscv.vector.tuple", , 2) %src) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 8 # | %1 = call @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) %0, i32 1) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv4i64.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_u64m4_u64m4x2(target("riscv.vector.tuple", , 2) %dest, %val) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %val.addr = alloca , align 8 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 8 # | store %val, ptr %val.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 8 # | %1 = load , ptr %val.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2) %0, %1, i32 1) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb502b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb502b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb502b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc25021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2502725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc25021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc250203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb5024ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb5024ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb50233b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb4fee30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb4fee2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc250204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2502050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2502050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb4fee2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c (2207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsbf.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b62ad5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b62ad4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b62ad5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99d8505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99d855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99d8505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99d84ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b62ace6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b62ace6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b62accbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b62a97b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b62a97add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99d84eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99d84ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99d84ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b62a97acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c (2208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560bd770715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560bd77040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560bd770789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2566049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25660a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2566049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2566031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560bd769ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560bd769cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560bd7681b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560bd73310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560bd7330dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2566032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25660330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25660330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560bd7330cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c (2209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv1i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vec # | ... # `---data was truncated (10240/27595) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4e8e6f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4e8e6c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4e8e6f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3766f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3766f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3766f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3766f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4e8e04e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a4e8e04c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a4e8de9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4e8a990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4e8a98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3766f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3766f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3766f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4e8a98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c (2210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nx # | ... # `---data was truncated (10240/83629) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ae542a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ae54270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ae542a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5dac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5daca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5dac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5dac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ae53bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ae53bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ae53a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ae50540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ae5053dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5dac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5dac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5dac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ae5053cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c (2211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nx # | ... # `---data was truncated (10240/25567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644fcfa615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644fcfa30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644fcfa689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f002e505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f002e55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f002e505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f002e4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644fcf3be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644fcf3bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644fcf20b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644fcbd00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644fcbcfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f002e4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f002e4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f002e4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644fcbcfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c (2212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/108856) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055884251615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588425130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055884251689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b4ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b4ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b4ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b4ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588424abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588424abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558842490b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588421400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055884213fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b4ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b4ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b4ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055884213fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c (2213 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9781c715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9781c40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9781c789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd512505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd51255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd512505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5124ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b97815ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b97815cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b978141b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b977df10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b977df0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd5124eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5124ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5124ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b977df0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c (2214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 4) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32_v_f32m2x4_m( %mask, ptr noun # | ... # `---data was truncated (10240/17567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558570e8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558570e860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558570e8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadf1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadf12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadf1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadf1231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558570e1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558570e1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558570e03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558570ab30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558570ab2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadf1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadf12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadf12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558570ab2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c (2215 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf4_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16mf2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m1_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vx_u16m2_tu( %vd, %vs2, i8 noundef zeroext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabdau.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabdau_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c (2216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fd2c2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fd2c210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fd2c2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7eba933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7eba98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7eba933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7eba91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fd2bb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fd2bb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fd2b9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fd284e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fd284ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7eba91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7eba91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7eba91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fd284dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c (2217 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m2_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m4_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f16m8_f16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m2_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv4f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv4f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv2f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m4_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv8f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv8f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv4f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f32m8_f32m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 4 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = call @llvm.vector.extract.nxv8f32.nxv16f32( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f32.nxv16f32(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_f64m2_f64m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 8 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = call @llvm.vector.extract.nxv1f64.nxv2f64( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f64.nxv2f64(, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/246614) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056250560815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625056050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056250560889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd5b6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd5b618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd5b6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd5b611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056250559de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056250559dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562505582b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625052320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562505231dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd5b611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd5b611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd5b611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562505231cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c (2218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055acb395915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055acb39560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055acb395989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3ed333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3ed38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3ed333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3ed31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055acb38eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055acb38eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055acb38d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055acb35830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055acb3582dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb3ed31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3ed31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3ed31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055acb3582cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c (2219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8mf2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m1_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m2_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u8m8_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsumu_vs_u16mf4_u32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsumu.nxv2i # | ... # `---data was truncated (10240/51303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c42ad4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c42ad3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c42ad4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbc5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbc52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbc5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbc5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c42acd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c42acd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c42acbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c42a96c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c42a96bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbbc5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbc52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbc52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c42a96bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c (2220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv2bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_m( %mask, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64( poison, %1, bfloat %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv4bf16.bf16.i64(, , bfloat, , i # | ... # `---data was truncated (10240/14788) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d2595715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d259540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d2595789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7946449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7946449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7946431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d258ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d258ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d258d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d255810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d25580dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7946432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79464330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d25580cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c (2221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmaxu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmaxu.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmaxu_vv_u8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr # | ... # `---data was truncated (10240/97905) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056552ca6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056552ca610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056552ca6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f14b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f14b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f14b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f14aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056552c9f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056552c9f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056552c9deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056552c68e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056552c68ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f14aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f14aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f14aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056552c68dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c (2222 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/69677) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe0f41615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fe0f4130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fe0f41689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8dfaa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8dfaaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8dfaa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8dfaa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe0f3abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fe0f3abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fe0f390b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fe0f0400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fe0f03fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8dfaa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8dfaa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8dfaa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe0f03fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c (2223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesem.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesem_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesem.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fa38e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559fa38e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559fa38e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff9b8e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9b8e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff9b8e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff9b8e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fa3879e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559fa3879c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559fa385eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559fa350e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559fa350ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff9b8e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9b8e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9b8e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fa350dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c (2224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 5) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a521c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557a521c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557a521c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2902d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2902d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2902d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2902d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a52158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557a52158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557a5213db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557a51ded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557a51decdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2902d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2902d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2902d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a51deccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c (2225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/16382) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c48308f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c48308c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c48308f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b68849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b688a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b68849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b68831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c483024e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c483024c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c483009b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c482cb90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c482cb8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b68832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b688330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b688330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c482cb8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c (2226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target # | ... # `---data was truncated (10240/23439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005568231ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005568231c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005568231ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa462449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa462449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa462431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055682315fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055682315fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556823144b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556822df40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556822df3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa462432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556822df3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c (2227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vncvt_x_x_w_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c (2228 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056059ac0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056059abfd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056059ac0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ae961bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ae96725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ae961ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ae9603507 abort ./stdlib/abort.c:85:3 # | #7 0x000056059ab95e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056059ab95c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056059ab7ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056059a82a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056059a829dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ae9604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ae96050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ae96050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056059a829cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c (2229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_i32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_u32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e32_v_f32mf2x5_tum( %mask, target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c (2230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b5a19015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b5a18d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b5a19089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f433521bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43352725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f433521ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4335203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b5a125e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b5a125c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b5a10ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b59dba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b59db9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4335204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43352050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43352050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b59db9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c (2231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnot_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a3c7e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a3c7e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a3c7e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f677cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f677cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f677cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f677cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a3c77be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a3c77bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a3c760b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a3c4100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a3c40fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f677cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f677cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f677cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a3c40fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c (2232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32f16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32f16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, # | ... # `---data was truncated (10240/20307) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d4c00f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d4c00c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d4c00f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f766c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f766c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f766c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f766c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d4bfa4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d4bfa4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d4bf89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d4bc390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d4bc38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f766c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f766c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f766c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d4bc38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c (2233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( %1, ptr %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load p # | ... # `---data was truncated (10240/28353) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557914a4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557914a3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557914a4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53d9c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53d9ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53d9c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53d9c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579149d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579149d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579149bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055791466b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055791466add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f53d9c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53d9c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53d9c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055791466acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c (2234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055606e17015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055606e16d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055606e17089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb66249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb662a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb66249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb66231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055606e105e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055606e105c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055606e0eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055606dd9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055606dd99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb66232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb662330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb662330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055606dd99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c (2235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_tumu( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559ccf14e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559ccf14b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559ccf14e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc792733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc79278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc792733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc79271b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559ccf0e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559ccf0e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559ccf0c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559cced780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559cced77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc79271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc79271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc79271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cced77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-bf16-params-returns.c (2236 of 27911) ******************** TEST 'Clang :: CodeGen/arm-bf16-params-returns.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef bfloat @test_ret_bf16(bfloat noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret bfloat %v # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) # | define dso_local arm_aapcs_vfpcc noundef <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) local_unnamed_addr #0 { # | entry: # | ret <4 x bfloat> %v # | } # | # | attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.6-a,+bf16,+neon,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | !llvm.errno.tbaa = !{!6} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # | !6 = !{!7, !8, i64 0} # | !7 = !{!"__libc_errno", !8, i64 0} # | !8 = !{!"int", !9, i64 0} # | !9 = !{!"omnipotent char", !10, i64 0} # | !10 = !{!"Simple C/C++ TBAA"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x000055ec8906915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec890660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec8906989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8cf101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8cf10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8cf101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8cf1003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec88ffee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec88ffec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec88fe3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec88c930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec88c92dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8cf1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8cf10050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8cf10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec88c92cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-bf16-params-returns.c --check-prefix=CHECK32-HARD # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c (2237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_xu_f_v_u32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_rtz_x_f_v_i64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm # | ... # `---data was truncated (10240/35597) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055910a28d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055910a28a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055910a28d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2ac649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2ac6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2ac649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2ac631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055910a222e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055910a222c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055910a207b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559109eb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559109eb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe2ac632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2ac6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2ac6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559109eb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c (2238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10878) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7360cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7360c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7360cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99dd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99dd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99dd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99dd8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b736060e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b736060c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b736045b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b735cf50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b735cf4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99dd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99dd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99dd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b735cf4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c (2239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmax.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmax_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df7d57b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df7d5780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df7d57b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab79933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab7998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab79933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab7991b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df7d510e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df7d510c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df7d4f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df7d1a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df7d1a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab7991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab7991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab7991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df7d1a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c (2240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, # | ... # `---data was truncated (10240/40726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618e0d7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005618e0d760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005618e0d7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f025b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f025b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f025b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f025b031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618e0d0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005618e0d0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005618e0cf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005618e09a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005618e09a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f025b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f025b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f025b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618e09a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c (2241 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b30924b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b3092480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b30924b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9039849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f90398a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9039849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9039831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3091e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3091e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3091c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b308e750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b308e74dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9039832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f90398330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f90398330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b308e74cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c (2242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c (2243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005581ea04f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005581ea04c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005581ea04f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3302305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f330235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3302305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33022ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005581e9fe4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005581e9fe4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005581e9fc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005581e9c790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005581e9c78dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f33022eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33022ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33022ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581e9c78cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c (2244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac3825a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac382570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac3825a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa112e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa112ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa112e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa112e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac381efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac381efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac381d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac37e840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac37e83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa112e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa112e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa112e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac37e83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c (2245 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vmaxnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vmaxnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e4ff7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e4ff6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e4ff7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2ee049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2ee0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2ee049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2ee031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e4ff05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e4ff05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e4feeab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e4fb9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e4fb99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2ee032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2ee0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2ee0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e4fb99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c (2246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056509d79215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056509d78f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056509d79289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd776c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd776ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd776c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd776c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056509d727e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056509d727c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056509d70cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056509d3bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056509d3bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd776c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd776c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd776c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056509d3bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c (2247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei8_v_f64m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 # | ... # `---data was truncated (10240/99178) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576ee76515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005576ee7620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005576ee76589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b54e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b54ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b54e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b54e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576ee6fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005576ee6fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005576ee6dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005576ee38f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005576ee38edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b54e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b54e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b54e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576ee38ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c (2248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv4f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrdiv.nxv8f32.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/61058) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be990d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564be990a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564be990d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0d3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0d30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0d3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0d3031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be98a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564be98a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564be9887b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564be95370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564be9536dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0d3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0d30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0d30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be9536cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c (2249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | defi # | ... # `---data was truncated (10240/48385) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005626199e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005626199de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005626199e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45a1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45a1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45a1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45a1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562619976e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562619976c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056261995bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056261960b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056261960add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f45a1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45a1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45a1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056261960acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c (2250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_f16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, # | ... # `---data was truncated (10240/288103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d55162715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5516240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d55162789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b42e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b42ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b42e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b42e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5515bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5515bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5515a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5512510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d551250dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b42e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b42e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b42e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d551250cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c (2251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558424c1d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558424c1a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558424c1d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff4dd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff4dd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff4dd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff4dd631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558424bb2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558424bb2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558424b97b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005584248470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558424846dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff4dd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff4dd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff4dd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558424846cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c (2252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccus_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1771d615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1771d30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1771d689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0dd81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0dd8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0dd81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0dd803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b17716be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b17716bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b177150b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b176e000b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b176dffdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc0dd804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0dd8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0dd8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b176dffcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c (2253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f16m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vect # | ... # `---data was truncated (10240/113765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2a033415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2a03310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2a033489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e7b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e7b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e7b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e7b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2a02c9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a2a02c9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2a02aeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a29ff5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a29ff5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e7b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e7b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e7b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a29ff5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c (2254 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf4_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16mf2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m1_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vx_i16m2_tu( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccsu.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccsu_vv_i16m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/151245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005617e5d3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005617e5d350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005617e5d3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d81449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d814a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d81449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d81431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005617e5ccde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005617e5ccdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005617e5cb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005617e59620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005617e5961dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7d81432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d814330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d814330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005617e5961cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c (2255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmax.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmax_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmax.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/61937) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a46e9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a46e8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a46e9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f704df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f704df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f704df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f704df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a46e27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a46e27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a46e0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a46abc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a46abbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f704df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f704df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f704df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a46abbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c (2256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m2_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m4_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv32i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i8m8_i8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv32i8.nxv64i8(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m2_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m4_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv32i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv16i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_u8m8_u8m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv32i8.nxv64i8( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m2_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv8i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv8i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m4_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv16i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv16i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vget_v_i16m8_i16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4i16.nxv32i16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4i16.nxv32i16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale # | ... # `---data was truncated (10240/40902) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f75a2d515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f75a2d20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f75a2d589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd2c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd2c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd2c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd2c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f75a26ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f75a26ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f75a24fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f759eff0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f759efedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd2c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd2c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd2c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f759efecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c (2257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e12157d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e12157a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e12157d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3863e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3863e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3863e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3863e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e121512e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e121512c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1214f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1211a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1211a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3863e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3863e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3863e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1211a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c (2258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/30268) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564999ada15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564999ad70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564999ada89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa4ffb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa4ffb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa4ffb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa4ffb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564999a6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564999a6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564999a54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649997040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564999703dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa4ffb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa4ffb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa4ffb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564999703cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c (2259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593c41ab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005593c41a80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005593c41ab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aa1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aa14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aa1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aa1431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593c4140e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005593c4140c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005593c4125b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005593c3dd50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005593c3dd4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9aa1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aa14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aa14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593c3dd4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c (2260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractval # | ... # `---data was truncated (10240/13669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644490f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644490f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644490f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee22f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee22f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee22f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee22f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056444908ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056444908ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564449073b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564448d230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564448d22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fee22f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee22f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee22f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564448d22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c (2261 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bb0eb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558bb0eaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558bb0eb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efc81505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efc8155c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efc81505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efc814ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bb0e47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558bb0e47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558bb0e2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558bb0adc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558bb0adbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efc814eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efc814ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efc814ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bb0adbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c (2262 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dae78e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dae78b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dae78e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e65133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e6518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e65133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e6511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dae723e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dae723c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dae708b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dae3b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dae3b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5e6511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e6511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e6511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dae3b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c (2263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv2bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv2bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv4bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv4bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( %value) #0 { # | entry: # | %value.addr = alloca , align 2 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %value.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c (2264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d8d6d2a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d8d6d270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d8d6d2a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef77333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef7738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef77333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef7731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d8d6cbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d8d6cbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d8d6ca4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d8d69540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d8d6953dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fef7731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef7731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef7731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d8d6953cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c (2265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cbc46215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556cbc45f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556cbc46289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac97449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac974a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac97449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac97431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cbc3f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556cbc3f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556cbc3dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556cbc08c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556cbc08bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fac97432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac974330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac974330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cbc08bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c (2266 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7dbc0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7dbc070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7dbc0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e08b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e08b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e08b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e08b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7dbb9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e7dbb9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e7dbb84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e7db8340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e7db833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e08b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e08b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e08b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7db833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vbicq.c (2267 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vbicq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = and <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = and <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = and <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = and <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr # | ... # `---data was truncated (10240/11060) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005594aac1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594aac0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594aac1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d7ce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d7cea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d7ce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d7ce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594aaba7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594aaba7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594aab8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594aa83c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594aa83bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2d7ce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d7ce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d7ce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594aa83bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vbicq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c (2268 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfle.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c (2269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c (2270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646605ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005646605ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005646605ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8782649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87826a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8782649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8782631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564660543e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564660543c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564660528b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646601d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005646601d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8782632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87826330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87826330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646601d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c (2271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = loa # | ... # `---data was truncated (10240/18917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3214f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3214f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3214f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f754c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f754c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f754c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f754c003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c32148ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c32148ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c32146fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c32111f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c32111edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f754c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f754c0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f754c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c32111ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c (2272 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557efac2815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557efac250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557efac2889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb887a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb887a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb887a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb887a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557efabbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557efabbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557efaba2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557efa8520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557efa851dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb887a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb887a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb887a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557efa851cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c (2273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f16m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_f32m1x2_tu(target("riscv # | ... # `---data was truncated (10240/295533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff0554c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff055490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff0554c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc26bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc26bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc26bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc26bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff054e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff054e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff054c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff051760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff05175dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc26bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc26bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc26bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff05175cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c (2274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define # | ... # `---data was truncated (10240/37564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587dd66315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587dd6600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587dd66389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd9b6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9b62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd9b6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd9b6231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587dd5f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587dd5f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587dd5ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587dd28d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587dd28cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd9b6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9b62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9b62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587dd28ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c (2275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4366b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4366b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4366b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad70733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad7078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad70733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad7071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f43664ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f43664cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f436631b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4362e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4362e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad7071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad7071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad7071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4362e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c (2276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563134e7815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563134e750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563134e7889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb635533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb63558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb635533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb63551b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563134e0de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563134e0dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563134df2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563134aa20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563134aa1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb63551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb63551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb63551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563134aa1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c (2277 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv # | ... # `---data was truncated (10240/53726) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ca553a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ca55370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ca553a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2628649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26286a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2628649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2628631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ca54cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ca54cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ca54b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ca51640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ca5163dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2628632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26286330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26286330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ca5163cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c (2278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16 # | ... # `---data was truncated (10240/69305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f38308c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3830890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f38308c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4230c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4230ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4230c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4230c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f383021e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f383021c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f383006b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f382cb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f382cb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4230c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4230c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4230c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f382cb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c (2279 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, i32 noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %.splat, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056347b4c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056347b4c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056347b4c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd0c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd0c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd0c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd0c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056347b45ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056347b45ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056347b43fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056347b0ef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056347b0eedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd0c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd0c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd0c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056347b0eecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c (2280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bf0be315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555bf0be00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555bf0be389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa1fa533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1fa58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa1fa533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa1fa51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bf0b78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555bf0b78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555bf0b5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555bf080d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555bf080cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa1fa51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1fa51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1fa51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bf080ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c (2281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_i8m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf8x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv1i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8ff_v_u8mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %ba # | ... # `---data was truncated (10240/15594) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620f484715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620f48440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005620f484789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa170649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa1706a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa170649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa170631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620f47dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620f47dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005620f47c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620f44710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005620f4470dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa170632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa1706330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa1706330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620f4470cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c (2282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_f64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_i64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u8m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u16m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32mf2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u32m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m1() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m2() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m4() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vundefined_u64m8() #0 { # | entry: # | ret poison # | } # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/63140) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056514c5cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056514c5cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056514c5cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc43eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc43eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc43eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc43eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056514c564e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056514c564c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056514c549b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056514c1f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056514c1f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc43eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc43eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc43eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056514c1f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c (2283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c (2284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %m # | ... # `---data was truncated (10240/41661) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a65830c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6583090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a65830c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f04a2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f04a24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f04a2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f04a2431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6582a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a6582a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a658286b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a657f360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a657f35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f04a2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f04a24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f04a24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a657f35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c (2285 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 immarg) #1 # | ... # `---data was truncated (10240/78234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005576b67fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005576b67fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005576b67fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f4281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f428725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f4281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f42803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005576b6792e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005576b6792c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005576b6777b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005576b64270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005576b6426dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6f42804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f428050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f428050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576b6426cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 2, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c (2287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e95eb7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e95eb770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e95eb7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc202e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc202ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc202e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc202e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e95eb0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e95eb0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e95eaf4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e95e7a40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e95e7a3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc202e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc202e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc202e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e95e7a3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c (2288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dbe347815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dbe34750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dbe347889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8856c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8856ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8856c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8856c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dbe340de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dbe340dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dbe33f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dbe30a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dbe30a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8856c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8856c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8856c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dbe30a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c (2289 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056402059a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005640205970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056402059a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fac6101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fac610725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fac6101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fac61003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056402052fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056402052fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564020514b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005640201c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005640201c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fac61004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fac610050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fac610050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005640201c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c (2290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c (2291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641e1e6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641e1e610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641e1e6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe118733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe11878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe118733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe11871b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005641e1df9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005641e1df9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005641e1ddeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641e1a8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641e1a8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe11871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe11871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe11871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641e1a8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/WebAssembly/builtins-table-funcref.c (2292 of 27911) ******************** TEST 'Clang :: CodeGen/WebAssembly/builtins-table-funcref.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32" # | # | @table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | @other_table = internal addrspace(1) global [0 x target("wasm.funcref")] zeroinitializer, align 4 # | # | ; Function Attrs: noinline nounwind # | define target("wasm.funcref") @test_builtin_wasm_table_get(i32 noundef %index) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = call target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 %0) # | ret target("wasm.funcref") %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("wasm.funcref") @llvm.wasm.table.get.funcref(ptr addrspace(1), i32) #1 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_set(i32 noundef %index, target("wasm.funcref") noundef %ref) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.wasm.table.set.funcref(ptr addrspace(1), i32, target("wasm.funcref")) #2 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_size() #0 { # | entry: # | %0 = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) # | ret i32 %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare i32 @llvm.wasm.table.size(ptr addrspace(1)) #1 # | # | ; Function Attrs: noinline nounwind # | define i32 @test_builtin_wasm_table_grow(target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %1 = load i32, ptr %nelem.addr, align 4 # | %2 = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, target("wasm.funcref") %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1), target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_builtin_wasm_table_fill(i32 noundef %index, target("wasm.funcref") noundef %ref, i32 noundef %nelem) #0 { # | entry: # | %index.addr = alloca i32, align 4 # | %ref.addr = alloca target("wasm.funcref"), align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %index, ptr %index.addr, align 4 # | store target("wasm.funcref") %ref, ptr %ref.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %index.addr, align 4 # | %1 = load target("wasm.funcref"), ptr %ref.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 %0, target("wasm.funcref") %1, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.fill.funcref(ptr addrspace(1), i32, target("wasm.funcref"), i32) #3 # | # | ; Function Attrs: noinline nounwind # | define void @test_table_copy(i32 noundef %dst_idx, i32 noundef %src_idx, i32 noundef %nelem) #0 { # | entry: # | %dst_idx.addr = alloca i32, align 4 # | %src_idx.addr = alloca i32, align 4 # | %nelem.addr = alloca i32, align 4 # | store i32 %dst_idx, ptr %dst_idx.addr, align 4 # | store i32 %src_idx, ptr %src_idx.addr, align 4 # | store i32 %nelem, ptr %nelem.addr, align 4 # | %0 = load i32, ptr %dst_idx.addr, align 4 # | %1 = load i32, ptr %src_idx.addr, align 4 # | %2 = load i32, ptr %nelem.addr, align 4 # | call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 %1, i32 %0, i32 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.wasm.table.copy(ptr addrspace(1), ptr addrspace(1), i32, i32, i32) #3 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+reference-types" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(write) } # | attributes #3 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b92caff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b92cafc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b92caff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80d701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80d70725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80d701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80d7003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b92ca94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b92ca94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b92ca79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b92c7290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b92c728dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80d7004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80d70050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80d70050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b92c728cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c (2293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643b8e4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643b8e3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643b8e4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa268a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa268aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa268a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa268a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643b8dd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643b8dd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643b8dbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643b8a6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643b8a6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa268a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa268a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa268a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643b8a6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c (2294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/164791) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c58552015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c58551d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c58552089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6291649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f62916a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6291649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6291631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5854b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5854b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c58549ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c58514a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c585149dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6291632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f62916330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f62916330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c585149cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c (2295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.viota.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_viota_m_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.viota.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare < # | ... # `---data was truncated (10240/40411) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c93de3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c93de330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c93de3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97a7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97a718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97a7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97a711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c93ddcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c93ddcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c93ddb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c93da600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c93da5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97a711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97a711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97a711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c93da5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c (2296 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8_tu( %maskedoff, %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( %0, %1, half %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2_tu( %maskedoff, %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( %0, %1, float %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/22367) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005641296cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641296cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005641296cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5aa2c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5aa2ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5aa2c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5aa2c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564129664e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564129664c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564129649b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641292f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641292f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5aa2c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5aa2c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5aa2c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641292f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/inline-then-fold-variadics.cpp (2297 of 27911) ******************** TEST 'Clang :: CodeGenCXX/inline-then-fold-variadics.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes='module(expand-variadics,default)' --expand-variadics-override=optimize -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp -triple wasm32-unknown-unknown -Wno-varargs -O1 -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp" # | target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20" # | target triple = "wasm32-unknown-unknown" # | # | %struct.asc = type { i8, i16, i32, i32, float, double } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIiiET_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_pair_i32(i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIiiET0_z(i32 noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIiiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %0 = load i32, ptr %argp.next, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIddET_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIddET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_pair_f64(double noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIddET0_z(double noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIddET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %1 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 16 # | store ptr %argp.next2, ptr %va, align 4 # | %2 = load double, ptr %1, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %2 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL5firstIidET_z(i32 noundef %x, double noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIidET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @second_i32_f64(i32 noundef %x, double noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL6secondIidET0_z(i32 noundef %x, double noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL6secondIidET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 11 # | %argp.cur1.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur1.aligned, i32 8 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load double, ptr %argp.cur1.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef double @first_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef double (...) @_ZL5firstIdiET_z(double noundef %x, i32 noundef %y) # | ret double %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef double @_ZL5firstIdiET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | store ptr %argp.next, ptr %va, align 4 # | %1 = load double, ptr %argp.cur.aligned, align 8, !tbaa !7 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret double %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @second_f64_i32(double noundef %x, i32 noundef %y) local_unnamed_addr #0 { # | entry: # | %call = tail call noundef i32 (...) @_ZL6secondIdiET0_z(double noundef %x, i32 noundef %y) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL6secondIdiET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %0 = getelementptr inbounds nuw i8, ptr %argp.cur, i32 7 # | %argp.cur.aligned = call align 8 ptr @llvm.ptrmask.p0.i32(ptr nonnull %0, i32 -8) # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 8 # | %argp.next2 = getelementptr inbounds nuw i8, ptr %argp.cur.aligned, i32 12 # | store ptr %argp.next2, ptr %va, align 4 # | %1 = load i32, ptr %argp.next, align 8, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %1 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define noundef i32 @first_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef i32 (...) @_ZL5firstIiDv2_yET_z(i32 noundef %x, <2 x i64> noundef %0) # | ret i32 %call # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef i32 @_ZL5firstIiDv2_yET_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr nonnull %va) # | %argp.cur = load ptr, ptr %va, align 4 # | %argp.next = getelementptr inbounds nuw i8, ptr %argp.cur, i32 4 # | store ptr %argp.next, ptr %va, align 4 # | %0 = load i32, ptr %argp.cur, align 4, !tbaa !6 # | call void @llvm.va_end.p0(ptr %va) # | call void @llvm.lifetime.end.p0(ptr nonnull %va) #4 # | ret i32 %0 # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define void @second_i32_ulong2(i32 noundef %x, ptr nofree noundef readonly captures(none) %y, ptr nofree noundef writeonly captures(none) initializes((0, 16)) %r) local_unnamed_addr #0 { # | entry: # | %0 = load <2 x i64>, ptr %y, align 16, !tbaa !9 # | %call = tail call noundef <2 x i64> (...) @_ZL6secondIiDv2_yET0_z(i32 noundef %x, <2 x i64> noundef %0) # | store <2 x i64> %call, ptr %r, align 16, !tbaa !9 # | ret void # | } # | # | ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn # | define internal noundef <2 x i64> @_ZL6secondIiDv2_yET0_z(...) unnamed_addr #0 { # | entry: # | %va = alloca ptr, align 4 # | call void @llvm.lifetime.start.p0(ptr nonnull %va) #4 # | call void @llvm.va_start.p0(ptr n # | ... # `---data was truncated (10240/20646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S '--passes=module(expand-variadics,default)' --expand-variadics-override=optimize -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt - -S --passes=module(expand-variadics,default) --expand-variadics-override=optimize -o - # | #0 0x0000560dbad6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560dbad640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560dbad6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f82b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f82b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f82b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f82b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560dbacfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560dbacfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560dbace1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560dba9910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560dba990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5f82b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f82b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f82b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560dba990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/inline-then-fold-variadics.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c (2298 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsle_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsle.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558b5bffb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558b5bff80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558b5bffb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc83ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc83eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc83ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc83ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558b5bf90e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558b5bf90c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558b5bf75b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558b5bc250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558b5bc24dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc83ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc83ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc83ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558b5bc24cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c (2299 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d33a8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d33a890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d33a8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61b7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61b70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61b7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61b7031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d33a21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d33a21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d33a06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d336b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d336b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61b7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61b70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61b70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d336b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c (2300 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0be17e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0be17b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0be17e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde66849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde668a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde66849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde66831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0be113e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c0be113c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c0be0f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0bdda80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c0bdda7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde66832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde668330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde668330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0bdda7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c (2301 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsll.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsll.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsll_vv_i8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/aapcs-bitfield.c (2302 of 27911) ******************** TEST 'Clang :: CodeGen/aapcs-bitfield.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8-none-linux-eabi -fno-aapcs-bitfield-width -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8-none-linux-eabi" # | # | %struct.st6 = type { i16, i8, i8 } # | %struct.st7b = type { i8, [3 x i8], %struct.st7a } # | %struct.st7a = type { i8, i8, [2 x i8] } # | %struct.st11 = type <{ i8, i16, i8 }> # | %struct.st13 = type <{ i8, i32 }> # | %struct.st16 = type { i32, i16, i32, i16 } # | %struct.st17 = type <{ i32, i8 }> # | %struct.zero_bitfield = type { i8, i8, [2 x i8] } # | %struct.zero_bitfield_ok = type { i16, i32 } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st0_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st0_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st1_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.ashr = ashr i16 %bf.load, 10 # | %conv = sext i16 %bf.ashr to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st1_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, 1023 # | %bf.set = or i16 %bf.clear, 1024 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st2_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 9 # | %bf.ashr = ashr i32 %bf.shl, 25 # | %bf.cast = trunc i32 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st2_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -8323073 # | %bf.set = or i32 %bf.clear, 65536 # | store i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st3_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.shl = shl i8 %bf.load, 1 # | %bf.ashr = ashr i8 %bf.shl, 1 # | %bf.cast = sext i8 %bf.ashr to i16 # | %conv = sext i16 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st3_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 2 # | %bf.clear = and i8 %bf.load, -128 # | %bf.set = or i8 %bf.clear, 1 # | store volatile i8 %bf.set, ptr %0, align 2 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st4_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 2 # | %bf.ashr = ashr i16 %bf.shl, 11 # | %bf.cast = trunc i16 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -15873 # | %bf.set = or i16 %bf.clear, 512 # | store volatile i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st4_check_nonv_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -512 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st5_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.shl = shl i32 %bf.load, 11 # | %bf.ashr = ashr i32 %bf.shl, 27 # | %bf.cast = trunc i32 %bf.ashr to i8 # | %conv = sext i8 %bf.cast to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st5_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i32, ptr %0, align 4 # | %bf.clear = and i32 %bf.load, -2031617 # | %bf.set = or i32 %bf.clear, 65536 # | store volatile i32 %bf.set, ptr %0, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st6_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %x = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i16, ptr %0, align 4 # | %bf.shl = shl i16 %bf.load, 4 # | %bf.ashr = ashr i16 %bf.shl, 4 # | %bf.cast = sext i16 %bf.ashr to i32 # | store i32 %bf.cast, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | %2 = load volatile i8, ptr %b, align 2 # | %conv = sext i8 %2 to i32 # | %3 = load i32, ptr %x, align 4 # | %add = add nsw i32 %3, %conv # | store i32 %add, ptr %x, align 4 # | %4 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %4, i32 0, i32 2 # | %bf.load1 = load volatile i8, ptr %c, align 1 # | %bf.shl2 = shl i8 %bf.load1, 3 # | %bf.ashr3 = ashr i8 %bf.shl2, 3 # | %bf.cast4 = sext i8 %bf.ashr3 to i32 # | %5 = load i32, ptr %x, align 4 # | %add5 = add nsw i32 %5, %bf.cast4 # | store i32 %add5, ptr %x, align 4 # | %6 = load i32, ptr %x, align 4 # | ret i32 %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st6_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load i16, ptr %0, align 4 # | %bf.clear = and i16 %bf.load, -4096 # | %bf.set = or i16 %bf.clear, 1 # | store i16 %bf.set, ptr %0, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %b = getelementptr inbounds nuw %struct.st6, ptr %1, i32 0, i32 1 # | store i8 2, ptr %b, align 2 # | %2 = load ptr, ptr %m.addr, align 4 # | %c = getelementptr inbounds nuw %struct.st6, ptr %2, i32 0, i32 2 # | %bf.load1 = load i8, ptr %c, align 1 # | %bf.clear2 = and i8 %bf.load1, -32 # | %bf.set3 = or i8 %bf.clear2, 3 # | store i8 %bf.set3, ptr %c, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st7_check_load(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | %r = alloca i32, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | %1 = load i8, ptr %x, align 4 # | %conv = sext i8 %1 to i32 # | store i32 %conv, ptr %r, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | %3 = load volatile i8, ptr %a, align 4 # | %conv1 = sext i8 %3 to i32 # | %4 = load i32, ptr %r, align 4 # | %add = add nsw i32 %4, %conv1 # | store i32 %add, ptr %r, align 4 # | %5 = load ptr, ptr %m.addr, align 4 # | %y2 = getelementptr inbounds nuw %struct.st7b, ptr %5, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y2, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.shl = shl i8 %bf.load, 3 # | %bf.ashr = ashr i8 %bf.shl, 3 # | %bf.cast = sext i8 %bf.ashr to i32 # | %6 = load i32, ptr %r, align 4 # | %add3 = add nsw i32 %6, %bf.cast # | store i32 %add3, ptr %r, align 4 # | %7 = load i32, ptr %r, align 4 # | ret i32 %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @st7_check_store(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %x = getelementptr inbounds nuw %struct.st7b, ptr %0, i32 0, i32 0 # | store i8 1, ptr %x, align 4 # | %1 = load ptr, ptr %m.addr, align 4 # | %y = getelementptr inbounds nuw %struct.st7b, ptr %1, i32 0, i32 2 # | %a = getelementptr inbounds nuw %struct.st7a, ptr %y, i32 0, i32 0 # | store volatile i8 2, ptr %a, align 4 # | %2 = load ptr, ptr %m.addr, align 4 # | %y1 = getelementptr inbounds nuw %struct.st7b, ptr %2, i32 0, i32 2 # | %b = getelementptr inbounds nuw %struct.st7a, ptr %y1, i32 0, i32 1 # | %bf.load = load volatile i8, ptr %b, align 1 # | %bf.clear = and i8 %bf.load, -32 # | %bf.set = or i8 %bf.clear, 3 # | store volatile i8 %bf.set, ptr %b, align 1 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @st8_check_assignment(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | store i16 -1, ptr %0, align 4 # | ret i32 65535 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @read_st9(ptr noundef %m) #0 { # | entry: # | %m.addr = alloca ptr, align 4 # | store ptr %m, ptr %m.addr, align 4 # | %0 = load ptr, ptr %m.addr, align 4 # | %bf.load = load volatile i8, ptr %0, align 4 # | %bf.cast = sext i8 %bf.load to i32 # | r # | ... # `---data was truncated (10240/24998) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650f3e2115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650f3e1e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650f3e2189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28b4333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28b438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28b4333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28b431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650f3db6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650f3db6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650f3d9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650f3a4b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650f3a4add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28b431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28b431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28b431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650f3a4acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/aapcs-bitfield.c -check-prefix=LE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c (2303 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d69f8ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d69f8aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d69f8ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e7b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e7b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e7b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e7b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d69f842e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d69f842c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d69f827b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d69f4d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d69f4d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5e7b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e7b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e7b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d69f4d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c (2304 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d72791b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7279180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d72791b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff7d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff7d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff7d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff7d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7278b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7278b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d727895b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7275450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d727544dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff7d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff7d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff7d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d727544cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c (2305 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc8ab5d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc8ab5a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc8ab5d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92f2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92f28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92f2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92f2831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc8aaf2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc8aaf2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc8aad7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc8a7870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc8a786dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f92f2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92f28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92f28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc8a786cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/absneg.c (2306 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/absneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabsq_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | ret <8 x half> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabsq_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | ret <4 x float> %1 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = icmp slt <16 x i8> %0, zeroinitializer # | %2 = sub <16 x i8> zeroinitializer, %0 # | %3 = select <16 x i1> %1, <16 x i8> %2, <16 x i8> %0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = icmp slt <8 x i16> %0, zeroinitializer # | %2 = sub <8 x i16> zeroinitializer, %0 # | %3 = select <8 x i1> %1, <8 x i16> %2, <8 x i16> %0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = icmp slt <4 x i32> %0, zeroinitializer # | %2 = sub <4 x i32> zeroinitializer, %0 # | %3 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = xor <16 x i8> %0, splat (i8 -1) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = xor <8 x i16> %0, splat (i16 -1) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = xor <4 x i32> %0, splat (i32 -1) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_m_u8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.mvn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_u32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmvnq_x_s8(<16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = al # | ... # `---data was truncated (10240/40137) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c1958115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c1957e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c1958189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e4581bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e458725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e4581ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e45803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c19516e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c19516c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c194fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c191ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c191aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e45804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e458050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e458050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c191aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/absneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c (2307 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vcpop.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vcpop.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vcpop_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vcpop.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nof # | ... # `---data was truncated (10240/11966) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562759bc815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562759bc50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562759bc889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe227e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe227ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe227e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe227e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562759b5de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562759b5dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562759b42b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627597f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627597f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe227e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe227e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe227e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627597f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c (2308 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8mf2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8_v_u8m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vect # | ... # `---data was truncated (10240/24229) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644445b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644445b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644445b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4d57849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4d578a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4d57849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4d57831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056444454ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056444454ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564444533b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644441e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644441e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4d57832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4d578330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4d578330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644441e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c (2309 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.r # | ... # `---data was truncated (10240/33423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619efb9115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005619efb8e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619efb9189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f89be105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f89be15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f89be105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f89be0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619efb26e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005619efb26c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005619efb0bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619ef7bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619ef7badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f89be0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f89be0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f89be0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619ef7bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c (2310 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac2d2b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac2d2b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac2d2b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd42d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd42d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd42d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd42d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac2d248e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac2d248c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac2d22db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac2cedd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac2cedcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd42d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd42d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd42d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac2cedccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c (2311 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16mf2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv2f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv2f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m1_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv4f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv4f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m2_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv8f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv8f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m4_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv16f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv16f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv1f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv1f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16mf2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv2f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv2f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m1( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m2( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8f16.nxv32f16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlmul_trunc_v_f16m8_f16m4( %op1) #0 { # | entry: # | %op1.addr = alloca , align 2 # | store %op1, ptr %op1.addr, align 2 # | %0 = load , ptr %op1.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16f16.nxv32f16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16f16.nxv32f16(, i64 im # | ... # `---data was truncated (10240/78242) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c2a41415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c2a4110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c2a41489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fccb7f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fccb7f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fccb7f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fccb7f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c2a3a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c2a3a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c2a38eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c2a03e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c2a03ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fccb7f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fccb7f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fccb7f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2a03dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c (2312 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/97913) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8cfa2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8cfa1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8cfa2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1adc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1adca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1adc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1adc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8cf9b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c8cf9b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c8cf99ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8cf64a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8cf649dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1adc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1adc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1adc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8cf649cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c (2313 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648f91df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648f91dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648f91df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1064a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1064aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1064a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1064a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648f9174e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648f9174c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648f9159b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648f8e090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648f8e08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1064a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1064a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1064a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648f8e08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vabdq.c (2314 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vabdq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %0, <8 x half> %1, i32 0) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056434963b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643496380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056434963b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f86933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f8698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f86933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f8691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643495d0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643495d0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643495b5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643492650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564349264dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f8691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f8691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f8691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564349264cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c (2315 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf4_f8e4m3mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16mf2_f8e4m3mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m1_f8e4m3mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m2_f8e4m3m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.sat.f.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.f.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_sat_f_f_w_bf16m4_f8e4m3m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, ali # | ... # `---data was truncated (10240/201234) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b4dd81e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b4dd81b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b4dd81e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83d8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83d82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83d8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83d8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b4dd7b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b4dd7b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b4dd798b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b4dd4480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b4dd447dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f83d8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83d82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83d82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b4dd447cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c (2316 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i64.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c (2317 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555db7d4915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555db7d460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555db7d4989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c9af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c9af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c9af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c9af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555db7cdee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555db7cdec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555db7cc3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555db79730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555db7972dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c9af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c9af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c9af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555db7972cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c (2318 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv32i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv64i8.i8.i64( poison, %0, i8 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv1i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv2i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv4i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv8i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vxor.nxv16i16.i16.i64( poison, %0, i16 -1, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnot_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c (2319 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u16m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwcvtu_x_x_v_u32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i6 # | ... # `---data was truncated (10240/67158) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e18f0815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558e18f050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558e18f0889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5362933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f536298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5362933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f536291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e18e9de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558e18e9dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558e18e82b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558e18b320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558e18b31dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f536291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f536291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f536291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e18b31cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c (2320 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_s_w4_i8m8_i8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.s.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb2903a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb290370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb2903a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3cbe1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3cbe725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3cbe1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3cbe03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb28fcfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb28fcfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb28fb4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb28c640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb28c63dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3cbe04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3cbe050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3cbe050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb28c63cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c (2321 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32bf16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv1bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrec7.mask.nxv2bf16.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.mask.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | # | ... # `---data was truncated (10240/28350) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db3d3cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db3d3cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db3d3cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa85f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa85f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa85f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa85f831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db3d364e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db3d364c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db3d349b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db3cff90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db3cff8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa85f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa85f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa85f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db3cff8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c (2322 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv1i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv2i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv4i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv8i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vv_u8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vasubu_vx_u8m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vasubu.nxv16i8.i8.i64( poison, %0, i8 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vasubu.nxv16i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_lo # | ... # `---data was truncated (10240/99851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055733560815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573356050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055733560889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c7ee1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c7ee725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c7ee1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c7ee03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055733559de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055733559dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557335582b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573352320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557335231dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c7ee04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c7ee050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c7ee050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557335231cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c (2323 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3(ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale # | ... # `---data was truncated (10240/10790) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b58196b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5819680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b58196b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fea5de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fea5de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fea5de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fea5de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b581900e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b581900c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5818e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5815950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b581594dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fea5de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fea5de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fea5de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b581594cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c (2324 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulhsu.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulhsu_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llv # | ... # `---data was truncated (10240/18669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f58b45c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f58b4590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f58b45c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f208a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f208a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f208a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f208a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f58b3f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f58b3f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f58b3d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f58b0860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f58b085dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f208a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f208a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f208a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f58b085cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-neon-numeric-maxmin.c (2325 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-numeric-maxmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vmaxnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vmaxnm_v2.i = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %vmaxnm_v.i, <2 x float> %vmaxnm_v1.i) # | %vmaxnm_v3.i = bitcast <2 x float> %vmaxnm_v2.i to <8 x i8> # | store <8 x i8> %vmaxnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vmaxnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vmaxnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vmaxnmq_v2.i = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %vmaxnmq_v.i, <4 x float> %vmaxnmq_v1.i) # | %vmaxnmq_v3.i = bitcast <4 x float> %vmaxnmq_v2.i to <16 x i8> # | store <16 x i8> %vmaxnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vminnm_v.i = bitcast <8 x i8> %2 to <2 x float> # | %vminnm_v1.i = bitcast <8 x i8> %3 to <2 x float> # | %vminnm_v2.i = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %vminnm_v.i, <2 x float> %vminnm_v1.i) # | %vminnm_v3.i = bitcast <2 x float> %vminnm_v2.i to <8 x i8> # | store <8 x i8> %vminnm_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vminnmq_v.i = bitcast <16 x i8> %2 to <4 x float> # | %vminnmq_v1.i = bitcast <16 x i8> %3 to <4 x float> # | %vminnmq_v2.i = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %vminnmq_v.i, <4 x float> %vminnmq_v1.i) # | %vminnmq_v3.i = bitcast <4 x float> %vminnmq_v2.i to <16 x i8> # | store <16 x i8> %vminnmq_v3.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005654d42df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005654d42dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005654d42df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa650905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa65095c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa650905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6508ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005654d4274e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005654d4274c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005654d4259b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005654d3f090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005654d3f08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa6508eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6508ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6508ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005654d3f08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-numeric-maxmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c (2326 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8_tu( %maskedoff, %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load half, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1_tu( %maskedoff, %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 4 # | %2 = load float, ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( %0, %1, float %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2_tu( %maskedoff, %src, float noundef %value, i64 noundef # | ... # `---data was truncated (10240/78336) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef7585515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef758520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef7585589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f510f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f510f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f510f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f510f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef757eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef757eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef757cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef7547f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef7547edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f510f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f510f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f510f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef7547ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c (2327 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32bf16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056237e5ce15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056237e5cb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056237e5ce89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94b1b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94b1b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94b1b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94b1b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056237e563e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056237e563c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056237e548b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056237e1f80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056237e1f7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f94b1b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94b1b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94b1b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056237e1f7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c (2328 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_f16m4( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c (2329 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055599fb3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055599fb320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055599fb3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f370cf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f370cf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f370cf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f370cf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055599facae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055599facac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055599faafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055599f75f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055599f75edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f370cf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f370cf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f370cf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055599f75ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c (2330 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591f3f2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591f3f280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591f3f2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb97849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb978a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb97849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb97831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591f3ec0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005591f3ec0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005591f3ea5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005591f3b550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005591f3b54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb97832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb978330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb978330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591f3b54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c (2331 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c (2332 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c91633c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c9163390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c91633c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff953849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff9538a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff953849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff953831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c9162d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c9162d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c9162b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c915f660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c915f65dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff953832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff9538330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff9538330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c915f65cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c (2333 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vpaire.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vpaire_vv_f32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c (2334 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589d20aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005589d20a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005589d20aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa52305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa5235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa52305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa522ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589d203fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005589d203fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005589d2024b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589d1cd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005589d1cd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa522eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa522ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa522ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589d1cd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c (2335 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac7353f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac7353c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac7353f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc566b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc566b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc566b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc566b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac734d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac734d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac734b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac731690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac73168dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc566b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc566b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc566b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac73168cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c (2336 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | # | ... # `---data was truncated (10240/11938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c916b8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c916b870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c916b8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cf0505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cf055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cf0505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cf04ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c916b1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c916b1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c916b04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c9167b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c9167b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4cf04eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cf04ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cf04ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c9167b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c (2337 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562aa803b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562aa80380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562aa803b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ddb849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ddb8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ddb849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ddb831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562aa7fd0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562aa7fd0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562aa7fb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562aa7c650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562aa7c64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ddb832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ddb8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ddb8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562aa7c64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c (2338 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsrl_wv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = allo # | ... # `---data was truncated (10240/154609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b829ca115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b829c9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b829ca189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f339d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f339d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f339d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f339d803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b829c36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b829c36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b829c1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8298cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8298cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f339d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f339d8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f339d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8298cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c (2339 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | # | ... # `---data was truncated (10240/25616) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560483eb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560483eb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560483eb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd78333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd7838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd78333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd7831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560483e48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560483e48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560483e2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560483add0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560483adcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd7831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd7831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd7831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560483adccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c (2340 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.n # | ... # `---data was truncated (10240/95355) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f5e59de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f5e59db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f5e59de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ad9049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ad90a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ad9049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ad9031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f5e5973e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f5e5973c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f5e5958b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f5e56080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f5e5607dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ad9032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ad90330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ad90330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f5e5607cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c (2341 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8007e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8007e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f8007e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72c001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72c00725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72c001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72c0003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f80077be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f80077bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f800760b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f8004100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f80040fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72c0004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72c00050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72c00050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f80040fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c (2342 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_i8m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf8x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv1i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf4x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e8_v_u8mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl. # | ... # `---data was truncated (10240/13557) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055955f50615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055955f5030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055955f50689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb01c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb01ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb01c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb01c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055955f49be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055955f49bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055955f480b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055955f1300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055955f12fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb01c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb01c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb01c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055955f12fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c (2343 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563e3c94915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563e3c9460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563e3c94989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7730849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77308a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7730849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7730831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563e3c8dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563e3c8dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563e3c8c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563e3c5730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563e3c572dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7730832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77308330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77308330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563e3c572cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c (2344 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1down_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1down.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1down.nxv8f32.f32.i64(, , float, i64) # | ... # `---data was truncated (10240/34765) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a0957e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a0957b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a0957e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff47d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff47d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff47d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff47d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a09513e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a09513c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a094f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a091a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a091a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff47d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff47d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff47d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a091a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c (2345 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577dfa7415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005577dfa710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005577dfa7489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd61d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd61d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd61d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd61d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577dfa09e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005577dfa09c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005577df9eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005577df69e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005577df69ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd61d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd61d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd61d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577df69dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c (2346 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a4c0aa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558a4c0a70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558a4c0aa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd7b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd7b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd7b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd7b031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a4c03fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558a4c03fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558a4c024b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558a4bcd40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558a4bcd3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd7b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd7b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd7b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a4bcd3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c (2347 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603116a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056031169d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603116a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48ec533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48ec58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48ec533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48ec51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560311635e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560311635c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056031161ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005603112ca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005603112c9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48ec51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48ec51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48ec51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005603112c9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c (2348 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c (2349 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c (2350 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = # | ... # `---data was truncated (10240/14319) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556de4a3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556de4a390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556de4a3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa95e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa95e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa95e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa95e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556de49d1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556de49d1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556de49b6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556de46660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556de4665dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa95e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa95e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa95e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556de4665cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c (2351 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_i8m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv64i8.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8mf2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i8.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8ff_v_u8m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, al # | ... # `---data was truncated (10240/30013) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564fe81cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564fe81c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564fe81cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b0c105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b0c15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b0c105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b0c0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564fe8160e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564fe8160c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564fe8145b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564fe7df50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564fe7df4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2b0c0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b0c0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b0c0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564fe7df4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c (2352 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c (2353 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32, <8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32, <4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot180_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot270_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot270_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32, <8 x half>, <8 x half>, <8 x half>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot90_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4) # | %6 = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> %0, <8 x half> %1, <8 x half> %2, <8 x i1> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vcmulq_rot90_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %inactive.addr, align 8 # | %1 = load <4 x float>, ptr %a.addr, align 8 # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 %3 to i32 # | %5 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %4) # | %6 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x i1> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vcmulq_rot180_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %inactive.addr, align 8 # | %1 = load <8 x half>, ptr %a.addr, align 8 # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = load i16, ptr %p.addr, align 2 # | %4 = zext i16 % # | ... # `---data was truncated (10240/20326) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da5dec215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da5debf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da5dec289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6531533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f653158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6531533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f653151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da5de57e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da5de57c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da5de3cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da5daec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da5daebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f653151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f653151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f653151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da5daebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vcmulq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c (2354 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmul.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmul.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmul_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c (2355 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 5) # | ret ta # | ... # `---data was truncated (10240/32031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561f83ba415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561f83ba10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561f83ba489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2657f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2657f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2657f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2657f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561f83b39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561f83b39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561f83b1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561f837ce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561f837cddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2657f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2657f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2657f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561f837cdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c (2356 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648d3e5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648d3e520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648d3e5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe85a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe85aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe85a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe85a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648d3deae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648d3deac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648d3dcfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648d3a7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648d3a7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbe85a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe85a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe85a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648d3a7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c (2357 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593f9a9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005593f9a910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005593f9a9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7485649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74856a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7485649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7485631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005593f9a29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005593f9a29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005593f9a0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005593f96be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005593f96bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7485632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74856330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74856330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005593f96bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c (2358 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettm_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9020e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9020e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9020e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37b0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37b0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37b0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37b0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d902078e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d902078c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d90205db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d901d0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d901d0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37b0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37b0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37b0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d901d0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c (2359 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsrl.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c (2360 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585a913915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585a91360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585a913989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5339b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5339b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5339b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5339b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585a90cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585a90cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585a90b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585a8d630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585a8d62dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5339b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5339b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5339b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585a8d62cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c (2361 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrec7.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0c432915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0c43260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e0c432989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff82721bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8272725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff82721ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff827203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0c42bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e0c42bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e0c42a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e0c3f530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e0c3f52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff827204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8272050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8272050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0c3f52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c (2362 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align # | ... # `---data was truncated (10240/18311) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573c802215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573c801f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005573c802289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbbc9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbbc955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbbc9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbbc94ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573c7fb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005573c7fb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005573c7f9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573c7c4c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005573c7c4bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbbc94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbbc94ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbbc94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573c7c4bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c (2363 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_ # | ... # `---data was truncated (10240/13617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056347dd1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056347dd0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056347dd1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc329133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc32918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc329133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc32911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056347dca5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056347dca5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056347dc8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056347d93a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056347d939dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc32911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc32911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc32911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056347d939cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c (2364 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vctz.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vctz_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vctz.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | ... # `---data was truncated (10240/40669) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b1a50815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b1a5050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b1a50889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61e3133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61e318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61e3133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61e311b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b1a49de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b1a49dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b1a482b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b1a1320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b1a131dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61e311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61e311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61e311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b1a131cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c (2365 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c (2366 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call < # | ... # `---data was truncated (10240/101483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e93fabf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e93fabc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e93fabf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0542b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0542b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0542b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0542b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e93fa54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e93fa54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e93fa39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e93f6e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e93f6e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0542b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0542b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0542b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e93f6e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulq.c (2367 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = mul <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = mul <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = mul <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = fmul <4 x float> %0, %1 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmulq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.m # | ... # `---data was truncated (10240/21288) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b069c3315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b069c300f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b069c3389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc32b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc32b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc32b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc32b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b069bc8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b069bc8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b069badb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b06985d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b06985cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc32b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc32b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc32b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b06985ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --check-prefixes=CHECK,CHECK-NONSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c (2368 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555a3378015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a3377d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a3378089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f315ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f315ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f315ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f315ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a33715e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a33715c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a336fab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a333aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a333a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f315ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f315ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f315ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a333a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c (2369 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556aa9fe515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556aa9fe20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556aa9fe589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1248333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1248333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124831b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556aa9f7ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556aa9f7ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556aa9f5fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556aa9c0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556aa9c0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f124831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556aa9c0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c (2370 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c995fec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c995fe90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c995fec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd7b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd7b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd7b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd7b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c995f81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c995f81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c995f66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c995c160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c995c15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbd7b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd7b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd7b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c995c15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c (2371 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/68133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556f2ce3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556f2ce2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556f2ce3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8027933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f802798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8027933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f802791b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556f2cdc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556f2cdc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556f2cdacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556f2ca5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556f2ca5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f802791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f802791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f802791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556f2ca5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c (2372 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf8_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv1i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf4_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv2i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8mf2_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vxm_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv4i8.i8.i64( %0, %1, i8 %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmerge_vvm_i8m1_tu( %maskedoff, %op1, %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64( %0, %1, %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmerge.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/148020) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005579c3c8a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005579c3c870f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005579c3c8a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71c8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71c898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71c8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71c891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579c3c1fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579c3c1fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579c3c04b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579c38b40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005579c38b3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f71c891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71c891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71c891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005579c38b3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c (2373 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2cl_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2cl.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ff65c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ff65c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ff65c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf9de49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf9dea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf9de49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf9de31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ff655de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ff655dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ff6542b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ff61f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ff61f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf9de32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf9de330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf9de330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ff61f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c (2374 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vsca # | ... # `---data was truncated (10240/15944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056159cee615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056159cee30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056159cee689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7227133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7227133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056159ce7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056159ce7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056159ce60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056159cb100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056159cb0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f722711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056159cb0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c (2375 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.bf16.nxv8bf16.i6 # | ... # `---data was truncated (10240/51694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055642376115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055642375e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055642376189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fafb5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fafb56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fafb5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fafb5631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564236f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005564236f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005564236dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055642338b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055642338add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fafb5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fafb56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fafb56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055642338acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c (2376 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind # | ... # `---data was truncated (10240/68247) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d3f4b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d3f4b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d3f4b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48aff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48aff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48aff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48aff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d3f44ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d3f44cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d3f431b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d3f0e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d3f0e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48aff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48aff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48aff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d3f0e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c (2377 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561ffe84315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561ffe8400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561ffe84389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85dd649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85dd6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85dd649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85dd631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561ffe7d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561ffe7d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561ffe7bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ffe46d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ffe46cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85dd632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85dd6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85dd6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ffe46ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c (2378 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b48b2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b48b2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b48b2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f80d7705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80d775c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f80d7705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f80d76ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b48ac4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b48ac4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b48aa9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b487590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b48758dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f80d76eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80d76ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80d76ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b48758cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c (2379 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056405b4d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056405b4d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056405b4d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3f63449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3f634a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3f63449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3f63431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056405b46ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056405b46cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056405b451b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056405b1010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056405b100dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3f63432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3f634330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3f634330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056405b100cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c (2380 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005616282d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005616282d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005616282d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed49f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed49f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed49f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed49f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056162826ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056162826cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561628251b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561627f010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561627f00dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed49f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed49f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed49f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561627f00cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c (2381 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ffe21f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ffe21f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ffe21f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff46de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff46de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff46de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff46de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ffe218ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ffe218ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ffe216fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ffe1e1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ffe1e1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff46de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff46de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff46de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ffe1e1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c (2382 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf8( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv1i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv2i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv4i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv4i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vx_i8m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmacc.nxv8i8.i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmacc.nxv8i8.i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmacc_vv_i8m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs1.addr, a # | ... # `---data was truncated (10240/207757) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056075d03215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056075d02f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056075d03289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facca91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056075cfc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056075cfc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056075cfacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056075cc5c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056075cc5bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007facca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facca91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056075cc5bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c (2383 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561daeb7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561daeb780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561daeb7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f521f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f521f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f521f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f521f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561daeb10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561daeb10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561daeaf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561dae7a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561dae7a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f521f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f521f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f521f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dae7a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c (2384 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_f16m1x5_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559adb81e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559adb81b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559adb81e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc934c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc934ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc934c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc934c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559adb7b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559adb7b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559adb798b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559adb4480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559adb447dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc934c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc934c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc934c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559adb447cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c (2385 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op # | ... # `---data was truncated (10240/154517) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559cf7d4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559cf7d470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559cf7d4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd967849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd9678a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd967849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd967831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559cf7cdfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559cf7cdfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559cf7cc4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559cf79740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559cf7973dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd967832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd9678330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd9678330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559cf7973cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c (2386 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_i8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf8x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e8_v_u8m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582c800315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582c80000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582c800389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f840cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f840cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f840cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f840cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582c7f98e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582c7f98c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582c7f7db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582c7c2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582c7c2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f840cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f840cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f840cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582c7c2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c (2387 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m4_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16m8_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf4_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadt_vf_f16mf2_tum( %mask, %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load float, ptr %op2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32.i64( %1, %2, float %3, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c (2388 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4debaa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4deba70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4debaa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda3d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda3d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda3d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda3d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4deb3fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a4deb3fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a4deb24b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4de7d40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4de7d3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fda3d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda3d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda3d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4de7d3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c (2389 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align # | ... # `---data was truncated (10240/47596) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7134fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7134f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c7134fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a5d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a5d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a5d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a5d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c71348fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c71348fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c713474b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7131240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c713123dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a5d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a5d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a5d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c713123cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c (2390 of 27911) ******************** TEST 'Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wno-error=return-type -std=c99 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | @X = global i32 0, align 4 # | @Y = global i32 0, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @foo() #0 { # | entry: # | %retval = alloca i32, align 4 # | %i = alloca i32, align 4 # | store i32 0, ptr %i, align 4 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %entry # | %0 = load i32, ptr %i, align 4 # | %cmp = icmp slt i32 %0, 100 # | br i1 %cmp, label %for.body, label %for.end # | # | for.body: ; preds = %for.cond # | br label %for.end # | # | for.inc: ; No predecessors! # | %1 = load i32, ptr %i, align 4 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %i, align 4 # | br label %for.cond # | # | for.end: ; preds = %for.body, %for.cond # | %2 = load i32, ptr %retval, align 4 # | ret i32 %2 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # .---command stderr------------ # | /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/2005-06-15-ExpandGotoInternalProblem.c:13:1: warning: non-void function does not return a value [-Wreturn-type] # | 13 | } # | | ^ # | 1 warning generated. # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -O3 -disable-output # | #0 0x0000561d5e91215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d5e90f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d5e91289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff557b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff557b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff557b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff557b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d5e8a7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d5e8a7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d5e88cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d5e53c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d5e53bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff557b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff557b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff557b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d5e53bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c (2391 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6794e415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6794e10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a6794e489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3e02c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3e02c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3e02c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3e02c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a679479e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a679479c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a67945eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a67910e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a67910ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3e02c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3e02c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3e02c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a67910dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c (2392 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmulh_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | # | ... # `---data was truncated (10240/18925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b988ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b988b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b988ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75ce505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75ce55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75ce505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75ce4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b9884fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b9884fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b98834b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b984e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b984e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f75ce4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75ce4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75ce4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b984e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c (2393 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589bb80115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005589bb7fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005589bb80189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8a7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8a7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8a7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8a7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589bb796e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005589bb796c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005589bb77bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589bb42b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005589bb42add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc8a7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8a7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8a7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589bb42acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c (2394 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c796a815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c796a50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c796a889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5646449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56464a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5646449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5646431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c7963de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c7963dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c79622b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c792d20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c792d1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5646432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56464330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56464330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c792d1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c (2395 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b00e0f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b00e0ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b00e0f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f31649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f316a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f31649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f31631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b00e086e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b00e086c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b00e06bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b00dd1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b00dd1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f31632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f316330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f316330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b00dd1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c (2396 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587d901915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587d90160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587d901989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fbd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fbd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fbd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fbd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587d8faee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587d8faec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587d8f93b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587d8c430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587d8c42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8fbd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fbd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fbd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587d8c42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c (2397 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055911fb8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055911fb880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055911fb8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3890649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38906a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3890649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3890631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055911fb20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055911fb20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055911fb05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055911f7b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055911f7b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3890632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38906330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38906330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055911f7b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c (2398 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560ec7f2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560ec7f1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560ec7f2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa23be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa23bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa23be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa23be31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560ec7eb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560ec7eb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560ec7e9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560ec7b4a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560ec7b49dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa23be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa23be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa23be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560ec7b49cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c (2399 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64ff_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aee8dec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aee8de90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aee8dec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbef5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbef558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbef5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbef551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aee8d81e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aee8d81c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aee8d66b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aee8a160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aee8a15dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbef551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbef551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbef551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aee8a15cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c (2400 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_f16m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32f16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32f16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16_v_i16m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i16.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinli # | ... # `---data was truncated (10240/17403) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619556a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056195569f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619556a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f02ca449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f02ca4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f02ca449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f02ca431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561955637e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561955637c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056195561cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619552cc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619552cbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f02ca432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f02ca4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f02ca4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619552cbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c (2401 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee0f60315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee0f6000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee0f60389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0b3d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0b3d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0b3d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0b3d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee0f598e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee0f598c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee0f57db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee0f22d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee0f22cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0b3d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0b3d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0b3d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee0f22ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c (2402 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564781fd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564781fcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564781fd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2c2f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2c2f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2c2f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2c2f031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564781f67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564781f67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564781f4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564781bfc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564781bfbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2c2f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2c2f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2c2f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564781bfbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c (2403 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16mf2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m1( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m2( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m4( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f16m8( %src, half noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store half %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load half, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv32f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32mf2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv1f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m1( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv2f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m2( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv4f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_f32m4( %src, float noundef %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %value.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store float %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load float, ptr %value.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfslide1up.nxv8f32.f32.i64( poison, %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8f32.f32.i64(, , float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | de # | ... # `---data was truncated (10240/34581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0ce14815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0ce1450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0ce14889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efefeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efefeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efefeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efefeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0ce0dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c0ce0ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c0ce0c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0cdd720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c0cdd71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efefeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efefeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efefeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0cdd71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c (2404 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c (2405 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/62752) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc965f015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc965ed0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc965f089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9cfe933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9cfe98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9cfe933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9cfe91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc96585e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc96585c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc9656ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc9621a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc96219dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9cfe91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9cfe91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9cfe91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc96219cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c (2406 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf4( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16mf2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m1( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vx_i16m2( %vd, i8 noundef signext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmacc.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmacc_vv_i16m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store # | ... # `---data was truncated (10240/79497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9eb82915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9eb8260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9eb82989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d21e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d21ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d21e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d21e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9eb7bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9eb7bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9eb7a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9eb4530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e9eb452dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9d21e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d21e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d21e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9eb452cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c (2407 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf4_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16mf2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m1_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_f16m2_tu( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_f16m4_tu( %vd, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c (2408 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) # # | ... # `---data was truncated (10240/12075) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea039a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea039a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea039a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f39ebe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f39ebea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f39ebe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f39ebe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea0393ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea0393cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea03921b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea035d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea035d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f39ebe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f39ebe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f39ebe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea035d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c (2409 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv1i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v # | ... # `---data was truncated (10240/18520) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056091a3cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056091a3cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056091a3cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f774ff05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f774ff5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f774ff05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f774feed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056091a364e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056091a364c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056091a349b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560919ff90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560919ff8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f774feeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f774feef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f774feef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560919ff8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c (2410 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("risc # | ... # `---data was truncated (10240/11912) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558585d5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558585d580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558585d5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd80a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd80aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd80a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd80a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558585cf0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558585cf0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558585cd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585859850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558585984dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd80a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd80a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd80a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558585984cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c (2411 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | # | ... # `---data was truncated (10240/135119) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1e1cb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1e1cb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1e1cb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d6e849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d6e8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d6e849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d6e831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1e1c4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1e1c4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1e1c30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1e18e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b1e18dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d6e832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d6e8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d6e8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1e18dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c (2412 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %m # | ... # `---data was truncated (10240/160133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c3b3a5a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c3b3a570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c3b3a5a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6b261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6b26725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6b261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6b2603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c3b39efe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c3b39efc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c3b39d4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c3b36840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c3b3683dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc6b2604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6b26050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6b26050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c3b3683cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c (2413 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055949cf9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055949cf940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055949cf9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbe7a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbe7a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbe7a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbe7a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055949cf2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055949cf2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055949cf11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055949cbc10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055949cbc0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbe7a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbe7a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbe7a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055949cbc0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c (2414 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea5423d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea5423a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea5423d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa878449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8784a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa878449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa878431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea541d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea541d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea541b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea53e670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea53e66dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa878432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8784330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8784330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea53e66cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c (2415 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dd6b8c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dd6b890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dd6b8c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b34b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b34b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b34b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b34aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dd6b21e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dd6b21c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dd6b06b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dd67b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dd67b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6b34aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b34aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b34aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dd67b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c (2416 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_i64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_u64m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i64.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse64_v_f64m1_m( %mask, ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca # | ... # `---data was truncated (10240/22898) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f58f0b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f58f0ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f58f0b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad08049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad080a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad08049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad08031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f58f045e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f58f045c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f58f02ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f58ecda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f58ecd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad08032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad080330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad080330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f58ecd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c (2417 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c (2418 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558c6ed3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558c6ed340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558c6ed3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f650c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f650c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f650c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f650c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558c6eccce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558c6ecccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558c6ecb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558c6e9610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558c6e960dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f650c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f650c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f650c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558c6e960cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm64_vcreate.c (2419 of 27911) ******************** TEST 'Clang :: CodeGen/arm64_vcreate.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c" # | target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-apple-ios7" # | # | ; Function Attrs: noinline nounwind optnone # | define <2 x float> @test_vcreate_f32(i64 noundef %a1) #0 { # | entry: # | %a1.addr = alloca i64, align 8 # | %__ret = alloca <2 x float>, align 8 # | %__promote = alloca i64, align 8 # | %tmp = alloca <2 x float>, align 8 # | store i64 %a1, ptr %a1.addr, align 8 # | %0 = load i64, ptr %a1.addr, align 8 # | store i64 %0, ptr %__promote, align 8 # | %1 = load <2 x float>, ptr %__promote, align 8 # | store <2 x float> %1, ptr %__ret, align 8 # | %2 = load <2 x float>, ptr %__ret, align 8 # | store <2 x float> %2, ptr %tmp, align 8 # | %3 = load <2 x float>, ptr %tmp, align 8 # | ret <2 x float> %3 # | } # | # | attributes #0 = { noinline nounwind optnone "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c41e02415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c41e0210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c41e02489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5fd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5fd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5fd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5fd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c41dfb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c41dfb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c41df9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c41dc4e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c41dc4ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb5fd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5fd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5fd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c41dc4dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64_vcreate.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c (2420 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s64_f16 = call i64 @llvm.fptosi.sat.i64.f16(half %1) # | store i64 %vcvth_s64_f16, ptr %ref.tmp, align 8 # | %2 = load i64, ptr %ref.tmp, align 8 # | store i64 %2, ptr %__ret, align 8 # | %3 = load i64, ptr %__ret, align 8 # | store i64 %3, ptr %tmp, align 8 # | %4 = load i64, ptr %tmp, align 8 # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.fptosi.sat.i64.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_u16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | st # | ... # `---data was truncated (10240/53064) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e10ef4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e10ef4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e10ef4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37db133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37db18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37db133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37db11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e10eee3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e10eee3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e10eec8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e10eb780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e10eb77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37db11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37db11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37db11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e10eb77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c (2421 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/16424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056414789515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005641478920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056414789589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7588733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f758878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7588733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f758871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056414782ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056414782ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056414780fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641474bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641474bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f758871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f758871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f758871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641474becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c (2422 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmulh.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmulh_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load i64, ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmulh.mask.nxv1i64.i64.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c (2423 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5(ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056351482a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005635148270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056351482a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd6a305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd6a35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd6a305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd6a2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005635147bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005635147bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005635147a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635144540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563514453dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd6a2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd6a2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd6a2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563514453cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c (2424 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_f32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_i32m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32mf2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e32_v_u32m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("ris # | ... # `---data was truncated (10240/26965) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561716d6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561716d640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561716d6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1245133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f124518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1245133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f124511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561716cfce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561716cfcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561716ce1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005617169910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561716990dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f124511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f124511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f124511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561716990cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c (2425 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.maxnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559feef9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559feef980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559feef9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d58249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d582a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d58249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d58231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559feef30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559feef30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559feef15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559feebc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559feebc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d58232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d582330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d582330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559feebc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c (2426 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloc # | ... # `---data was truncated (10240/27533) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055979e8de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055979e8db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055979e8de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a0a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a0a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a0a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a0a231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055979e873e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055979e873c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055979e858b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055979e5080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055979e507dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8a0a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a0a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a0a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055979e507cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c (2427 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557956c2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557956c1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557956c2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8207849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82078a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8207849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8207831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557956bb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557956bb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557956b9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055795684c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055795684bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8207832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82078330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82078330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055795684bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c (2428 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16f32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i32.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %bas # | ... # `---data was truncated (10240/60209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0250ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0250aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0250ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ef0249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ef02a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ef0249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ef0231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c025042e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c025042c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c025027b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c024cd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c024cd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ef0232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ef02330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ef02330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c024cd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c (2429 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m4_u16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m8_u16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf4_u16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16mf2_u16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m1_u16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfclass.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_bf16m2_u16m2_tum( %vm, %vd, %vs2, i64 nounde # | ... # `---data was truncated (10240/26592) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056247798715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624779840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056247798789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056247791ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056247791cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562477901b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624775b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624775b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bc811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624775b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c (2430 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c (2431 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a239f5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a239f530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a239f5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cf0733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cf078a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cf0733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cf071b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a239eebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a239eebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a239ed0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a239b800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a239b7fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3cf071cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cf071d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cf071d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a239b7fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c (2432 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e264ba515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e264ba20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e264ba589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83b6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83b6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83b6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83b6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e264b3ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e264b3ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e264b1fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e2647cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e2647cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f83b6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83b6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83b6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2647cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c (2433 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588b58b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588b58b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588b58b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ac3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ac338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ac3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ac331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588b584be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588b584bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588b5830b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588b54e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588b54dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ac331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ac331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ac331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588b54dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c (2434 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_asrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.asrl(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.asrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_lsll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %3, i32 %2, i32 %4) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqrshr(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.sqrshr(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqrshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqrshrl(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqrshrl_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.sqrshrl(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_sqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.sqshl(i32 %0, i32 2) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.sqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_sqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.sqshll(i32 %3, i32 %2, i32 17) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.sqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_srshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.srshr(i32 %0, i32 6) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.srshr(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_srshrl(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.srshrl(i32 %3, i32 %2, i32 26) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.srshrl(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqrshl(i32 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | %shift.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = load i32, ptr %shift.addr, align 4 # | %2 = call i32 @llvm.arm.mve.uqrshl(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqrshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 64) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqrshll(i32, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqrshll_sat48(i64 noundef %value, i32 noundef %shift) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | %shift.addr = alloca i32, align 4 # | store i64 %value, ptr %value.addr, align 8 # | store i32 %shift, ptr %shift.addr, align 4 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = load i32, ptr %shift.addr, align 4 # | %5 = call { i32, i32 } @llvm.arm.mve.uqrshll(i32 %3, i32 %2, i32 %4, i32 48) # | %6 = extractvalue { i32, i32 } %5, 1 # | %7 = zext i32 %6 to i64 # | %8 = shl i64 %7, 32 # | %9 = extractvalue { i32, i32 } %5, 0 # | %10 = zext i32 %9 to i64 # | %11 = or i64 %8, %10 # | ret i64 %11 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_uqshl(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.uqshl(i32 %0, i32 21) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.uqshl(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_uqshll(i64 noundef %value) #0 { # | entry: # | %value.addr = alloca i64, align 8 # | store i64 %value, ptr %value.addr, align 8 # | %0 = load i64, ptr %value.addr, align 8 # | %1 = lshr i64 %0, 32 # | %2 = trunc i64 %1 to i32 # | %3 = trunc i64 %0 to i32 # | %4 = call { i32, i32 } @llvm.arm.mve.uqshll(i32 %3, i32 %2, i32 16) # | %5 = extractvalue { i32, i32 } %4, 1 # | %6 = zext i32 %5 to i64 # | %7 = shl i64 %6, 32 # | %8 = extractvalue { i32, i32 } %4, 0 # | %9 = zext i32 %8 to i64 # | %10 = or i64 %7, %9 # | ret i64 %10 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { i32, i32 } @llvm.arm.mve.uqshll(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_urshr(i32 noundef %value) #0 { # | entry: # | %value.addr = alloca i32, align 4 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load i32, ptr %value.addr, align 4 # | %1 = call i32 @llvm.arm.mve.urshr(i32 %0, i32 22) # | ret i32 %1 # | } # | # | ; Function Attrs: nocallback nofree nos # | ... # `---data was truncated (10240/11578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587cef4015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587cef3d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587cef4089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f463db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f463db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f463db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587ceed5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587ceed5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587ceebab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587ceb6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587ceb69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f463db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f463db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f463db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587ceb69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c (2435 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv1bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv1bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16mf2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv2bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv2bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m1_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv4bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv4bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m2_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv8bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv8bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m4_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv16bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv16bf16() #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local bfloat @test_vfmv_f_s_bf16m8_bf16( %src) #0 { # | entry: # | %src.addr = alloca , align 2 # | store %src, ptr %src.addr, align 2 # | %0 = load , ptr %src.addr, align 2 # | %1 = call bfloat @llvm.riscv.vfmv.f.s.nxv32bf16( %0) # | ret bfloat %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare bfloat @llvm.riscv.vfmv.f.s.nxv32bf16() #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed165d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed165d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed165d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd481533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd48158a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd481533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd48151b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed1656ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed1656cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed16551b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed162010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed16200dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd48151cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd48151d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd48151d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed16200cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c (2436 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd # | ... # `---data was truncated (10240/110070) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c71aba915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c71aba60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c71aba989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a08a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a08aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a08a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a08a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c71ab3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c71ab3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c71ab23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c71a7d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c71a7d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a08a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a08a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a08a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c71a7d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c (2437 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv64i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv64i8.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i8.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.a # | ... # `---data was truncated (10240/63518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609348da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609348d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609348da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff86d649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff86d6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff86d649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff86d631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056093486fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056093486fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560934854b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609345040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560934503dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff86d632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff86d6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff86d6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560934503cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c (2438 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/69980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5f5e0215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5f5dff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b5f5e0289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa550933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa55098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa550933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa55091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5f5d97e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b5f5d97c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5f5d7cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5f5a2c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b5f5a2bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa55091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa55091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa55091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5f5a2bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c (2439 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ... # `---data was truncated (10240/14904) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608bfcf915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005608bfcf60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005608bfcf989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61e6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61e6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61e6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61e6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608bfc8ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005608bfc8ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005608bfc73b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005608bf9230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005608bf922dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61e6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61e6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61e6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608bf922cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c (2440 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv1i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1ca87415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e1ca8710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e1ca87489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4c7a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4c7aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4c7a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4c7a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1ca809e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e1ca809c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1ca7eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1ca49e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1ca49ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4c7a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4c7a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4c7a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1ca49dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c (2441 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558aaf59f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558aaf59c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558aaf59f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facbf533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facbf58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facbf533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facbf51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558aaf534e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558aaf534c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558aaf519b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558aaf1c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558aaf1c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007facbf51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facbf51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facbf51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558aaf1c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c (2442 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf4( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16mf2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m1( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_f16m2( %vd, half noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store half %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load half, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8f16.f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8f16.f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_f16m4( %vd, %vs1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c (2443 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, ali # | ... # `---data was truncated (10240/33772) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c878ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c878ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c878ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb610705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb61075c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb610705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6106ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c87843e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c87843c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c87828b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c874d80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c874d7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6106eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6106ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6106ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c874d7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c (2444 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32mf2x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_u32m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055edd55d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055edd55d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055edd55d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bf3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bf398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bf3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bf391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055edd556ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055edd556cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055edd5551b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055edd52010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055edd5200dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bf391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bf391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bf391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055edd5200cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c (2445 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf4x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f16m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32mf2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f32m2x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_f64m1x3(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0. # | ... # `---data was truncated (10240/82975) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005563f5f7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005563f5f6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005563f5f7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa9cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa9cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa9cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa9cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563f5f06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005563f5f06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005563f5eebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005563f5b9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005563f5b9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa9cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa9cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa9cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005563f5b9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c (2446 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4e # | ... # `---data was truncated (10240/216250) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e1c45c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e1c45c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e1c45c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3962f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3962f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3962f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3962f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e1c455de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e1c455dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1c4542b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1c41f20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1c41f1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3962f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3962f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3962f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1c41f1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c (2447 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ab8be7715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ab8be740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ab8be7789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc200a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc200aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc200a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc200a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ab8be0ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ab8be0cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ab8bdf1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ab8baa10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ab8baa0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc200a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc200a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc200a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ab8baa0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c (2448 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e7eff8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e7eff8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e7eff8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab2d81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab2d8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab2d81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab2d803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e7eff24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e7eff24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e7eff09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e7efbb90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e7efbb8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab2d804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab2d8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab2d8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e7efbb8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c (2449 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_u32m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 # | ... # `---data was truncated (10240/14010) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055859666a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585966670f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055859666a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1296905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f129695c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1296905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12968ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585965ffe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585965ffc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585965e4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585962940b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558596293dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f12968eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12968ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12968ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558596293cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/builtins-loongarch.c (2450 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-loongarch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple loongarch32 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "loongarch32" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 4, ptr %res, align 4 # | store volatile i32 5, ptr %res, align 4 # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit" } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"target-abi", !"ilp32d"} # | !1 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b62895815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6289550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b62895889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff564533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff564533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56451b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6288ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6288edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6288d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6285820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b628581dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff56451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b628581cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-loongarch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c (2451 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8i64.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8i64.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.ad # | ... # `---data was truncated (10240/13903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629d76d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629d76d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005629d76d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0596a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0596aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0596a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0596a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629d7668e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005629d7668c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005629d764db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629d72fd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629d72fcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0596a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0596a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0596a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629d72fccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c (2452 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv2i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv4i8_7t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056312c6a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056312c6a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056312c6a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f98133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f9818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f98133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f9811b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056312c63ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056312c63cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056312c621b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056312c2d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056312c2d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f9811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f9811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f9811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056312c2d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c (2453 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16>, <8 x i16>, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32>, <4 x i32>, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmladhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 0) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmladhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 0) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmladhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 0) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 0, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 0, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmlsdhxq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 1, i32 0, i32 1) # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmlsdhxq_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %inactive.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call <8 x i16> @llvm.arm.mve.vqdmlad.v8i16(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2, i32 1, i32 0, i32 1) # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmlsdhxq_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %inactive.addr, align 8 # | %1 = load <4 x i32>, ptr %a.addr, align 8 # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = call <4 x i32> @llvm.arm.mve.vqdmlad.v4i32(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, i32 1, i32 0, i32 1) # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqrdmladhq_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call <16 x i8> @llvm.arm.mve.vqdmlad.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2, i32 0, i32 1, i32 0) # | r # | ... # `---data was truncated (10240/43005) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056215bc1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056215bc0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056215bc1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1d281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1d28725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1d281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1d2803507 abort ./stdlib/abort.c:85:3 # | #7 0x000056215bba5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056215bba5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056215bb8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056215b83a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056215b839dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1d2804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1d28050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1d28050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056215b839cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmlad.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp (2454 of 27911) ******************** TEST 'Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -O1 -disable-llvm-passes -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp -o - -triple=x86_64-linux-gnu # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | declare noundef zeroext i1 @_Z1av() #1 # | # | declare noundef zeroext i1 @_Z1bv() #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.expect.i64(i64, i64) #2 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2alRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | %call.expval = call i1 @llvm.expect.i1(i1 %call, i1 true) # | br i1 %call.expval, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | %call1.expval = call i1 @llvm.expect.i1(i1 %call1, i1 true) # | br i1 %call1.expval, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i1 @llvm.expect.i1(i1, i1) #2 # | # | declare noundef zeroext i1 @_Z1cv() #1 # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ab0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %land.end # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.rhs, label %land.end # | # | land.rhs: ; preds = %land.lhs.true # | %call2 = call noundef zeroext i1 @_Z1cv() # | br label %land.end # | # | land.end: ; preds = %land.rhs, %land.lhs.true, %entry # | %0 = phi i1 [ false, %land.lhs.true ], [ false, %entry ], [ %call2, %land.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 0) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %land.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %inc = add nsw i32 %2, 1 # | store i32 %inc, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.end # | %3 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %4 = load i32, ptr %3, align 4, !tbaa !11 # | %dec = add nsw i32 %4, -1 # | store i32 %dec, ptr %3, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2auRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %land.lhs.true, label %if.else # | # | land.lhs.true: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %land.lhs.true2, label %if.else # | # | land.lhs.true2: ; preds = %land.lhs.true # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 false) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %land.lhs.true2 # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %1 = load i32, ptr %0, align 4, !tbaa !11 # | %inc = add nsw i32 %1, 1 # | store i32 %inc, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %land.lhs.true2, %land.lhs.true, %entry # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob1Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: ; preds = %lor.lhs.false # | %call2 = call noundef zeroext i1 @_Z1av() # | br label %lor.end # | # | lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry # | %0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %call2, %lor.rhs ] # | %conv = zext i1 %0 to i64 # | %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) # | %tobool = icmp ne i64 %expval, 0 # | br i1 %tobool, label %if.then, label %if.else # | # | if.then: ; preds = %lor.end # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.end # | %2 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %3 = load i32, ptr %2, align 4, !tbaa !11 # | %dec = add nsw i32 %3, -1 # | store i32 %dec, ptr %2, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z2olRi(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %if.then, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %if.then, label %lor.lhs.false2 # | # | lor.lhs.false2: ; preds = %lor.lhs.false # | %call3 = call noundef zeroext i1 @_Z1cv() # | %call3.expval = call i1 @llvm.expect.i1(i1 %call3, i1 true) # | br i1 %call3.expval, label %if.then, label %if.else # | # | if.then: ; preds = %lor.lhs.false2, %lor.lhs.false, %entry # | %0 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | store i32 0, ptr %0, align 4, !tbaa !11 # | br label %if.end # | # | if.else: ; preds = %lor.lhs.false2 # | %1 = load ptr, ptr %i.addr, align 8, !tbaa !6, !nonnull !9, !align !10 # | %2 = load i32, ptr %1, align 4, !tbaa !11 # | %dec = add nsw i32 %2, -1 # | store i32 %dec, ptr %1, align 4, !tbaa !11 # | br label %if.end # | # | if.end: ; preds = %if.else, %if.then # | ret void # | } # | # | ; Function Attrs: mustprogress nounwind # | define dso_local void @_Z3ob0Ri(ptr noundef nonnull align 4 dereferenceable(4) %i) #0 { # | entry: # | %i.addr = alloca ptr, align 8 # | store ptr %i, ptr %i.addr, align 8, !tbaa !6 # | %call = call noundef zeroext i1 @_Z1av() # | br i1 %call, label %lor.end, label %lor.lhs.false # | # | lor.lhs.false: ; preds = %entry # | %call1 = call noundef zeroext i1 @_Z1bv() # | br i1 %call1, label %lor.end, label %lor.rhs # | # | lor.rhs: # | ... # `---data was truncated (10240/28468) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=lower-expect -S # | #0 0x000055ccc620315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ccc62000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ccc620389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f73a3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f73a3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f73a3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f73a3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccc6198e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ccc6198c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ccc617db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ccc5e2d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ccc5e2cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f73a3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f73a3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f73a3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccc5e2ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c (2455 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vceqzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oeq half %1, 0.000000e+00 # | %vceqz = sext i1 %2 to i16 # | store i16 %vceqz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp oge half %1, 0.000000e+00 # | %vcgez = sext i1 %2 to i16 # | store i16 %vcgez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcgtzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ogt half %1, 0.000000e+00 # | %vcgtz = sext i1 %2 to i16 # | store i16 %vcgtz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vclezh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp ole half %1, 0.000000e+00 # | %vclez = sext i1 %2 to i16 # | store i16 %vclez, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcltzh_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %2 = fcmp olt half %1, 0.000000e+00 # | %vcltz = sext i1 %2 to i16 # | store i16 %vcltz, ptr %ref.tmp, align 2 # | %3 = load i16, ptr %ref.tmp, align 2 # | store i16 %3, ptr %__ret, align 2 # | %4 = load i16, ptr %__ret, align 2 # | store i16 %4, ptr %tmp, align 2 # | %5 = load i16, ptr %tmp, align 2 # | ret i16 %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = sitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = sitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_s64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = sitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u16(i16 noundef %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca i16, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | store i16 %0, ptr %__s0, align 2 # | %1 = load i16, ptr %__s0, align 2 # | %2 = uitofp i16 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %__ret = alloca half, align 2 # | %__s0 = alloca i32, align 4 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | store i32 %0, ptr %__s0, align 4 # | %1 = load i32, ptr %__s0, align 4 # | %2 = uitofp i32 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_vcvth_f16_u64(i64 noundef %a) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %__ret = alloca half, align 2 # | %__s0 = alloca i64, align 8 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store i64 %a, ptr %a.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | store i64 %0, ptr %__s0, align 8 # | %1 = load i64, ptr %__s0, align 8 # | %2 = uitofp i64 %1 to half # | store half %2, ptr %ref.tmp, align 2 # | %3 = load half, ptr %ref.tmp, align 2 # | store half %3, ptr %__ret, align 2 # | %4 = load half, ptr %__ret, align 2 # | store half %4, ptr %tmp, align 2 # | %5 = load half, ptr %tmp, align 2 # | ret half %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i16 @test_vcvth_s16_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i16, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i16, align 2 # | %tmp = alloca i16, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s16_f16 = call i16 @llvm.fptosi.sat.i16.f16(half %1) # | store i16 %vcvth_s16_f16, ptr %ref.tmp, align 2 # | %2 = load i16, ptr %ref.tmp, align 2 # | store i16 %2, ptr %__ret, align 2 # | %3 = load i16, ptr %__ret, align 2 # | store i16 %3, ptr %tmp, align 2 # | %4 = load i16, ptr %tmp, align 2 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i16 @llvm.fptosi.sat.i16.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_vcvth_s32_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i32, align 4 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i32, align 4 # | %tmp = alloca i32, align 4 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vcvth_s32_f16 = call i32 @llvm.fptosi.sat.i32.f16(half %1) # | store i32 %vcvth_s32_f16, ptr %ref.tmp, align 4 # | %2 = load i32, ptr %ref.tmp, align 4 # | store i32 %2, ptr %__ret, align 4 # | %3 = load i32, ptr %__ret, align 4 # | store i32 %3, ptr %tmp, align 4 # | %4 = load i32, ptr %tmp, align 4 # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.fptosi.sat.i32.f16(half) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_vcvth_s64_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca i64, align 8 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca i64, align 8 # | %tmp = alloca i64, align 8 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, al # | ... # `---data was truncated (10240/28866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df460dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df460d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df460dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc02b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc02b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc02b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc02b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df46071e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df46071c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df46056b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df45d060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df45d05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc02b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc02b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc02b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df45d05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c (2456 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_ran # | ... # `---data was truncated (10240/10777) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564e73fa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564e73fa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564e73fa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee92933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee9298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee92933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee9291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564e73f3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564e73f3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564e73f21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564e73bd10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564e73bd0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fee9291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee9291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee9291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564e73bd0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c (2457 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f91187715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f9118740f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f91187789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f015f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f015f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f015f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f015f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f91180ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f91180cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f9117f1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f9114a10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f9114a0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f015f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f015f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f015f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f9114a0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c (2458 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e5m2_w4_f8e4m3m8_f8e5m2m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e5m2.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653456dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653456da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653456dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc000849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0008a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc000849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc000831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565345672e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565345672c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565345657b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653453070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565345306dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc000832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0008330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0008330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565345306cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmovn.c (2459 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmovn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = shufflevector <16 x i8> %1, <16 x i8> poison, <16 x i32> # | %3 = bitcast <16 x i8> %2 to <8 x i16> # | %4 = shufflevector <8 x i16> %0, <8 x i16> %3, <16 x i32> # | %5 = trunc <16 x i16> %4 to <16 x i8> # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load <8 x i16>, ptr %a.addr, align 8 # | %2 = shufflevector <8 x i16> %1, <8 x i16> poison, <8 x i32> # | %3 = bitcast <8 x i16> %2 to <4 x i32> # | %4 = shufflevector <4 x i32> %0, <4 x i32> %3, <8 x i32> # | %5 = trunc <8 x i32> %4 to <8 x i16> # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_s16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_s32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_u16(<16 x i8> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = bitcast <16 x i8> %0 to <8 x i16> # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = shufflevector <8 x i16> %1, <8 x i16> %2, <16 x i32> # | %4 = trunc <16 x i16> %3 to <16 x i8> # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovntq_u32(<8 x i16> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = bitcast <8 x i16> %0 to <4 x i32> # | %2 = load <4 x i32>, ptr %b.addr, align 8 # | %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> # | %4 = trunc <8 x i32> %3 to <8 x i16> # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_s32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovnbq_m_u16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %0, <8 x i16> %1, i32 0, <8 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmovnbq_m_u32(<8 x i16> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %0, <4 x i32> %1, i32 0, <4 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmovntq_m_s16(<16 x i8> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, a # | ... # `---data was truncated (10240/13410) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf1019315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf101900f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf1019389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4facc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4facca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4facc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4facc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf10128e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf10128c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf1010db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf0fdbd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf0fdbcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4facc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4facc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4facc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf0fdbccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=LE /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmovn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c (2460 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = all # | ... # `---data was truncated (10240/41587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d0add415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d0add10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d0add489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94ec649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94ec6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94ec649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94ec631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d0ad69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d0ad69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d0ad4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d0a9fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d0a9fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f94ec632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94ec6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94ec6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d0a9fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c (2461 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmacc_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv. # | ... # `---data was truncated (10240/51804) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567b27a315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567b27a00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567b27a389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faed201bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faed20725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faed201ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faed2003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567b2738e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567b2738c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567b271db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567b23cd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005567b23ccdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faed2004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faed20050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faed20050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567b23cccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c (2462 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv2i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 4) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d06360715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d0636040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d06360789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbcc8a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbcc8aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbcc8a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbcc8a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d06359ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d06359cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d063581b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d0632310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d063230dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbcc8a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbcc8a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbcc8a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d063230cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c (2463 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e95f97815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e95f9750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e95f97889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe37c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe37c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe37c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe37c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e95f90de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e95f90dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e95f8f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e95f5a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e95f5a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe37c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe37c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe37c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e95f5a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c (2464 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fc1f84c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fc1f8490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fc1f84c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007facc7e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007facc7e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007facc7e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007facc7e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fc1f7e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fc1f7e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fc1f7c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fc1f4760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fc1f475dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007facc7e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007facc7e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007facc7e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fc1f475cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmldav.c (2465 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmldav.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmladavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 1, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load <4 x i32>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %0, <4 x i32> %1, <4 x i32> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s8(i32 noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <16 x i8>, align 8 # | %c.addr = alloca <16 x i8>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store <16 x i8> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load <16 x i8>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 1, i32 %0, <16 x i8> %1, <16 x i8> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s16(i32 noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <8 x i16>, align 8 # | %c.addr = alloca <8 x i16>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store <8 x i16> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load <8 x i16>, ptr %c.addr, align 8 # | %3 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 1, i32 %0, <8 x i16> %1, <8 x i16> %2) # | ret i32 %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmlsdavaxq_s32(i32 noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | %c.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store <4 x i32> %c, ptr %c.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr # | ... # `---data was truncated (10240/44315) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x00005604b06b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604b06b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604b06b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fe9505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fe955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fe9505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fe94ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604b064be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604b064bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604b0630b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604b02e00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604b02dfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4fe94eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fe94ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fe94ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604b02dfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c (2466 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64_v_f64m2x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557239c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557239c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557239c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fecbea1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fecbea725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fecbea1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fecbea03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055572395be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055572395bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555723940b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557235f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557235efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fecbea04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fecbea050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fecbea050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557235efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c (2467 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_f64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste64.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_i64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste64_u64(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste64.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633a852915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633a85260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633a852989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8674333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f867438a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8674333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f867431b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633a84bee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633a84bec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633a84a3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633a81530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633a8152dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f867431cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f867431d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f867431d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633a8152cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c (2468 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650bb69515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650bb6920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650bb69589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9015133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f901518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9015133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f901511b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650bb62ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650bb62ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650bb60fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650bb2bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650bb2bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f901511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f901511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f901511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650bb2becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c (2469 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4171ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c4171aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c4171ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13a5f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13a5f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13a5f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13a5f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c417142e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c417142c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c417127b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c416dd70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c416dd6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f13a5f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13a5f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13a5f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c416dd6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c (2470 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056038325815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603832550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056038325889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5090b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5090b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5090b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5090b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005603831ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005603831edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603831d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560382e820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560382e81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5090b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5090b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5090b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560382e81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c (2471 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m1x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32m2x3(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 # | ... # `---data was truncated (10240/24072) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f69b18715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f69b1840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f69b18789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff14b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff14b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff14b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff14b631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f69b11ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f69b11cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f69b101b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f69adb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f69adb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff14b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff14b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff14b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f69adb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c (2472 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Functio # | ... # `---data was truncated (10240/13657) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556aa618b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556aa61880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556aa618b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f467c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f467c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f467c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f467c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556aa6120e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556aa6120c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556aa6105b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556aa5db50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556aa5db4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f467c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f467c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f467c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556aa5db4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c (2473 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf4_b64( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16mf2_b32( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m1_b16( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m2_b8( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_f16m4_b4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16f16.f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16f16.f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_f16m8_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/66565) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2ae7e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2ae7e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2ae7e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b50f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b50f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b50f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b50f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2ae778e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a2ae778c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2ae75db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2ae40d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2ae40cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b50f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b50f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b50f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2ae40ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c (2474 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f3635b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f363580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f3635b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f13d5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13d5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f13d5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f13d5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f362f0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f362f0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f362d5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f35f850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f35f84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f13d5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13d5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13d5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f35f84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c (2475 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32bf16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64( %3, ptr %1, i64 %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c (2476 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aba794215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aba793f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aba794289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f491da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f491daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f491da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f491da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aba78d7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aba78d7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aba78bcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aba756c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aba756bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f491da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f491da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f491da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aba756bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c (2477 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv1i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv1i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv2i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv2i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv4i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv4i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv8i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv8i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssra_vx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vssra.nxv16i8.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssra.nxv16i8.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function # | ... # `---data was truncated (10240/100281) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056420bb8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056420bb8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056420bb8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f923e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f923e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f923e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f923e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056420bb23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056420bb23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056420bb08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056420b7b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056420b7b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f923e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f923e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f923e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056420b7b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c (2478 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfne.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c (2479 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d0bafd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d0bafa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d0bafd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4c2933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4c298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4c2933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4c291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d0ba92e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d0ba92c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d0ba77b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d0b7270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d0b726dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4c291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4c291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4c291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d0b726cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c (2480 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8bf16.nxv8f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16bf16.nxv16f32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vs # | ... # `---data was truncated (10240/10886) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e0570215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e056ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e0570289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcedf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcedf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcedf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcedf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e05697e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e05697c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e0567cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e0532c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e0532bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdcedf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcedf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcedf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e0532bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c (2481 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_bf16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32bf16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32f16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16f32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8f64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_i64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u8m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u16m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv32i16.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u32m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv16i32.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_u64m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv8i64.i64(i64 %0, %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_vtmv_t_v_f8e4m3m8(i64 noundef %tss, %src, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %src.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store %src, ptr %src.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load , ptr %src.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vtmv.t.v.nxv64i8.i64(i64 %0, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c (2482 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define d # | ... # `---data was truncated (10240/12208) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b59f71015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b59f70d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b59f71089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f76049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f760a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f76049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f76031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b59f6a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b59f6a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b59f68ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b59f33a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b59f339dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f76032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f760330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f760330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b59f339cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c (2483 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005646e4c1615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005646e4c130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005646e4c1689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4a1449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4a14a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4a1449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4a1431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005646e4babe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005646e4babc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005646e4b90b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646e48400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005646e483fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4a1432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4a14330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4a14330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005646e483fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c (2484 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function A # | ... # `---data was truncated (10240/30415) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558408fde15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558408fdb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558408fde89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f537c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f537c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f537c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f537c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558408f73e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558408f73c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558408f58b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558408c080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558408c07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f537c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f537c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f537c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558408c07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c (2485 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_i8m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv64i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse8_v_u8m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32i8.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | # | ... # `---data was truncated (10240/25279) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560fc5dcd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560fc5dca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560fc5dcd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f841a905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f841a95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f841a905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f841a8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560fc5d62e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560fc5d62c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560fc5d47b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560fc59f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560fc59f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f841a8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f841a8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f841a8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560fc59f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c (2486 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_u8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8_v_i8mf8x5_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557de8f8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557de8f800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557de8f8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed62649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed626a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed62649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed62631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557de8f18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557de8f18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557de8efdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557de8bad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557de8bacdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed62632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed626330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed626330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557de8baccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c (2487 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a339b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a339af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a339b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c55a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c55aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c55a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c55a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a33947e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a33947c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a3392cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a335dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a335dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c55a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c55a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c55a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a335dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c (2488 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624a51ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624a51e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624a51ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ebf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ebf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ebf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ebf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624a517fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624a517fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624a5164b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624a4e140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624a4e13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ebf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ebf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ebf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624a4e13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c (2489 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da2a45815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da2a4550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da2a45889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb16d41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb16d4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb16d41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb16d403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da2a3ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da2a3edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da2a3d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da2a0820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da2a081dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb16d404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb16d4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb16d4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da2a081cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c (2490 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005590241e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005590241e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005590241e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2faa849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2faa8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2faa849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2faa831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055902417ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055902417ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559024163b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559023e130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559023e12dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2faa832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2faa8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2faa8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559023e12cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c (2491 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf4_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf4_f32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32mf2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16mf2_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_bf16mf2_f32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_bf16_f32m1( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_bf16m1_f32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_bf16m1_f32m2( %vs2, bfloat noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | # | ... # `---data was truncated (10240/86100) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd9978915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd997860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd9978989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb965049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9650a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb965049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb965031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd9971ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd9971ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd99703b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd993b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd993b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb965032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9650330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9650330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd993b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c (2492 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd6b44315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bd6b4400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bd6b44389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f017e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f017e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f017e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f017e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd6b3d8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bd6b3d8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bd6b3bdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bd6b06d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bd6b06cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f017e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f017e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f017e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd6b06ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/cx-complex-range-real.c (2493 of 27911) ******************** TEST 'Clang :: CodeGen/cx-complex-range-real.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c -O0 -disable-O0-optnone -emit-llvm -triple x86_64-unknown-unknown -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulaf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %mul.rl = fmul float %a.real, %0 # | %mul.il = fmul float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.il, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mulassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %mul.rl = fmul float %.real, %0 # | %mul.il = fmul float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %mul.rl, ptr %.realp1, align 4 # | store float %mul.il, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @mulbf(float noundef %a, <2 x float> noundef %b.coerce) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { float, float }, align 4 # | %a.addr = alloca float, align 4 # | store <2 x float> %b.coerce, ptr %b, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | %b.realp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 0 # | %b.real = load float, ptr %b.realp, align 4 # | %b.imagp = getelementptr inbounds nuw { float, float }, ptr %b, i32 0, i32 1 # | %b.imag = load float, ptr %b.imagp, align 4 # | %mul.rl = fmul float %0, %b.real # | %mul.ir = fmul float %0, %b.imag # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %mul.rl, ptr %retval.realp, align 4 # | store float %mul.ir, ptr %retval.imagp, align 4 # | %1 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divf(<2 x float> noundef %a.coerce, float noundef %b) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %a = alloca { float, float }, align 4 # | %b.addr = alloca float, align 4 # | store <2 x float> %a.coerce, ptr %a, align 4 # | store float %b, ptr %b.addr, align 4 # | %a.realp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 0 # | %a.real = load float, ptr %a.realp, align 4 # | %a.imagp = getelementptr inbounds nuw { float, float }, ptr %a, i32 0, i32 1 # | %a.imag = load float, ptr %a.imagp, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = fdiv float %a.real, %0 # | %2 = fdiv float %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %1, ptr %retval.realp, align 4 # | store float %2, ptr %retval.imagp, align 4 # | %3 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignf(ptr noundef %a, float noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca float, align 4 # | store ptr %a, ptr %a.addr, align 8 # | store float %b, ptr %b.addr, align 4 # | %0 = load float, ptr %b.addr, align 4 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.real = load float, ptr %.realp, align 4 # | %.imagp = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | %.imag = load float, ptr %.imagp, align 4 # | %2 = fdiv float %.real, %0 # | %3 = fdiv float %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { float, float }, ptr %1, i32 0, i32 1 # | store float %2, ptr %.realp1, align 4 # | store float %3, ptr %.imagp2, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { double, double } @divd(double noundef %a.coerce0, double noundef %a.coerce1, double noundef %b) #1 { # | entry: # | %retval = alloca { double, double }, align 8 # | %a = alloca { double, double }, align 8 # | %b.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | store double %a.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | store double %a.coerce1, ptr %1, align 8 # | store double %b, ptr %b.addr, align 8 # | %a.realp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 0 # | %a.real = load double, ptr %a.realp, align 8 # | %a.imagp = getelementptr inbounds nuw { double, double }, ptr %a, i32 0, i32 1 # | %a.imag = load double, ptr %a.imagp, align 8 # | %2 = load double, ptr %b.addr, align 8 # | %3 = fdiv double %a.real, %2 # | %4 = fdiv double %a.imag, %2 # | %retval.realp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { double, double }, ptr %retval, i32 0, i32 1 # | store double %3, ptr %retval.realp, align 8 # | store double %4, ptr %retval.imagp, align 8 # | %5 = load { double, double }, ptr %retval, align 8 # | ret { double, double } %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @divbd(double noundef %a, double noundef %b.coerce0, double noundef %b.coerce1) #0 { # | entry: # | %retval = alloca { float, float }, align 4 # | %b = alloca { double, double }, align 8 # | %a.addr = alloca double, align 8 # | %0 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | store double %b.coerce0, ptr %0, align 8 # | %1 = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | store double %b.coerce1, ptr %1, align 8 # | store double %a, ptr %a.addr, align 8 # | %2 = load double, ptr %a.addr, align 8 # | %b.realp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 0 # | %b.real = load double, ptr %b.realp, align 8 # | %b.imagp = getelementptr inbounds nuw { double, double }, ptr %b, i32 0, i32 1 # | %b.imag = load double, ptr %b.imagp, align 8 # | %call = call { double, double } @__divdc3(double noundef %2, double noundef 0.000000e+00, double noundef %b.real, double noundef %b.imag) #2 # | %3 = extractvalue { double, double } %call, 0 # | %4 = extractvalue { double, double } %call, 1 # | %conv = fptrunc double %3 to float # | %conv1 = fptrunc double %4 to float # | %retval.realp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { float, float }, ptr %retval, i32 0, i32 1 # | store float %conv, ptr %retval.realp, align 4 # | store float %conv1, ptr %retval.imagp, align 4 # | %5 = load <2 x float>, ptr %retval, align 4 # | ret <2 x float> %5 # | } # | # | declare { double, double } @__divdc3(double, double, double, double) # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignd(ptr noundef %a, double noundef %b) #1 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca double, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store double %b, ptr %b.addr, align 8 # | %0 = load double, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | %.realp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.real = load double, ptr %.realp, align 8 # | %.imagp = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | %.imag = load double, ptr %.imagp, align 8 # | %2 = fdiv double %.real, %0 # | %3 = fdiv double %.imag, %0 # | %.realp1 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 0 # | %.imagp2 = getelementptr inbounds nuw { double, double }, ptr %1, i32 0, i32 1 # | store double %2, ptr %.realp1, align 8 # | store double %3, ptr %.imagp2, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local { x86_fp80, x86_fp80 } @divld(ptr noundef byval({ x86_fp80, x86_fp80 }) align 16 %a, x86_fp80 noundef %b) #1 { # | entry: # | %retval = alloca { x86_fp80, x86_fp80 }, align 16 # | %b.addr = alloca x86_fp80, align 16 # | store x86_fp80 %b, ptr %b.addr, align 16 # | %a.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 0 # | %a.real = load x86_fp80, ptr %a.realp, align 16 # | %a.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %a, i32 0, i32 1 # | %a.imag = load x86_fp80, ptr %a.imagp, align 16 # | %0 = load x86_fp80, ptr %b.addr, align 16 # | %1 = fdiv x86_fp80 %a.real, %0 # | %2 = fdiv x86_fp80 %a.imag, %0 # | %retval.realp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 0 # | %retval.imagp = getelementptr inbounds nuw { x86_fp80, x86_fp80 }, ptr %retval, i32 0, i32 1 # | store x86_fp80 %1, ptr %retval.realp, align 16 # | store x86_fp80 %2, ptr %retval.imagp, align 16 # | %3 = load { x86_fp80, x86_fp80 }, ptr %retval, align 16 # | ret { x86_fp80, x86_fp80 } %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @divassignld(ptr noundef %a, x86_fp80 noundef %b) #1 { # | entry: # | %a.addr # | ... # `---data was truncated (10240/11567) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055ce26dad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce26daa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce26dad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f78a5a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f78a5aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f78a5a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f78a5a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce26d42e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce26d42c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce26d27b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce269d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce269d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f78a5a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f78a5a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f78a5a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce269d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/cx-complex-range-real.c --check-prefix=FULL # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c (2494 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c (2495 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a02b18d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a02b18a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a02b18d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f81f101bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f81f10725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f81f101ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f81f1003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a02b122e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a02b122c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a02b107b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a02adb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a02adb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f81f1004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f81f10050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f81f10050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a02adb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c (2496 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558239d4315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558239d400f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558239d4389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6f49733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6f4978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6f49733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6f4971b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558239cd8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558239cd8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558239cbdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055823996d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055823996cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6f4971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6f4971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6f4971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055823996ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c (2497 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef # | ... # `---data was truncated (10240/69988) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fdc660215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fdc65ff0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fdc660289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad18505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad1855c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad18505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad184ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fdc6597e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fdc6597c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fdc657cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fdc622c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fdc622bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad184eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad184ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad184ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fdc622bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c (2498 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c (2499 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v # | ... # `---data was truncated (10240/160911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e655b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e655b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e655b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f5ba1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f5ba725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f5ba1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f5ba03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e6554ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e6554cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e65531b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e651e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e651e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5f5ba04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f5ba050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f5ba050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e651e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c (2500 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c (2501 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c (2502 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597bd86915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597bd8660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597bd86989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98aa81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98aa8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98aa81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98aa803507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597bd7fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597bd7fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597bd7e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597bd4930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597bd492dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98aa804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98aa8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98aa8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597bd492cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c (2503 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb8136715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb813640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb8136789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3e7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3e78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3e7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3e7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb812fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb812fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb812e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb80f910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb80f90dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3e7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3e78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3e78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb80f90cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (2504 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vln.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vln8_v_i8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret # | ... # `---data was truncated (10240/29371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643ea6ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643ea6ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643ea6ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f812b533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f812b58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f812b533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f812b51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643ea684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643ea684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643ea669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643ea3190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643ea318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f812b51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f812b51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f812b51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643ea318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c (2505 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8mf2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m1_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m2_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m4_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i8m8_i8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredxor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredxor_vs_i16mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredxor.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretu # | ... # `---data was truncated (10240/113047) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d304ee315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d304ee00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d304ee389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f61f6f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f61f6f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f61f6f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f61f6f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d304e78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d304e78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d304e5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d304b0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d304b0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f61f6f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f61f6f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f61f6f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d304b0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c (2506 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_f32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_i32m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32ff_v_u32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base # | ... # `---data was truncated (10240/60683) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649a21af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005649a21ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005649a21af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc546933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc54698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc546933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc54691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649a2144e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005649a2144c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005649a2129b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649a1dd90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649a1dd8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc54691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc54691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc54691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649a1dd8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c (2507 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei32_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, ali # | ... # `---data was truncated (10240/14621) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005634f75af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005634f75ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005634f75af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9348c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9348ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9348c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9348c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005634f7544e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005634f7544c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005634f7529b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005634f71d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005634f71d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9348c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9348c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9348c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005634f71d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c (2508 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c (2509 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e64_v_i64m2x4_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c (2510 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8mf2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m1( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m2( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m4( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i8m8( %src, i8 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 1 # | %value.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 1 # | store i8 %value, ptr %value.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 1 # | %1 = load i8, ptr %value.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf4( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16mf2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m1( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i16 %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i16, ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslide1down.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslide1down.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vslide1down_vx_i16m2( %src, i16 noundef signext %value, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %value.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c (2511 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ms_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ms.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/12227) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b4ae2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b4ae260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b4ae2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2048b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2048b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2048b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2048b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b4adbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b4adbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b4ada3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b4aa530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b4aa52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2048b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2048b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2048b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b4aa52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c (2512 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2ff30715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e2ff3040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e2ff30789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0588533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f058858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0588533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f058851b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2ff29ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e2ff29cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e2ff281b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e2fef310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e2fef30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f058851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f058851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f058851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2fef30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c (2513 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfne.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfne_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfne.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ee9b2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ee9b230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ee9b2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1bf3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1bf358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1bf3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1bf351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ee9abbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ee9abbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ee9aa0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ee97500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ee974fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1bf351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1bf351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1bf351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ee974fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c (2514 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588af38d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588af38a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588af38d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2706c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2706ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2706c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2706c31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588af322e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588af322c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588af307b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588aefb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588aefb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2706c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2706c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2706c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588aefb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c (2515 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i8m8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf4( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16mf2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m1( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vrsub_vx_i16m2( %op1, i16 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i16, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i16 %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i16, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub # | ... # `---data was truncated (10240/84979) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639db01315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639db0100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639db01389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cede1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cede725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cede1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cede03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639dafa8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639dafa8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639daf8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639dac3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639dac3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4cede04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cede050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cede050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639dac3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c (2516 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8f16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f16m4_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16f16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32mf2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1f32.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m1_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2f32.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m2_tu( %maskedoff, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4f32.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vluxei32_v_f32m4_tu( %maskedoff, ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c (2517 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettk_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562eb922815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562eb92250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562eb922889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a49333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a4938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a49333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a4931b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562eb91bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562eb91bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562eb91a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562eb8e520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562eb8e51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a4931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a4931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a4931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562eb8e51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c (2518 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei64_v_f32m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_v # | ... # `---data was truncated (10240/216258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056397ab7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056397ab6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056397ab7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f768d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f768d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f768d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f768d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056397ab07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056397ab07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056397aaecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056397a79c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056397a79bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f768d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f768d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f768d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056397a79bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c (2519 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv8bf16.nxv8bf16.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c (2520 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056360100d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056360100a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056360100d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f74c2f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74c2f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f74c2f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f74c2eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563600fa2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563600fa2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563600f87b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563600c370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563600c36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f74c2eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74c2eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74c2eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563600c36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c (2521 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc38d6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc38d630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc38d6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f12c7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f12c7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f12c7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f12c7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc38cfbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc38cfbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc38ce0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc389900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc3898fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f12c7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f12c7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f12c7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc3898fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c (2522 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055977bcd215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055977bccf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055977bcd289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef04449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef044a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef04449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef04431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055977bc67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055977bc67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055977bc4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055977b8fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055977b8fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fef04432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef044330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef044330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055977b8fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c (2523 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_f16m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf4x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16mf2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_i16m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055941aa5e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055941aa5b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055941aa5e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f110cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f110cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f110cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f110cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055941a9f3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055941a9f3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055941a9d8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055941a6880b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055941a687dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f110cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f110cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f110cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055941a687cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c (2524 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4f16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8f16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m4(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16f16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f16m8(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32f16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32mf2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1f32.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m1(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2f32.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxei16_v_f32m2(ptr noundef %base, %bindex, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4f32.p0.nxv4i16.i64( %2, ptr %0, %1, i6 # | ... # `---data was truncated (10240/132470) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056210e2be15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056210e2bb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056210e2be89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbde4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbde46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbde4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbde4631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056210e253e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056210e253c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056210e238b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056210dee80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056210dee7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbde4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbde46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbde46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056210dee7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c (2525 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg3ei16_v_f64m1x3(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c (2526 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055974631d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055974631a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055974631d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d74933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d7498a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d74933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d7491b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597462b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597462b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559746297b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559745f470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559745f46dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d7491cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d7491d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d7491d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559745f46cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c (2527 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dbc78815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557dbc7850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557dbc78889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c70049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c700a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c70049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c70031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dbc71de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557dbc71dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557dbc702b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557dbc3b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557dbc3b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c70032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c700330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c700330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dbc3b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c (2528 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b79e3ae15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b79e3ab0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b79e3ae89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f94649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f946a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f94649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f94631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b79e343e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b79e343c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b79e328b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b79dfd80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b79dfd7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f94632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f946330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f946330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b79dfd7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c (2529 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556966f3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556966f3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556966f3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe322905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe32295c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe322905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3228ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556966ed4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556966ed4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556966eb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556966b690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556966b68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe3228eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3228ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3228ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556966b68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c (2530 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564541b6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564541b5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564541b6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbad9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbad98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbad9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbad9831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564541af6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564541af6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564541adbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056454178b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056454178add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbad9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbad98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbad98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056454178acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c (2531 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local targ # | ... # `---data was truncated (10240/70855) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569d727c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569d72790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569d727c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdaa2249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdaa22a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdaa2249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdaa2231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569d7211e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569d7211c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569d71f6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569d6ea60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569d6ea5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdaa2232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdaa22330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdaa22330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569d6ea5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c (2532 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638cefd815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638cefd50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005638cefd889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5965105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f596515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5965105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59650ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638cef6de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638cef6dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638cef52b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638cec020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638cec01dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f59650eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59650ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59650ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638cec01cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c (2533 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ab2b1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ab2b110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ab2b1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe5d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe5d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe5d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe5d6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ab2aa9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ab2aa9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ab2a8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ab273e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ab273ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe5d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe5d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe5d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ab273dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c (2534 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650bacbb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650bacb80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650bacbb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fee7f705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fee7f75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fee7f705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fee7f6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650bac50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650bac50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650bac35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650ba8e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650ba8e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fee7f6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fee7f6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fee7f6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650ba8e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c (2535 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwadd_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, a # | ... # `---data was truncated (10240/151903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6f932515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6f93220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6f932589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f231fc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f231fca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f231fc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f231fc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6f92bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c6f92bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c6f929fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6f8f4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c6f8f4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f231fc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f231fc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f231fc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6f8f4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c (2536 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559265edb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559265ed80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559265edb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc59ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc59eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc59ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc59ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559265e70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559265e70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559265e55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559265b050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559265b04dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc59ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc59ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc59ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559265b04cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c (2537 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccdedc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ccdedc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ccdedc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c32133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c3218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c32133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c3211b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccded5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ccded5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ccded43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ccde9f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ccde9f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c3211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c3211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c3211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccde9f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c (2538 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056135f1ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056135f1eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056135f1ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5471705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f547175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5471705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f54716ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056135f183e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056135f183c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056135f168b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056135ee180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056135ee17dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f54716eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f54716ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f54716ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056135ee17cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c (2539 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 5) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e8m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 6) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e16m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32mf2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 7) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e32m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 2, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m1(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 0) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m2(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m4(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vsetvl_e64m8(i64 noundef %avl) #0 { # | entry: # | %avl.addr = alloca i64, align 8 # | store i64 %avl, ptr %avl.addr, align 8 # | %0 = load i64, ptr %avl.addr, align 8 # | %1 = call i64 @llvm.riscv.vsetvli.i64(i64 %0, i64 3, i64 3) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e5f06015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e5f05d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e5f06089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb3ee733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb3ee78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb3ee733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb3ee71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e5eff5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e5eff5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e5efdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e5ec8a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e5ec89dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb3ee71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb3ee71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb3ee71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e5ec89cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c (2540 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv1i64.nxv1i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv2i64.nxv2i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsha2ch_vv_u64m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsha2ch.nxv4i64.nxv4i64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscal # | ... # `---data was truncated (10240/12235) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560572b2715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560572b240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560572b2789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd28d705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd28d75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd28d705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd28d6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560572abce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560572abcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560572aa1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005605727510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560572750dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd28d6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd28d6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd28d6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560572750cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c (2541 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056554c00b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056554c0080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056554c00b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc041333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc04138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc041333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc04131b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056554bfa0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056554bfa0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056554bf85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056554bc350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056554bc34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc04131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc04131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc04131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056554bc34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c (2542 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055774cb5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055774cb580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055774cb5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a0281bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a028725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a0281ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a02803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055774caf0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055774caf0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055774cad5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055774c7850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055774c784dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4a02804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a028050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a028050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055774c784cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c (2543 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto_backend.ll (2544 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto_backend.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto_backend.ll.tmp1.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto_backend.ll # | #0 0x00005594a579a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005594a57970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005594a579a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8eb8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8eb858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8eb8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8eb851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005594a572fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005594a572fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005594a5714b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005594a53c40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005594a53c3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8eb851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8eb851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8eb851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005594a53c3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c (2545 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnand_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnand.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055986889115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055986888e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055986889189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbf1a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbf1a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbf1a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbf1a031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559868826e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559868826c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055986880bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598684bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005598684badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbf1a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbf1a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbf1a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598684bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c (2546 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredsum.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredsum_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/94371) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569ff65d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569ff65a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569ff65d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f001ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f001eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f001ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f001ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569ff5f2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569ff5f2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569ff5d7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569ff2870b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569ff286dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f001ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f001ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f001ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569ff286cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c (2547 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( # | ... # `---data was truncated (10240/51185) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555858be915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555858be60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555858be989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1a0f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1a0f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1a0f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1a0f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555858b7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555858b7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555858b63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558588130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555858812dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1a0f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1a0f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1a0f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555858812cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGenHIP/offload-pgo-sections.hip (2548 of 27911) ******************** TEST 'Clang :: CodeGenHIP/offload-pgo-sections.hip' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 12 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple amdgpu-amd-amdhsa -fcuda-is-device -cuid=abc -fprofile-instrument=clang -emit-llvm -o - -x hip /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip" # | target datalayout = "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-p10:32:32-p11:32:32-p12:32:32-p13:32:32-p14:32:32-p15:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9" # | target triple = "amdgpu-amd-amdhsa" # | # | $__profc__Z6helperi = comdat any # | # | $__llvm_prf_unifcnt__Z6helperi = comdat any # | # | $__profc__Z6kernelPi = comdat any # | # | $__llvm_prf_unifcnt__Z6kernelPi = comdat any # | # | @__hip_cuid_b04fd23c98500190 = addrspace(1) global i8 0 # | @__profc__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6helperi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6helperi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 6265860958107916728, i64 24, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6helperi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6helperi), align 8 # | @__profc__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 # | @__llvm_prf_unifcnt__Z6kernelPi = linkonce_odr protected addrspace(1) global [1 x i64] zeroinitializer, section "__llvm_prf_ucnts", comdat, align 8 # | @__profd__Z6kernelPi = linkonce_odr protected addrspace(1) global { i64, i64, i64, i64, i64, ptr, ptr, i32, [3 x i16], i16, i32 } { i64 4905896731224577586, i64 0, i64 sub (i64 ptrtoint (ptr addrspace(1) @__profc__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 sub (i64 ptrtoint (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to i64), i64 ptrtoint (ptr addrspace(1) @__profd__Z6kernelPi to i64)), i64 0, ptr null, ptr null, i32 1, [3 x i16] zeroinitializer, i16 0, i32 0 }, section "__llvm_prf_data", comdat($__profc__Z6kernelPi), align 8 # | @__llvm_prf_nm_b04fd23c98500190 = protected addrspace(1) constant [32 x i8] c"\16\1Ex\DA\8B\8F2\CBH\CD)H-\CAd\8C\8F2\CBN-\CAK\CD\09\C8\04\00Z\AD\08\03", section "__llvm_prf_names", align 1 # | @__start___llvm_prf_names = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_names = external hidden addrspace(1) global i8 # | @__start___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_cnts = external hidden addrspace(1) global i8 # | @__start___llvm_prf_data = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_data = external hidden addrspace(1) global i8 # | @__start___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__stop___llvm_prf_ucnts = external hidden addrspace(1) global i8 # | @__llvm_profile_raw_version = external addrspace(1) constant i64 # | @__llvm_profile_sections_b04fd23c98500190 = protected addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) @__start___llvm_prf_names, ptr addrspace(1) @__stop___llvm_prf_names, ptr addrspace(1) @__start___llvm_prf_cnts, ptr addrspace(1) @__stop___llvm_prf_cnts, ptr addrspace(1) @__start___llvm_prf_data, ptr addrspace(1) @__stop___llvm_prf_data, ptr addrspace(1) @__start___llvm_prf_ucnts, ptr addrspace(1) @__stop___llvm_prf_ucnts, ptr addrspace(1) @__llvm_profile_raw_version } # | @llvm.compiler.used = appending addrspace(1) global [6 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_b04fd23c98500190 to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__profd__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_profile_sections_b04fd23c98500190 to ptr)], section "llvm.metadata" # | @llvm.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__llvm_prf_nm_b04fd23c98500190 to ptr)], section "llvm.metadata" # | # | ; Function Attrs: convergent mustprogress noinline nounwind optnone # | define dso_local noundef i32 @_Z6helperi(i32 noundef %x) #0 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6helperi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %x.addr = alloca i32, align 4, addrspace(5) # | %x.addr.ascast = addrspacecast ptr addrspace(5) %x.addr to ptr # | store i32 %x, ptr %x.addr.ascast, align 4 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load i32, ptr %x.addr.ascast, align 4 # | %add = add nsw i32 %1, 1 # | ret i32 %add # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6helperi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6helperi to ptr), i64 1) # | br label %po_cont # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.instrprof.increment(ptr, i64, i32, i32) #1 # | # | ; Function Attrs: convergent mustprogress noinline norecurse nounwind optnone # | define dso_local amdgpu_kernel void @_Z6kernelPi(ptr addrspace(1) noundef %p.coerce) #2 { # | entry: # | %0 = call i32 @llvm.amdgcn.wavefrontsize() # | %wavesize.i16 = trunc i32 %0 to i16 # | store i16 %wavesize.i16, ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @__profd__Z6kernelPi, i64 66), align 2 # | %pgo.sampled = call i32 @__llvm_profile_sampling_gpu(i32 3) # | %pgo.matched = icmp ne i32 %pgo.sampled, 0 # | %p = alloca ptr, align 8, addrspace(5) # | %p.addr = alloca ptr, align 8, addrspace(5) # | %p.addr.ascast = addrspacecast ptr addrspace(5) %p.addr to ptr # | store ptr addrspace(1) %p.coerce, ptr addrspace(5) %p, align 8 # | %p1 = load ptr, ptr addrspace(5) %p, align 8 # | store ptr %p1, ptr %p.addr.ascast, align 8 # | br i1 %pgo.matched, label %po_then, label %po_cont # | # | po_cont: ; preds = %po_then, %entry # | %1 = load ptr, ptr %p.addr.ascast, align 8 # | %2 = load i32, ptr %1, align 4 # | %call = call noundef i32 @_Z6helperi(i32 noundef %2) #4 # | %3 = load ptr, ptr %p.addr.ascast, align 8 # | store i32 %call, ptr %3, align 4 # | ret void # | # | po_then: ; preds = %entry # | call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) @__profc__Z6kernelPi to ptr), ptr addrspacecast (ptr addrspace(1) @__llvm_prf_unifcnt__Z6kernelPi to ptr), i64 1) # | br label %po_cont # | } # | # | declare i32 @__llvm_profile_sampling_gpu(i32) # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #3 # | # | declare void @__llvm_profile_instrument_gpu(ptr, ptr, i64) # | # | attributes #0 = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #1 = { nounwind } # | attributes #2 = { convergent mustprogress noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,1024" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size" } # | attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #4 = { convergent nounwind "uniform-work-group-size" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 2, !"EnableValueProfiling", i32 0} # | !1 = !{i32 1, !"amdhsa_code_object_version", i32 600} # | !2 = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} # | !3 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=instrprof -S # | #0 0x0000557bb59b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557bb59ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557bb59b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11b0449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11b04a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11b0449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11b0431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bb5946e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557bb5946c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557bb592bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557bb55db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557bb55dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11b0432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11b04330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11b04330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bb55dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefix=DEV /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenHIP/offload-pgo-sections.hip # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c (2549 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4cc5c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4cc5bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4cc5c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f798b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f798b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f798b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f798b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a4cc555e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a4cc555c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a4cc53ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a4cc1ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a4cc1e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f798b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f798b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f798b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a4cc1e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c (2550 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmin_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622d70bf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005622d70bc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005622d70bf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbcf61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbcf6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbcf61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbcf603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622d7054e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005622d7054c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005622d7039b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622d6ce90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622d6ce8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbcf604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbcf6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbcf6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622d6ce8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c (2551 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vssub.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vssub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vssub_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c (2552 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609b925915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609b92560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609b925989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38c8533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38c858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38c8533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38c851b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609b91eee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005609b91eec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005609b91d3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609b8e830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609b8e82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f38c851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38c851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38c851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609b8e82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c (2553 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vcompress_vm_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vcompress.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32bf16.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557d172b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557d172b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557d172b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa79e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa79e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa79e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa79e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557d1724be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557d1724bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557d17230b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557d16ee00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557d16edfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa79e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa79e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa79e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557d16edfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c (2554 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056224659c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005622465990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056224659c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f18ef333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f18ef38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f18ef333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f18ef31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562246531e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562246531c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562246516b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622461c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622461c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f18ef31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f18ef31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f18ef31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622461c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c (2555 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_i8m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv32i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf8x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv1i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e8_v_u8mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 nounde # | ... # `---data was truncated (10240/16083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d70f48e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d70f48b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d70f48e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcdda649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcdda6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcdda649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcdda631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d70f423e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d70f423c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d70f408b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d70f0b80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d70f0b7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcdda632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcdda6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcdda6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d70f0b7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c (2556 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b28dc4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b28dc450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b28dc4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4721e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4721e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4721e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4721e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b28dbdde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b28dbddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b28dbc2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b28d8720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b28d871dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4721e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4721e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4721e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b28d871cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c (2557 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | stor # | ... # `---data was truncated (10240/52599) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558459b4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558459b4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558459b4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4104f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4104f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4104f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4104f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558459ae2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558459ae2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558459ac7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005584597770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558459776dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4104f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4104f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4104f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558459776cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c (2558 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcpopv.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vcpop_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vcpopv.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | # | ... # `---data was truncated (10240/40891) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c300c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c300be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c300c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5911d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5911d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5911d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5911d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c30056e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c30056c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c3003bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c2fceb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c2fceadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5911d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5911d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5911d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c2fceacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c (2559 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c (2560 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv1i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv1i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wx_i16mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.w.nxv2i16.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.w.nxv2i16.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_vx_i16m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwadd_wv_i16m1(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c (2561 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv64i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vbrev.nxv32i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noca # | ... # `---data was truncated (10240/40803) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055676bf7815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055676bf750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055676bf7889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb163533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb16358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb163533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb16351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055676bf0de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055676bf0dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055676bef2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055676bba20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055676bba1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb16351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb16351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb16351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055676bba1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c (2562 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl. # | ... # `---data was truncated (10240/24951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ce5c2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ce5c260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ce5c2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67ca133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67ca18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67ca133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67ca11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ce5bbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ce5bbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ce5ba3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ce58530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ce5852dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f67ca11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67ca11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67ca11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ce5852cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c (2563 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a438ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a438ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a438ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb7a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb7a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb7a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb7a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a43882e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a43882c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a43867b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a435170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a43516dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb7a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb7a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb7a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a43516cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c (2564 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei32_v_f32m2x2(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c (2565 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055888078215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055888077f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055888078289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2891e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2891ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2891e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2891e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558880717e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558880717c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588806fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588803ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588803abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2891e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2891e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2891e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588803abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c (2566 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005629b38c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005629b38bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005629b38c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa252133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa25218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa252133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa25211b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005629b3857e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005629b3857c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005629b383cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005629b34ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005629b34ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa25211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa25211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa25211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005629b34ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c (2567 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6d4d5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6d4d590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6d4d5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c4b733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c4b78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c4b733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c4b71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6d4cf1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6d4cf1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6d4cd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6d49860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6d4985dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c4b71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c4b71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c4b71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6d4985cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c (2568 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjx_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjx.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e86eaa715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e86eaa40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e86eaa789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f936b449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f936b4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f936b449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f936b431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e86ea3ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e86ea3cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e86ea21b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e86e6d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e86e6d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f936b432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f936b4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f936b4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e86e6d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c (2569 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m1_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv8i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m2_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv16i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_i8m4_i8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv32i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv64i8.nxv32i8(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m2( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m4( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv32i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m1_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv8i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m2_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store i64 %index, ptr %index.addr, align 8 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv64i8.nxv16i8( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vset_v_u8m4_u8m8( %dest, i64 noundef %index, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %index.addr = alloca i64, align 8 # | %val.addr = alloca , align 1 # | store %dest, p # | ... # `---data was truncated (10240/54546) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005605bbb5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005605bbb550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005605bbb5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5bc5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5bc578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5bc5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5bc571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005605bbaede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005605bbaedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005605bbad2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005605bb7820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005605bb781dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5bc571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5bc571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5bc571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005605bb781cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c (2570 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562844eed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562844eea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562844eed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f68733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f6878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f68733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f6871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562844e82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562844e82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562844e67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562844b170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562844b16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f6871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f6871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f6871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562844b16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c (2571 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b64ac7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b64ac720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b64ac7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53e9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b64ac0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b64ac0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b64abefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b64a89f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b64a89edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f53e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b64a89ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c (2572 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f1ab92015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f1ab91d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f1ab92089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59cd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59cd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59cd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59cd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f1ab8b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f1ab8b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f1ab89ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f1ab54a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f1ab549dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f59cd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59cd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59cd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f1ab549cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c (2573 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.2a-linux-gnu -target-abi apcs-gnu -target-feature +neon -target-feature -fullfp16 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.2a-unknown-linux-gnu" # | # | %struct.float16x4x2_t = type { [2 x <4 x half>] } # | %struct.float16x8x2_t = type { [2 x <8 x half>] } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vbsl_f16(<4 x i16> noundef %a, <2 x i32> noundef %b.coerce, <2 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p2.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__p2.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %retval = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %c = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %c.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | %coerce4 = alloca <4 x half>, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b1 = load <4 x half>, ptr %b, align 8 # | store <2 x i32> %c.coerce, ptr %c, align 8 # | %c2 = load <4 x half>, ptr %c, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x half> %b1, ptr %b.addr, align 8 # | store <4 x half> %c2, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | %2 = load <4 x half>, ptr %c.addr, align 8 # | store <4 x half> %1, ptr %coerce, align 8 # | %3 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %2, ptr %coerce3, align 8 # | %4 = load <2 x i32>, ptr %coerce3, align 8 # | store <2 x i32> %3, ptr %__p1.i, align 8 # | %__p11.i = load <4 x half>, ptr %__p1.i, align 8 # | store <2 x i32> %4, ptr %__p2.i, align 8 # | %__p22.i = load <4 x half>, ptr %__p2.i, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %__p11.i, ptr %__p1.addr.i, align 8 # | store <4 x half> %__p22.i, ptr %__p2.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %6 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %7 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vbsl_v.i = call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %5, <8 x i8> %6, <8 x i8> %7) # | store <8 x i8> %vbsl_v.i, ptr %ref.tmp.i, align 8 # | %8 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %8, ptr %__ret.i, align 8 # | %9 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %9, ptr %retval.i, align 8 # | %10 = load <2 x i32>, ptr %retval.i, align 8 # | store <2 x i32> %10, ptr %coerce4, align 8 # | %11 = load <4 x half>, ptr %coerce4, align 8 # | store <4 x half> %11, ptr %retval, align 8 # | %12 = load <2 x i32>, ptr %retval, align 8 # | ret <2 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vbslq_f16(<8 x i16> noundef %a, <4 x i32> noundef %b.coerce, <4 x i32> noundef %c.coerce) #0 { # | entry: # | %retval.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p2.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %__p2.addr.i = alloca <8 x half>, align 16 # | %__ret.i = alloca <8 x half>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %retval = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %c = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %c.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | %coerce4 = alloca <8 x half>, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b1 = load <8 x half>, ptr %b, align 16 # | store <4 x i32> %c.coerce, ptr %c, align 16 # | %c2 = load <8 x half>, ptr %c, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x half> %b1, ptr %b.addr, align 16 # | store <8 x half> %c2, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | %2 = load <8 x half>, ptr %c.addr, align 16 # | store <8 x half> %1, ptr %coerce, align 16 # | %3 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %2, ptr %coerce3, align 16 # | %4 = load <4 x i32>, ptr %coerce3, align 16 # | store <4 x i32> %3, ptr %__p1.i, align 16 # | %__p11.i = load <8 x half>, ptr %__p1.i, align 16 # | store <4 x i32> %4, ptr %__p2.i, align 16 # | %__p22.i = load <8 x half>, ptr %__p2.i, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x half> %__p11.i, ptr %__p1.addr.i, align 16 # | store <8 x half> %__p22.i, ptr %__p2.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %6 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %7 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vbslq_v.i = call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %5, <16 x i8> %6, <16 x i8> %7) # | store <16 x i8> %vbslq_v.i, ptr %ref.tmp.i, align 16 # | %8 = load <8 x half>, ptr %ref.tmp.i, align 16 # | store <8 x half> %8, ptr %__ret.i, align 16 # | %9 = load <8 x half>, ptr %__ret.i, align 16 # | store <8 x half> %9, ptr %retval.i, align 16 # | %10 = load <4 x i32>, ptr %retval.i, align 16 # | store <4 x i32> %10, ptr %coerce4, align 16 # | %11 = load <8 x half>, ptr %coerce4, align 16 # | store <8 x half> %11, ptr %retval, align 16 # | %12 = load <4 x i32>, ptr %retval, align 16 # | ret <4 x i32> %12 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzip_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef %a.coerce, <2 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <4 x half>, align 8 # | %__p1.i = alloca <4 x half>, align 8 # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %a = alloca <4 x half>, align 8 # | %b = alloca <4 x half>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %coerce = alloca <4 x half>, align 8 # | %coerce3 = alloca <4 x half>, align 8 # | store <2 x i32> %a.coerce, ptr %a, align 8 # | %a1 = load <4 x half>, ptr %a, align 8 # | store <2 x i32> %b.coerce, ptr %b, align 8 # | %b2 = load <4 x half>, ptr %b, align 8 # | store <4 x half> %a1, ptr %a.addr, align 8 # | store <4 x half> %b2, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %coerce, align 8 # | %2 = load <2 x i32>, ptr %coerce, align 8 # | store <4 x half> %1, ptr %coerce3, align 8 # | %3 = load <2 x i32>, ptr %coerce3, align 8 # | call void @llvm.experimental.noalias.scope.decl(metadata !3) # | store <2 x i32> %2, ptr %__p0.i, align 8, !noalias !3 # | %__p01.i = load <4 x half>, ptr %__p0.i, align 8, !noalias !3 # | store <2 x i32> %3, ptr %__p1.i, align 8, !noalias !3 # | %__p12.i = load <4 x half>, ptr %__p1.i, align 8, !noalias !3 # | store <4 x half> %__p01.i, ptr %__p0.addr.i, align 8, !noalias !3 # | store <4 x half> %__p12.i, ptr %__p1.addr.i, align 8, !noalias !3 # | %4 = load <8 x i8>, ptr %__p0.addr.i, align 8, !noalias !3 # | %5 = load <8 x i8>, ptr %__p1.addr.i, align 8, !noalias !3 # | %6 = bitcast <8 x i8> %4 to <4 x i16> # | %7 = bitcast <8 x i8> %5 to <4 x i16> # | %vzip.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !3 # | %8 = getelementptr inbounds <4 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <4 x i16> %6, <4 x i16> %7, <4 x i32> # | store <4 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !3 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vzipq_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 16 %agg.result, <4 x i32> noundef %a.coerce, <4 x i32> noundef %b.coerce) #0 { # | entry: # | %__p0.i = alloca <8 x half>, align 16 # | %__p1.i = alloca <8 x half>, align 16 # | %__p0.addr.i = alloca <8 x half>, align 16 # | %__p1.addr.i = alloca <8 x half>, align 16 # | %a = alloca <8 x half>, align 16 # | %b = alloca <8 x half>, align 16 # | %a.addr = alloca <8 x half>, align 16 # | %b.addr = alloca <8 x half>, align 16 # | %coerce = alloca <8 x half>, align 16 # | %coerce3 = alloca <8 x half>, align 16 # | store <4 x i32> %a.coerce, ptr %a, align 16 # | %a1 = load <8 x half>, ptr %a, align 16 # | store <4 x i32> %b.coerce, ptr %b, align 16 # | %b2 = load <8 x half>, ptr %b, align 16 # | store <8 x half> %a1, ptr %a.addr, align 16 # | store <8 x half> %b2, ptr %b.addr, align 16 # | %0 = load <8 x half>, ptr %a.addr, align 16 # | %1 = load <8 x half>, ptr %b.addr, align 16 # | store <8 x half> %0, ptr %coerce, align 16 # | %2 = load <4 x i32>, ptr %coerce, align 16 # | store <8 x half> %1, ptr %coerce3, align 16 # | %3 = load <4 x i32>, ptr %coerce3, align 16 # | call void @llvm.experimental.noalias.scope.decl(metadata !6) # | store <4 x i32> %2, ptr %__p0.i, align 16, !noalias !6 # | %__p01.i = load <8 x half>, ptr %__p0.i, align 16, !noalias !6 # | store <4 x i32> %3, ptr %__p1.i, align 16, !noalias !6 # | %__p12.i = load <8 x half>, ptr %__p1.i, align 16, !noalias !6 # | store <8 x half> %__p01.i, ptr %__p0.addr.i, align 16, !noalias !6 # | store <8 x half> %__p12.i, ptr %__p1.addr.i, align 16, !noalias !6 # | %4 = load <16 x i8>, ptr %__p0.addr.i, align 16, !noalias !6 # | %5 = load <16 x i8>, ptr %__p1.addr.i, align 16, !noalias !6 # | %6 = bitcast <16 x i8> %4 to <8 x i16> # | %7 = bitcast <16 x i8> %5 to <8 x i16> # | %vzip.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip.i, ptr %agg.result, align 4, !alias.scope !6 # | %8 = getelementptr inbounds <8 x i16>, ptr %agg.result, i32 1 # | %vzip3.i = shufflevector <8 x i16> %6, <8 x i16> %7, <8 x i32> # | store <8 x i16> %vzip3.i, ptr %8, align 4, !alias.scope !6 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_vuzp_f16(ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 %agg.result, <2 x i32> noundef # | ... # `---data was truncated (10240/35874) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055b12652e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b12652b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b12652e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98aec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98aeca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98aec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98aec31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1264c3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1264c3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1264a8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1261580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b126157dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98aec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98aec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98aec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b126157cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c --check-prefixes=CHECK-NOFP16 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c (2574 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.6a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vmmlaq_u32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vmmla1.i = call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %vmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vusmmlaq_s32(<4 x i32> noundef %r, <16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 8 # | %__p1.addr.i = alloca <16 x i8>, align 8 # | %__p2.addr.i = alloca <16 x i8>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %r.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <4 x i32> %r, ptr %r.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %r.addr, align 8 # | %1 = load <16 x i8>, ptr %a.addr, align 8 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | store <4 x i32> %0, ptr %__p0.addr.i, align 8 # | store <16 x i8> %1, ptr %__p1.addr.i, align 8 # | store <16 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 8 # | %vusmmla.i = bitcast <16 x i8> %3 to <4 x i32> # | %vusmmla1.i = call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %vusmmla.i, <16 x i8> %4, <16 x i8> %5) # | store <4 x i32> %vusmmla1.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <8 x i8> %1, ptr %__p1.addr.i, align 8 # | store <8 x i8> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %3 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %4, <8 x i8> %5) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vusdot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_845 = alloca <2 x i32>, align 8 # | %__s0_845 = alloca <2 x i32>, align 8 # | %__s1_845 = alloca <8 x i8>, align 8 # | %__s2_845 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_845, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_845, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_845, align 8 # | %3 = load <2 x i32>, ptr %__s0_845, align 8 # | %4 = load <8 x i8>, ptr %__s1_845, align 8 # | %5 = load <2 x i32>, ptr %__s2_845, align 8 # | store <2 x i32> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <2 x i32> # | %lane = shufflevector <2 x i32> %7, <2 x i32> %7, <2 x i32> zeroinitializer # | store <2 x i32> %lane, ptr %ref.tmp1, align 8 # | %8 = load <2 x i32>, ptr %ref.tmp1, align 8 # | store <2 x i32> %8, ptr %__ret, align 8 # | %9 = load <2 x i32>, ptr %__ret, align 8 # | store <2 x i32> %9, ptr %tmp, align 8 # | %10 = load <2 x i32>, ptr %tmp, align 8 # | store <2 x i32> %10, ptr %ref.tmp, align 8 # | %11 = load <8 x i8>, ptr %ref.tmp, align 8 # | store <2 x i32> %3, ptr %__p0.addr.i, align 8 # | store <8 x i8> %4, ptr %__p1.addr.i, align 8 # | store <8 x i8> %11, ptr %__p2.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %14 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vusdot.i = bitcast <8 x i8> %12 to <2 x i32> # | %vusdot1.i = call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %vusdot.i, <8 x i8> %13, <8 x i8> %14) # | store <2 x i32> %vusdot1.i, ptr %ref.tmp.i, align 8 # | %15 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %15, ptr %__ret.i, align 8 # | %16 = load <2 x i32>, ptr %__ret.i, align 8 # | store <2 x i32> %16, ptr %__ret_845, align 8 # | %17 = load <2 x i32>, ptr %__ret_845, align 8 # | store <2 x i32> %17, ptr %tmp2, align 8 # | %18 = load <2 x i32>, ptr %tmp2, align 8 # | ret <2 x i32> %18 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vsudot_lane_s32(<2 x i32> noundef %r, <8 x i8> noundef %a, <8 x i8> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <8 x i8>, align 8 # | %__p2.addr.i = alloca <8 x i8>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %r.addr = alloca <2 x i32>, align 8 # | %a.addr = alloca <8 x i8>, align 8 # | %b.addr = alloca <8 x i8>, align 8 # | %__ret_841 = alloca <2 x i32>, align 8 # | %__s0_841 = alloca <2 x i32>, align 8 # | %__s1_841 = alloca <8 x i8>, align 8 # | %__s2_841 = alloca <8 x i8>, align 8 # | %ref.tmp = alloca <2 x i32>, align 8 # | %__ret = alloca <2 x i32>, align 8 # | %__s0 = alloca <2 x i32>, align 8 # | %ref.tmp1 = alloca <8 x i8>, align 8 # | %tmp = alloca <2 x i32>, align 8 # | %tmp2 = alloca <2 x i32>, align 8 # | store <2 x i32> %r, ptr %r.addr, align 8 # | store <8 x i8> %a, ptr %a.addr, align 8 # | store <8 x i8> %b, ptr %b.addr, align 8 # | %0 = load <2 x i32>, ptr %r.addr, align 8 # | store <2 x i32> %0, ptr %__s0_841, align 8 # | %1 = load <8 x i8>, ptr %a.addr, align 8 # | store <8 x i8> %1, ptr %__s1_841, align 8 # | %2 = load <8 x i8>, ptr %b.addr, align 8 # | store <8 x i8> %2, ptr %__s2_841, align 8 # | %3 = load <2 x i32>, ptr %__s0_841, align 8 # | %4 = load <2 x i32>, ptr %__s2_841, align 8 # | store <2 x i32> %4, ptr %__s0, align 8 # | %5 = load <8 x i8>, ptr %__s0, align 8 # | %6 = bitcast <8 x i8> %5 to <2 x i32> # | %lane = shufflevector <2 x i32> %6, <2 x i32> %6, <2 # | ... # `---data was truncated (10240/18482) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000564645be715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564645be40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564645be789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd12a133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd12a18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd12a133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd12a11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564645b7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564645b7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564645b61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005646458110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564645810dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd12a11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd12a11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd12a11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564645810cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c (2575 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_i16m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv. # | ... # `---data was truncated (10240/16654) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cb760fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cb760fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cb760fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2b3441bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2b344725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2b3441ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2b34403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cb76093e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cb76093c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cb76078b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cb75d280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cb75d27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2b34404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2b344050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2b344050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cb75d27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c (2576 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c (2577 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmacc_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmacc.nxv8f32.f16.nxv8f16.i64(, ha # | ... # `---data was truncated (10240/90685) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056505ee0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056505ee070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056505ee0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff515505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff51555c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff515505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff5154ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056505ed9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056505ed9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056505ed84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056505ea340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056505ea33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff5154eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff5154ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff5154ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056505ea33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c (2578 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | ... # `---data was truncated (10240/12457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559fd11bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559fd11b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559fd11bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cde449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cde4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cde449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cde431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559fd1151e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559fd1151c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559fd1136b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559fd0de60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559fd0de5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0cde432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cde4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cde4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559fd0de5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c (2579 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ac5133e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ac5133b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ac5133e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98fcb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98fcb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98fcb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98fcaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ac512d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ac512d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ac512b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ac50f680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ac50f67dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98fcaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98fcaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98fcaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ac50f67cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/distributed-thin-lto/newpm.ll (2580 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/newpm.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 11 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/newpm.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/newpm.ll # | #0 0x00005561fdf0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005561fdf080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005561fdf0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a6921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a692725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a6921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a69203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005561fdea0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005561fdea0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005561fde85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005561fdb350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005561fdb34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9a69204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a692050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a692050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005561fdb34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c (2581 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfclass.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfclass_v_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfclass.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: n # | ... # `---data was truncated (10240/66314) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cdaebe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555cdaebb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555cdaebe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb470f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb470f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb470f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb470eed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cdae53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555cdae53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555cdae38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555cdaae80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555cdaae7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb470eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb470eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb470eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cdaae7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c (2582 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056204375c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620437590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056204375c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc3d2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc3d238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc3d2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc3d231b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620436f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620436f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005620436d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620433860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562043385dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc3d231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc3d231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc3d231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562043385cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c (2583 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d7e77cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d7e77c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d7e77cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f333f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f333f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f333f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f333f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d7e7760e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d7e7760c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d7e7745b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d7e73f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d7e73f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f333f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f333f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f333f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d7e73f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c (2584 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32bf16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32bf16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | defin # | ... # `---data was truncated (10240/13035) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f22226115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f22225e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f22226189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3624e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3624ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3624e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3624e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2221f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f2221f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f2221dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f221e8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f221e8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3624e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3624e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3624e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f221e8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c (2585 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("ri # | ... # `---data was truncated (10240/13634) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056485627615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648562730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056485627689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f88a5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f88a56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f88a5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f88a5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056485620be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056485620bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648561f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564855ea00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564855e9fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f88a5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f88a56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f88a56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564855e9fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c (2586 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c (2587 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c (2588 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557550a0915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557550a060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557550a0989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9b4249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9b42a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9b4249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9b4231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055755099ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055755099ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557550983b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575506330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557550632dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb9b4232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9b42330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9b42330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557550632cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c (2589 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005565db71915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005565db7160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005565db71989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff792e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff792ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff792e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff792e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005565db6aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005565db6aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005565db693b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005565db3430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005565db342dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff792e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff792e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff792e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005565db342cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c (2590 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558bbcf4415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558bbcf410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558bbcf4489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd54a933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd54a98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd54a933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd54a91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558bbced9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558bbced9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558bbcebeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558bbcb6e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558bbcb6ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd54a91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd54a91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd54a91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558bbcb6dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminq.c (2591 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = icmp ule <16 x i8> %0, %1 # | %3 = select <16 x i1> %2, <16 x i8> %0, <16 x i8> %1 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = icmp sle <8 x i16> %0, %1 # | %3 = select <8 x i1> %2, <8 x i16> %0, <8 x i16> %1 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = icmp ule <4 x i32> %0, %1 # | %3 = select <4 x i1> %2, <4 x i32> %0, <4 x i32> %1 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a22a32715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a22a3240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a22a32789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0428333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f042838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0428333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f042831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a22a2bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a22a2bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a22a2a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a229f510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a229f50dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f042831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f042831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f042831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a229f50cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c (2592 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627456e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627456e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627456e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4371f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4371f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4371f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4371f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056274567de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056274567dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562745662b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627453120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562745311dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4371f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4371f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4371f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562745311cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c (2593 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8mf2_b16( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m1_b8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vx_i8m2_b4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsge.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsge_vv_i8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsge.nxv32i8.nxv32i8.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c (2594 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577a194c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005577a19490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005577a194c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe3d0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe3d058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe3d0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe3d051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577a18e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005577a18e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005577a18c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005577a15760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005577a1575dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe3d051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe3d051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe3d051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577a1575cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c (2595 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf4_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.mask.nxv1bf16.bf16.i64(, , bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_bf16mf2_tum( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.a # | ... # `---data was truncated (10240/32394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d3594f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d3594c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d3594f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff08db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff08db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff08db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff08db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d358e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d358e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d358c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d355790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d35578dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff08db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff08db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff08db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d35578cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c (2596 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_f32m4x2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple # | ... # `---data was truncated (10240/96919) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633b993e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633b993b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633b993e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd4a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd4a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd4a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd4a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633b98d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633b98d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633b98b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633b95680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633b9567dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd4a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd4a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd4a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633b9567cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c (2597 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005611480fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005611480f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005611480fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca68b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca68b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca68b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca68b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056114808fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056114808fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561148074b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561147d240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561147d23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca68b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca68b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca68b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561147d23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c (2598 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv64i8.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv1i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv2i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv4i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv8i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv16i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8_tu( %maskedoff, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vid.nxv32i16.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c (2599 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_i8mf8x8 # | ... # `---data was truncated (10240/160903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fea710f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fea710c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fea710f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6487f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6487f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6487f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6487eed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fea70a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fea70a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fea7089b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fea6d390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fea6d38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6487eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6487eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6487eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fea6d38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c (2600 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8_tu( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2_tu( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.a # | ... # `---data was truncated (10240/73947) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d6d4c6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d6d4c660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d6d4c6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc156a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc156aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc156a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc156a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d6d4bfee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d6d4bfec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d6d4be3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d6d48930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d6d4892dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc156a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc156a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc156a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d6d4892cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c (2601 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsof.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ceef9fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ceef9fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ceef9fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f72fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f72fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f72fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f72fd031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ceef993e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ceef993c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ceef978b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ceef6280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ceef627dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f72fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f72fd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f72fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ceef627cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c (2602 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f16m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_v # | ... # `---data was truncated (10240/253156) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609724b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609724b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609724b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce02933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce0298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce02933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce0291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056097244ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056097244cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560972431b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609720e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609720e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce0291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce0291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce0291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609720e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c (2603 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627980fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627980fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627980fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46fde49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46fdea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46fde49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46fde31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562798092e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562798092c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562798077b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562797d270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562797d26dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f46fde32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46fde330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46fde330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562797d26cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c (2604 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c0ffc3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c0ffc340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c0ffc3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5647333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f564738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5647333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f564731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c0ffbcce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c0ffbccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c0ffbb1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c0ff8610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c0ff860dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f564731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f564731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f564731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c0ff860cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c (2605 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i6 # | ... # `---data was truncated (10240/25511) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056229a3ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056229a3ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056229a3ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4f5bc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4f5bca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4f5bc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4f5bc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056229a382e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056229a382c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056229a367b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056229a0170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056229a016dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4f5bc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4f5bc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4f5bc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056229a016cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c (2606 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005564c8f5515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564c8f520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005564c8f5589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f433d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f433d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f433d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f433d431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005564c8eeae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005564c8eeac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005564c8ecfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005564c8b7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005564c8b7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f433d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f433d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f433d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005564c8b7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c (2607 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef # | ... # `---data was truncated (10240/14333) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056219a25315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056219a2500f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056219a25389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fef0e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fef0e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fef0e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fef0e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056219a1e8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056219a1e8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056219a1cdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562199e7d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562199e7cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fef0e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fef0e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fef0e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562199e7ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c (2608 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eaddbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561eaddbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561eaddbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9ae133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9ae18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9ae133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9ae11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eadd54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561eadd54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561eadd39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561ead9e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561ead9e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe9ae11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9ae11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9ae11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561ead9e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c (2609 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +v8.5a -flax-vector-conversions=none -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32z.i = call float @llvm.aarch64.frint32z.f32(float %1) # | ret float %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32z.i = call double @llvm.aarch64.frint32z.f64(double %1) # | ret double %frint32z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64zf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64z.i = call float @llvm.aarch64.frint64z.f32(float %1) # | ret float %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64z(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64z.i = call double @llvm.aarch64.frint64z.f64(double %1) # | ret double %frint64z.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint32xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint32x.i = call float @llvm.aarch64.frint32x.f32(float %1) # | ret float %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint32x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint32x.i = call double @llvm.aarch64.frint32x.f64(double %1) # | ret double %frint32x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_rint64xf(float noundef %a) #0 { # | entry: # | %__a.addr.i = alloca float, align 4 # | %a.addr = alloca float, align 4 # | store float %a, ptr %a.addr, align 4 # | %0 = load float, ptr %a.addr, align 4 # | store float %0, ptr %__a.addr.i, align 4 # | %1 = load float, ptr %__a.addr.i, align 4 # | %frint64x.i = call float @llvm.aarch64.frint64x.f32(float %1) # | ret float %frint64x.i # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_rint64x(double noundef %a) #0 { # | entry: # | %__a.addr.i = alloca double, align 8 # | %a.addr = alloca double, align 8 # | store double %a, ptr %a.addr, align 8 # | %0 = load double, ptr %a.addr, align 8 # | store double %0, ptr %__a.addr.i, align 8 # | %1 = load double, ptr %__a.addr.i, align 8 # | %frint64x.i = call double @llvm.aarch64.frint64x.f64(double %1) # | ret double %frint64x.i # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64z.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64z.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint32x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint32x.f64(double) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.aarch64.frint64x.f32(float) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare double @llvm.aarch64.frint64x.f64(double) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561388e5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561388e580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561388e5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fceebb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fceebb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fceebb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fceebb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561388df0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561388df0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561388dd5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561388a850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561388a84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fceebb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fceebb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fceebb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561388a84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c (2610 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf8( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf4( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8mf2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m1( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vx_i8m2( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vxor.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vxor.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vxor_vv_i8m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/175163) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b13131015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b13130d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b13131089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1afe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1afea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1afe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1afe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1312a5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1312a5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b13128ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b130f3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b130f39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1afe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1afe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1afe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b130f39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c (2611 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0cb6dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0cb6da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0cb6dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec90b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec90b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec90b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec90b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0cb672e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0cb672c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f0cb657b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0cb3070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f0cb306dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec90b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec90b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec90b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0cb306cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c (2612 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b030eb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b030eb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b030eb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0104049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01040a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0104049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0104031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b030e4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b030e4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b030e32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b030ae20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b030ae1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0104032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01040330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01040330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b030ae1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c (2613 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4a87fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4a87f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4a87fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb013b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb013b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb013b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb013b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4a8791e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f4a8791c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f4a8776b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4a84260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4a8425dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb013b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb013b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb013b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4a8425cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c (2614 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056137dcbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056137dcb90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056137dcbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2564705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f256475c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2564705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25646ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056137dc51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056137dc51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056137dc36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056137d8e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056137d8e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25646eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25646ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25646ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056137d8e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c (2615 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ececda15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ececd70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ececda89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8b2849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8b28a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8b2849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8b2831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ecec6fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ecec6fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ecec54b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ece9040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ece903dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8b2832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8b28330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8b28330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ece903cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c (2616 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv1f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv2f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv4f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnj.nxv8f16.f16.i64( %0, %1, half %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_f16m4_tu( %maskedoff, # | ... # `---data was truncated (10240/157475) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fc631315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556fc63100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556fc631389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f67aac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f67aac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f67aac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f67aac03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fc62a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556fc62a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556fc628db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556fc5f3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556fc5f3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f67aac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f67aac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f67aac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fc5f3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c (2617 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define d # | ... # `---data was truncated (10240/51420) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ffb4c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ffb4be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ffb4c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ae6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ae62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ae6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ae6231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ffb456e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ffb456c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ffb43bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ffb0eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ffb0eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ae6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ae62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ae62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ffb0eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c (2618 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/47728) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056160b29c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056160b2990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056160b29c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc4ae733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc4ae78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc4ae733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc4ae71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056160b231e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056160b231c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056160b216b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056160aec60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056160aec5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc4ae71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc4ae71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc4ae71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056160aec5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c (2619 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr, <8 x i16>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_s32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr, <4 x i32>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_s8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr, <16 x i8>, i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_u16(ptr noundef %base, <8 x i16> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0.v8i16(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_u32(ptr noundef %base, <4 x i32> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.v4i32.p0.v4i32(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_u8(ptr noundef %base, <16 x i8> noundef %offset) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.v16i8.p0.v16i8(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_s16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 0, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr, <8 x i16>, i32, i32, i32, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 0, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr, <4 x i32>, i32, i32, i32, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_s8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 0, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr, <16 x i8>, i32, i32, i32, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_z_u16(ptr noundef %base, <8 x i16> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <8 x i16> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <8 x i16>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0.v8i16.v8i1(ptr %0, <8 x i16> %1, i32 8, i32 0, i32 1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_u32(ptr noundef %base, <4 x i32> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <4 x i32> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <4 x i32>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0.v4i32.v4i1(ptr %0, <4 x i32> %1, i32 8, i32 0, i32 1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vldrbq_gather_offset_z_u8(ptr noundef %base, <16 x i8> noundef %offset, i16 noundef zeroext %p) #0 { # | entry: # | %base.addr = alloca ptr, align 4 # | %offset.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store ptr %base, ptr %base.addr, align 4 # | store <16 x i8> %offset, ptr %offset.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %base.addr, align 4 # | %1 = load <16 x i8>, ptr %offset.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vldr.gather.offset.predicated.v16i8.p0.v16i8.v16i1(ptr %0, <16 x i8> %1, i32 8, i32 0, i32 1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vf # | ... # `---data was truncated (10240/117019) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec6fdcb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec6fdc80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec6fdcb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ac5b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ac5b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ac5b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ac5b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec6fd60e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec6fd60c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec6fd45b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec6f9f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec6f9f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ac5b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ac5b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ac5b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec6f9f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c (2620 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfeq.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c (2621 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585cc10915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585cc1060f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585cc10989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec38249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec382a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec38249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec38231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585cc09ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585cc09ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585cc083b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585cbd330b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585cbd32dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec38232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec382330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec382330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585cbd32cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c (2622 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae701a215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae7019f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae701a289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c10049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c100a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c10049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c10031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae70137e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae70137c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae7011cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae6fdcc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae6fdcbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c10032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c100330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c100330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae6fdcbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c (2623 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captur # | ... # `---data was truncated (10240/30617) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583b7c2215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583b7c1f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005583b7c2289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb5ba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb5baa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb5ba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb5ba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583b7bb7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583b7bb7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583b7b9cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583b784c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005583b784bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb5ba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb5ba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb5ba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583b784bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c (2624 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tu # | ... # `---data was truncated (10240/16560) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d870c0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d870c070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d870c0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1552849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f15528a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1552849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1552831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d870b9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d870b9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d870b84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d8708340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d870833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1552832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f15528330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f15528330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d870833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c (2625 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vrhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vrhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vrhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558be774015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558be773d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558be774089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3737b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3737b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3737b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3737aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558be76d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558be76d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558be76bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558be736a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558be7369dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3737aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3737aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3737aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558be7369cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c (2626 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce8fd4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce8fd4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce8fd4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa61d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa61d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa61d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa61d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce8fce4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce8fce4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce8fcc9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce8f9790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce8f978dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa61d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa61d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa61d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce8f978cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c (2627 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64ff_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c (2628 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv2i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv4i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 3) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractva # | ... # `---data was truncated (10240/27866) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6b661815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6b66150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6b661889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc079733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc07978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc079733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc07971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6b65ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6b65adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6b6592b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6b62420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6b6241dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc07971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc07971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc07971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6b6241cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c (2629 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsif_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsif.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsif.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abd4b7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055abd4b760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055abd4b7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f534cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f534cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f534cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f534cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abd4b0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055abd4b0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055abd4af3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055abd47a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055abd47a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f534cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f534cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f534cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abd47a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c (2630 of 27911) ******************** TEST 'Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c" # | target datalayout = "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" # | target triple = "armv8.1a-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %0, ptr %__p0.addr.i, align 8 # | store <4 x i16> %1, ptr %__p1.addr.i, align 8 # | store <4 x i16> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %3 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %4 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %5 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %6 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %6, ptr %__ret.i, align 8 # | %7 = load <4 x i16>, ptr %__ret.i, align 8 # | ret <4 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x i32>, align 8 # | %b.addr = alloca <2 x i32>, align 8 # | %c.addr = alloca <2 x i32>, align 8 # | store <2 x i32> %a, ptr %a.addr, align 8 # | store <2 x i32> %b, ptr %b.addr, align 8 # | store <2 x i32> %c, ptr %c.addr, align 8 # | %0 = load <2 x i32>, ptr %a.addr, align 8 # | %1 = load <2 x i32>, ptr %b.addr, align 8 # | %2 = load <2 x i32>, ptr %c.addr, align 8 # | store <2 x i32> %0, ptr %__p0.addr.i, align 8 # | store <2 x i32> %1, ptr %__p1.addr.i, align 8 # | store <2 x i32> %2, ptr %__p2.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %4 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %5 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s32.i = bitcast <8 x i8> %3 to <2 x i32> # | %vqrdmlah_s321.i = bitcast <8 x i8> %4 to <2 x i32> # | %vqrdmlah_s322.i = bitcast <8 x i8> %5 to <2 x i32> # | %vqrdmlah_s323.i = call <2 x i32> @llvm.arm.neon.vqrdmlah.v2i32(<2 x i32> %vqrdmlah_s32.i, <2 x i32> %vqrdmlah_s321.i, <2 x i32> %vqrdmlah_s322.i) # | %vqrdmlah_s324.i = bitcast <2 x i32> %vqrdmlah_s323.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s324.i, ptr %ref.tmp.i, align 8 # | %6 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %6, ptr %__ret.i, align 8 # | %7 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i16> @test_vqrdmlahq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, <8 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <8 x i16>, align 16 # | %__p1.addr.i = alloca <8 x i16>, align 16 # | %__p2.addr.i = alloca <8 x i16>, align 16 # | %__ret.i = alloca <8 x i16>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <8 x i16>, align 16 # | %b.addr = alloca <8 x i16>, align 16 # | %c.addr = alloca <8 x i16>, align 16 # | store <8 x i16> %a, ptr %a.addr, align 16 # | store <8 x i16> %b, ptr %b.addr, align 16 # | store <8 x i16> %c, ptr %c.addr, align 16 # | %0 = load <8 x i16>, ptr %a.addr, align 16 # | %1 = load <8 x i16>, ptr %b.addr, align 16 # | %2 = load <8 x i16>, ptr %c.addr, align 16 # | store <8 x i16> %0, ptr %__p0.addr.i, align 16 # | store <8 x i16> %1, ptr %__p1.addr.i, align 16 # | store <8 x i16> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s16.i = bitcast <16 x i8> %3 to <8 x i16> # | %vqrdmlahq_s161.i = bitcast <16 x i8> %4 to <8 x i16> # | %vqrdmlahq_s162.i = bitcast <16 x i8> %5 to <8 x i16> # | %vqrdmlahq_s163.i = call <8 x i16> @llvm.arm.neon.vqrdmlah.v8i16(<8 x i16> %vqrdmlahq_s16.i, <8 x i16> %vqrdmlahq_s161.i, <8 x i16> %vqrdmlahq_s162.i) # | %vqrdmlahq_s164.i = bitcast <8 x i16> %vqrdmlahq_s163.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s164.i, ptr %ref.tmp.i, align 16 # | %6 = load <8 x i16>, ptr %ref.tmp.i, align 16 # | store <8 x i16> %6, ptr %__ret.i, align 16 # | %7 = load <8 x i16>, ptr %__ret.i, align 16 # | ret <8 x i16> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vqrdmlahq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i32>, align 16 # | %__p1.addr.i = alloca <4 x i32>, align 16 # | %__p2.addr.i = alloca <4 x i32>, align 16 # | %__ret.i = alloca <4 x i32>, align 16 # | %ref.tmp.i = alloca <16 x i8>, align 16 # | %a.addr = alloca <4 x i32>, align 16 # | %b.addr = alloca <4 x i32>, align 16 # | %c.addr = alloca <4 x i32>, align 16 # | store <4 x i32> %a, ptr %a.addr, align 16 # | store <4 x i32> %b, ptr %b.addr, align 16 # | store <4 x i32> %c, ptr %c.addr, align 16 # | %0 = load <4 x i32>, ptr %a.addr, align 16 # | %1 = load <4 x i32>, ptr %b.addr, align 16 # | %2 = load <4 x i32>, ptr %c.addr, align 16 # | store <4 x i32> %0, ptr %__p0.addr.i, align 16 # | store <4 x i32> %1, ptr %__p1.addr.i, align 16 # | store <4 x i32> %2, ptr %__p2.addr.i, align 16 # | %3 = load <16 x i8>, ptr %__p0.addr.i, align 16 # | %4 = load <16 x i8>, ptr %__p1.addr.i, align 16 # | %5 = load <16 x i8>, ptr %__p2.addr.i, align 16 # | %vqrdmlahq_s32.i = bitcast <16 x i8> %3 to <4 x i32> # | %vqrdmlahq_s321.i = bitcast <16 x i8> %4 to <4 x i32> # | %vqrdmlahq_s322.i = bitcast <16 x i8> %5 to <4 x i32> # | %vqrdmlahq_s323.i = call <4 x i32> @llvm.arm.neon.vqrdmlah.v4i32(<4 x i32> %vqrdmlahq_s32.i, <4 x i32> %vqrdmlahq_s321.i, <4 x i32> %vqrdmlahq_s322.i) # | %vqrdmlahq_s324.i = bitcast <4 x i32> %vqrdmlahq_s323.i to <16 x i8> # | store <16 x i8> %vqrdmlahq_s324.i, ptr %ref.tmp.i, align 16 # | %6 = load <4 x i32>, ptr %ref.tmp.i, align 16 # | store <4 x i32> %6, ptr %__ret.i, align 16 # | %7 = load <4 x i32>, ptr %__ret.i, align 16 # | ret <4 x i32> %7 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i16> @test_vqrdmlah_lane_s16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <4 x i16>, align 8 # | %__p1.addr.i = alloca <4 x i16>, align 8 # | %__p2.addr.i = alloca <4 x i16>, align 8 # | %__ret.i = alloca <4 x i16>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x i16>, align 8 # | %b.addr = alloca <4 x i16>, align 8 # | %c.addr = alloca <4 x i16>, align 8 # | %__ret_140 = alloca <4 x i16>, align 8 # | %__s0_140 = alloca <4 x i16>, align 8 # | %__s1_140 = alloca <4 x i16>, align 8 # | %__s2_140 = alloca <4 x i16>, align 8 # | %__ret = alloca <4 x i16>, align 8 # | %__s0 = alloca <4 x i16>, align 8 # | %ref.tmp = alloca <8 x i8>, align 8 # | %tmp = alloca <4 x i16>, align 8 # | %tmp1 = alloca <4 x i16>, align 8 # | store <4 x i16> %a, ptr %a.addr, align 8 # | store <4 x i16> %b, ptr %b.addr, align 8 # | store <4 x i16> %c, ptr %c.addr, align 8 # | %0 = load <4 x i16>, ptr %a.addr, align 8 # | store <4 x i16> %0, ptr %__s0_140, align 8 # | %1 = load <4 x i16>, ptr %b.addr, align 8 # | store <4 x i16> %1, ptr %__s1_140, align 8 # | %2 = load <4 x i16>, ptr %c.addr, align 8 # | store <4 x i16> %2, ptr %__s2_140, align 8 # | %3 = load <4 x i16>, ptr %__s0_140, align 8 # | %4 = load <4 x i16>, ptr %__s1_140, align 8 # | %5 = load <4 x i16>, ptr %__s2_140, align 8 # | store <4 x i16> %5, ptr %__s0, align 8 # | %6 = load <8 x i8>, ptr %__s0, align 8 # | %7 = bitcast <8 x i8> %6 to <4 x i16> # | %lane = shufflevector <4 x i16> %7, <4 x i16> %7, <4 x i32> # | store <4 x i16> %lane, ptr %ref.tmp, align 8 # | %8 = load <4 x i16>, ptr %ref.tmp, align 8 # | store <4 x i16> %8, ptr %__ret, align 8 # | %9 = load <4 x i16>, ptr %__ret, align 8 # | store <4 x i16> %9, ptr %tmp, align 8 # | %10 = load <4 x i16>, ptr %tmp, align 8 # | store <4 x i16> %3, ptr %__p0.addr.i, align 8 # | store <4 x i16> %4, ptr %__p1.addr.i, align 8 # | store <4 x i16> %10, ptr %__p2.addr.i, align 8 # | %11 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %12 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %13 = load <8 x i8>, ptr %__p2.addr.i, align 8 # | %vqrdmlah_s16.i = bitcast <8 x i8> %11 to <4 x i16> # | %vqrdmlah_s161.i = bitcast <8 x i8> %12 to <4 x i16> # | %vqrdmlah_s162.i = bitcast <8 x i8> %13 to <4 x i16> # | %vqrdmlah_s163.i = call <4 x i16> @llvm.arm.neon.vqrdmlah.v4i16(<4 x i16> %vqrdmlah_s16.i, <4 x i16> %vqrdmlah_s161.i, <4 x i16> %vqrdmlah_s162.i) # | %vqrdmlah_s164.i = bitcast <4 x i16> %vqrdmlah_s163.i to <8 x i8> # | store <8 x i8> %vqrdmlah_s164.i, ptr %ref.tmp.i, align 8 # | %14 = load <4 x i16>, ptr %ref.tmp.i, align 8 # | store <4 x i16> %14, ptr %__ret.i, align 8 # | %15 = load <4 x i16>, ptr %__ret.i, align 8 # | store <4 x i16> %15, ptr %__ret_140, align 8 # | %16 = load <4 x i16>, ptr %__ret_140, align 8 # | store <4 x i16> %16, ptr %tmp1, align 8 # | %17 = load <4 x i16>, ptr %tmp1, align 8 # | ret <4 x i16> %17 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vqrdmlah_lane_s32(<2 x i32> noundef %a, <2 x i32> noundef %b, <2 x i32> noundef %c) #0 { # | entry: # | %__p0.addr.i = alloca <2 x i32>, align 8 # | %__p1.addr.i = alloca <2 x i32>, align 8 # | %__p2.addr.i = alloca <2 x i32>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr # | ... # `---data was truncated (10240/38786) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=mem2reg,sroa,dce -S # | #0 0x0000561bbb0ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561bbb0b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561bbb0ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f942d01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f942d0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f942d01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f942d003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561bbb04fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561bbb04fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561bbb034b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561bbace40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561bbace3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f942d004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f942d0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f942d0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561bbace3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --check-prefix=CHECK-ARM # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c (2631 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 5) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_u32mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 nounde # | ... # `---data was truncated (10240/31748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005620e6d4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005620e6d470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005620e6d4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feed5c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feed5c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feed5c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feed5c03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005620e6cdfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005620e6cdfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005620e6cc4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005620e69740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005620e6973dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feed5c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feed5c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feed5c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005620e6973cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c (2632 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv4i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv4i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m1_b8( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv8i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv8i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m2_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8m2_b4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv16i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.nxv16i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m4_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsltu.nxv32i8.n # | ... # `---data was truncated (10240/95347) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564a5c84415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564a5c8410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564a5c84489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7d5261bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7d526725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7d5261ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7d52603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564a5c7d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564a5c7d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564a5c7beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564a5c46e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564a5c46ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7d52604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7d526050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7d526050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564a5c46dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c (2633 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wx_i8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64( %0, %1, i64 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclip_wv_i8m2_tu(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (2634 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvsintload -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vlnu.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf8_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf4_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vlnu8_v_u8mf2_tum( %mask, %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64( %1, ptr %2, %0, # | ... # `---data was truncated (10240/29451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005639a9ce915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005639a9ce60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005639a9ce989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe21f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe21f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe21f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe21f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005639a9c7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005639a9c7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005639a9c63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005639a99130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005639a9912dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe21f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe21f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe21f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005639a9912cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll (2635 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-diagnostic-handler-remarks-with-hotness.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll # | #0 0x000056350cf9a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056350cf970f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056350cf9a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48a5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48a50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48a5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48a5031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056350cf2fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056350cf2fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056350cf14b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056350cbc40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056350cbc3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48a5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48a50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48a50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056350cbc3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c (2636 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u8m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv64i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv64i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vbrev_v_u16m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vbrev.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vbrev.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define ds # | ... # `---data was truncated (10240/95215) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055811d1b015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055811d1ad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055811d1b089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb03c133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb03c18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb03c133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb03c11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055811d145e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055811d145c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055811d12ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055811cdda0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055811cdd9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb03c11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb03c11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb03c11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055811cdd9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c (2637 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055946e60615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055946e6030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055946e60689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f129b705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f129b75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f129b705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f129b6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055946e59be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055946e59bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055946e580b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055946e2300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055946e22fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f129b6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f129b6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f129b6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055946e22fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c (2638 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv1i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c (2639 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_m( %mask, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.mask.nxv1i64.nxv1i64.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_m( %mask, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/18867) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056031527a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603152770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056031527a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a41a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a41aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a41a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a41a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056031520fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056031520fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005603151f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560314ea40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560314ea3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a41a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a41a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a41a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560314ea3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c (2640 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipo_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipo.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @ # | ... # `---data was truncated (10240/35774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636cdc3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005636cdc2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005636cdc3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc462733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc46278a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc462733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc46271b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636cdbc7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005636cdbc7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005636cdbacb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636cd85c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005636cd85bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc46271cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc46271d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc46271d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636cd85bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c (2641 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589b45e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005589b45e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005589b45e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb94649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb946a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb94649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb94631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589b457ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005589b457ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005589b4563b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589b42130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005589b4212dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbb94632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb946330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb946330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589b4212cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c (2642 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslideup.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf4_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslideup_vx_bf16mf2_m( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslideup.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslideup.mask.nxv2bf16.i64(, , # | ... # `---data was truncated (10240/16521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621f3b5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621f3b590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005621f3b5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc9ca249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9ca2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc9ca249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc9ca231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621f3af1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621f3af1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621f3ad6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621f37860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005621f3785dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc9ca232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9ca2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9ca2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621f3785cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c (2643 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = # | ... # `---data was truncated (10240/10936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056040fc0e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056040fc0b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056040fc0e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfaf933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfaf98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfaf933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfaf91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056040fba3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056040fba3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056040fb88b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056040f8380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056040f837dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfaf91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfaf91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfaf91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056040f837cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c (2644 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c (2645 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, target("riscv # | ... # `---data was truncated (10240/70386) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005625d1a3215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005625d1a2f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005625d1a3289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0398933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f039898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0398933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f039891b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625d19c7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625d19c7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625d19acb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625d165c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005625d165bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f039891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f039891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f039891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005625d165bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c (2646 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_f32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32_v_i32m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/63169) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643345b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643345b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643345b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11c7649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11c76a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11c7649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11c7631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564334548e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564334548c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056433452db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643341dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643341dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11c7632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11c76330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11c76330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643341dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c (2647 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 1) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 1, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/11851) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565530a9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565530a940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565530a9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e05c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e05ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e05c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e05c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565530a2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565530a2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565530a11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005655306c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005655306c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e05c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e05c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e05c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005655306c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c (2648 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_i8m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf8x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv1i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e8_v_u8mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f86add215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f86adcf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f86add289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff7dda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff7ddaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff7dda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff7dda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f86ad67e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f86ad67c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f86ad4cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f86a9fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f86a9fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff7dda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff7dda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff7dda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f86a9fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c (2649 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f24652215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f24651f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f24652289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd758449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7584a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd758449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd758431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2464b7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f2464b7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f24649cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f24614c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f24614bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd758432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7584330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7584330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f24614bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c (2650 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrdiv.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrdiv.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrdiv_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee18f2615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee18f230f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee18f2689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7efda49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7efdaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7efda49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7efda31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee18ebbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee18ebbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee18ea0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee18b500b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee18b4fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7efda32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7efda330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7efda330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee18b4fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c (2651 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_i32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32mf2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m1x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_u32m2x3(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e93f7b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e93f7b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e93f7b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6e82e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6e82e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6e82e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6e82e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e93f748e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e93f748c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e93f72db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e93f3dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e93f3dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6e82e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6e82e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6e82e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e93f3dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c (2652 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willretur # | ... # `---data was truncated (10240/20190) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e2017815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e201750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e2017889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c49849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c49849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c49831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e2010de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e2010dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e200f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e1fda20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e1fda1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c49832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c498330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e1fda1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c (2653 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , a # | ... # `---data was truncated (10240/98149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a0360a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a036070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a0360a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f83ab933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f83ab98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f83ab933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f83ab91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a0359fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a0359fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a03584b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a032340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a03233dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f83ab91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f83ab91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f83ab91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a03233cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c (2654 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32mf2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.f16.nxv1f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m1( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.f16.nxv2f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m2( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.f16.nxv4f16.i64(, half, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_f32m4( %vd, half noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca half, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store half %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load half, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.f16.nxv8f16.i64( %0, half %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.f16.nx # | ... # `---data was truncated (10240/90875) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3ff89115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3ff88e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a3ff89189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6072649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f60726a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6072649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6072631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ff826e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a3ff826c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a3ff80bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3ff4bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3ff4badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6072632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f60726330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f60726330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ff4bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c (2655 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f52a3b315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f52a3b00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f52a3b389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe8af305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe8af35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe8af305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe8af2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f52a348e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f52a348c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f52a32db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f529fdd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f529fdcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe8af2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe8af2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe8af2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f529fdccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c (2656 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sig1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sig1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum0(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum0(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @sha512sum1(i64 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | %1 = load i64, ptr %__x.addr.i, align 8 # | %2 = call i64 @llvm.riscv.sha512sum1(i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sig1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum0(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @sha256sum1(i32 noundef signext %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sig1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum0(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.sha512sum1(i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055766587b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005576658780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055766587b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa365f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa365f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa365f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa365f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557665810e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557665810c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005576657f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005576654a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005576654a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa365f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa365f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa365f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005576654a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c -check-prefix=RV64ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c (2657 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv1i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv2i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv4i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv8i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3c_vi_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3c.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3c.nxv16i32.i64.i64(, , i64 immarg, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf6d40f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf6d40c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf6d40f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f178e533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f178e58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f178e533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f178e51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf6d3a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf6d3a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf6d389b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf6d0390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf6d038dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f178e51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f178e51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f178e51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf6d038cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c (2658 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | # | ... # `---data was truncated (10240/169917) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055646360a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005564636070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055646360a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb596d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb596d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb596d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb596d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055646359fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055646359fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556463584b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005564632340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556463233dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb596d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb596d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb596d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556463233cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c (2659 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i32.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i32.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf4_i32m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i32.nxv4 # | ... # `---data was truncated (10240/17503) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607e211f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005607e211c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005607e211f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ae1849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ae18a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ae1849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ae1831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607e20b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607e20b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607e2099b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607e1d490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607e1d48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ae1832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ae18330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ae18330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607e1d48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c (2660 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c (2661 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf4x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f16m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32mf2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m1x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f32m2x3(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg3ei32_v_f64m1x3(ptr noundef %base, %binde # | ... # `---data was truncated (10240/99754) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005567fd08115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005567fd07e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005567fd08189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a1bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a1bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a1bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a1bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005567fd016e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005567fd016c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005567fcffbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567fccab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005567fccaadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a1bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a1bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a1bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005567fccaacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c (2662 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005569a682a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005569a68270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005569a682a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b43d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b43d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b43d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b43d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005569a67bfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005569a67bfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005569a67a4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005569a64540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005569a6453dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b43d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b43d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b43d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005569a6453cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c (2663 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f5435815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557f543550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557f5435889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff703733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff70378a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff703733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff70371b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f542ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557f542edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557f542d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557f53f820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557f53f81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff70371cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff70371d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff70371d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f53f81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c (2664 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ee6e75215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ee6e74f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ee6e75289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d96133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d9618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d96133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d9611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ee6e6e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ee6e6e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ee6e6ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ee6e37c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ee6e37bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d9611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d9611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d9611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ee6e37bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c (2665 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d15463115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d15462e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d15463189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb037105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb03715c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb037105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb0370ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d1545c6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d1545c6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d1545abb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d15425b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d15425add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb0370eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb0370ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb0370ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d15425acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c (2666 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei64_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i # | ... # `---data was truncated (10240/82983) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055976028615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597602830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055976028689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f55bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f55bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f55bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f55bdb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055976021be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055976021bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559760200b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055975feb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055975feafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f55bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f55bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f55bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055975feafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c (2667 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = loa # | ... # `---data was truncated (10240/14529) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614cd20415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614cd2010f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005614cd20489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fe7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fe758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fe7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fe751b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614cd199e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005614cd199c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005614cd17eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005614cce2e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005614cce2ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9fe751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fe751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fe751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614cce2dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c (2668 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056450fb3715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056450fb340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056450fb3789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0139449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01394a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0139449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0139431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056450facce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056450faccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056450fab1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056450f7610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056450f760dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0139432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01394330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01394330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056450f760cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c (2669 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4891f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4891f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4891f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0ab649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0ab6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0ab649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0ab631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48918ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f48918ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f489173b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f488e230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f488e22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0ab632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0ab6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0ab6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f488e22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c (2670 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_m( %mask, %src, i64 noundef %vl) #0 { # | entr # | ... # `---data was truncated (10240/18361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561101b8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561101b8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561101b8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1c1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1c1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1c1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1c1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561101b22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561101b22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561101b07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005611017b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005611017b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1c1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1c1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1c1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005611017b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c (2671 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m4_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_f32m8_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16f32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32mf2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m1_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i32.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32ff_v_i32m2_tu( %maskedoff, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4i32.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 4 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.risc # | ... # `---data was truncated (10240/78164) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae46a0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae46a080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae46a0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f763f049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f763f0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f763f049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f763f031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae469a0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae469a0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae46985b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae466350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae46634dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f763f032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f763f0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f763f0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae46634cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c (2672 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsleu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsleu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c (2673 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056414bdf815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056414bdf50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056414bdf889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f94ec533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f94ec58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f94ec533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f94ec51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056414bd8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056414bd8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056414bd72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056414ba220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056414ba21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f94ec51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f94ec51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f94ec51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056414ba21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c (2674 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv2i8.nxv2i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv4i8.nxv4i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv8i8.nxv8i16.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wv_i8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnsra_wx_i8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnsra.nxv16i8.nxv16i16.i64.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c (2675 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5cc11b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5cc1180f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b5cc11b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca2a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca2a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca2a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca2a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5cc0b0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b5cc0b0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5cc095b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5cbd450b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b5cbd44dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efca2a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca2a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca2a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5cbd44cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c (2676 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hsub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhsub.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhsub.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhsubq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vhsub.v4i32(<4 x i32> %0, <4 x i32> %.splat, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhsubq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hsub.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhsubq_m_n_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hsub.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, i32 1, <8 x i1> %4, <8 x i # | ... # `---data was truncated (10240/14644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604ee94c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604ee9490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604ee94c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d56933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d5698a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d56933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d5691b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604ee8e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604ee8e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604ee8c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604ee5760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604ee575dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d5691cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d5691d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d5691d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604ee575cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhsubq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c (2677 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055594c21a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055594c2170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055594c21a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe19b61bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe19b6725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe19b61ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe19b603507 abort ./stdlib/abort.c:85:3 # | #7 0x000055594c1afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055594c1afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055594c194b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055594be440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055594be43dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe19b604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe19b6050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe19b6050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055594be43cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c (2678 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca247b715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca247b40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca247b789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c34e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c34ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c34e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c34e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca2474ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca2474cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca24731b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca243e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca243e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c34e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c34e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c34e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca243e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c (2679 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Fu # | ... # `---data was truncated (10240/68429) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005619b15af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005619b15ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005619b15af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c7af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c7af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c7af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c7af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005619b1544e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005619b1544c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005619b1529b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005619b11d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005619b11d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c7af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c7af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c7af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005619b11d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c (2680 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m2( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv8bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m4( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv16bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m1_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv4bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv4bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m2_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv8bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv8bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vset_v_bf16m4_bf16m8( %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load , ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call @llvm.vector.insert.nxv32bf16.nxv16bf16( %0, %1, i64 0) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv32bf16.nxv16bf16(, , i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vset_v_bf16mf4_bf16mf4x2(target("riscv.vector.tuple", , 2) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 2) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 2), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 2) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_2t.nxv1bf16(target("riscv.vector.tuple", , 2), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vset_v_bf16mf4_bf16mf4x3(target("riscv.vector.tuple", , 3) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 3) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 3), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3) %0, %1, i32 0) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv2i8_3t.nxv1bf16(target("riscv.vector.tuple", , 3), , i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vset_v_bf16mf4_bf16mf4x4(target("riscv.vector.tuple", , 4) %dest, i64 noundef %index, %value) #0 { # | entry: # | %dest.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | store target("riscv.vector.tuple", , 4) %dest, ptr %dest.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | store %value, ptr %value.addr, align 2 # | %0 = load target("riscv.vector.tuple", , 4), ptr %dest.addr, align 2 # | %1 = load , ptr %value.addr, align 2 # | %2 = call target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c (2681 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16mf2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m1( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m2( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vv_i16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulsu_vx_i16m4( %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64( poison, %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(, , i8, i64) # | ... # `---data was truncated (10240/68437) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559baed7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559baed720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559baed7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4549849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45498a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4549849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4549831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559baed0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559baed0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559baecefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559bae99f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559bae99edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4549832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45498330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45498330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559bae99ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c (2682 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf4x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f16m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32mf2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f32m2x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei16_v_f64m1x4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0. # | ... # `---data was truncated (10240/87884) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5c5bab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5c5ba80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5c5bab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa42a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa42a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa42a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa42a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5c5b40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5c5b40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5c5b25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5c57d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5c57d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa42a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa42a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa42a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5c57d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c (2683 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = loa # | ... # `---data was truncated (10240/33443) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d4503615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d450330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d4503689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f258eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f258eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f258eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f258eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d44fcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d44fcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d44fb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d44c600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d44c5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f258eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f258eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f258eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d44c5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c (2684 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca targ # | ... # `---data was truncated (10240/11920) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005609aa8cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005609aa8cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005609aa8cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ec5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ec578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ec5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ec571b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005609aa864e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005609aa864c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005609aa849b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005609aa4f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005609aa4f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ec571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ec571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ec571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005609aa4f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c (2685 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv32i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv64i8.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | % # | ... # `---data was truncated (10240/21774) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559817e4815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559817e450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559817e4889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb04b933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb04b98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb04b933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb04b91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559817ddde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559817dddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559817dc2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559817a720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559817a71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb04b91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb04b91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb04b91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559817a71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c (2686 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsub_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.r # | ... # `---data was truncated (10240/65582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d040ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d040e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d040ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd3ccf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd3ccf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd3ccf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd3ccf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d0407fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d0407fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d04064b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d03d140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d03d13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd3ccf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd3ccf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd3ccf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d03d13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c (2687 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c820ea915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c820ea60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c820ea989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f768c849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f768c8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f768c849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f768c831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c820e3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c820e3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c820e23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c820ad30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c820ad2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f768c832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f768c8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f768c8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c820ad2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c (2688 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv8i8_3t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_f16m2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv16i8_3t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf4x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv2i8_3t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16mf2x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.mask.triscv.vector.tuple_nxv4i8_3t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16ff_v_i16m1x3_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tu # | ... # `---data was truncated (10240/17844) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562754fe315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562754fe00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562754fe389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd7e7d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd7e7d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd7e7d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd7e7d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562754f78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562754f78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562754f5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562754c0d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562754c0cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd7e7d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd7e7d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd7e7d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562754c0ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (2689 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c (2690 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b3aa6b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b3aa6b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b3aa6b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec40533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec4058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec40533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec4051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b3aa64ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b3aa64ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b3aa62fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b3aa2df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b3aa2dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec4051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec4051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec4051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b3aa2decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c (2691 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f16.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c (2692 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b1402a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561b140270f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561b1402a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8907733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f890778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8907733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f890771b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b13fbfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561b13fbfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561b13fa4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561b13c540b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561b13c53dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f890771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f890771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f890771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b13c53cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c (2693 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/12644) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce668e215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce668df0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce668e289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6fddf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6fddf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6fddf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6fddeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce66877e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce66877c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce6685cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce6650c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce6650bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6fddeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6fddeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6fddeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce6650bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c (2694 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsqr # | ... # `---data was truncated (10240/28170) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a83f39415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a83f3910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a83f39489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28de21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28de2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28de21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28de203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a83f329e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a83f329c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a83f30eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a83efbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a83efbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28de204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28de2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28de2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a83efbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c (2695 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a88d03815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a88d0350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a88d03889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14ce533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14ce58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14ce533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14ce51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a88cfcde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a88cfcdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a88cfb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a88cc620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a88cc61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14ce51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14ce51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14ce51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a88cc61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c (2696 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b3e26f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b3e26c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b3e26f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e7d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e7d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e7d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e7d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b3e204e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b3e204c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b3e1e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b3de990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b3de98dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7e7d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e7d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e7d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b3de98cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c (2697 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005621eb21e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005621eb21b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005621eb21e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec19733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec1978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec19733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec1971b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621eb1b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621eb1b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621eb198b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621eae480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005621eae47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec1971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec1971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec1971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005621eae47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c (2698 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfeq.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfeq_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfeq # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562471ecf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562471ecc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562471ecf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9187c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9187ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9187c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9187c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562471e64e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562471e64c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562471e49b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562471af90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562471af8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9187c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9187c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9187c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562471af8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c (2699 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d04791115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d04790e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d04791189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f69ccc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f69ccca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f69ccc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f69ccc31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0478a6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d0478a6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d04788bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d04753b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d04753add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f69ccc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f69ccc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f69ccc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d04753acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c (2700 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559aa070015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559aa06fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559aa070089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9b1e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9b1ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9b1e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9b1e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559aa0695e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559aa0695c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559aa067ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559aa032a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559aa0329dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9b1e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9b1e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9b1e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559aa0329cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c (2701 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4_tu( %maskedoff, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c (2702 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca # | ... # `---data was truncated (10240/43515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c1706d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c1706a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c1706d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2fa2b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2fa2b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2fa2b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2fa2aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c17002e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c17002c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c16fe7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c16c970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c16c96dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2fa2aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2fa2aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2fa2aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c16c96cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c (2703 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a2b8d8515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2b8d820f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a2b8d8589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba13333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba1338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba13333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba1331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a2b8d1ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a2b8d1ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a2b8cffb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a2b89af0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a2b89aedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fba1331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba1331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba1331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a2b89aecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c (2704 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c (2705 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccsu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c3d69d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c3d69a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c3d69d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb23e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb23e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb23e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb23e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c3d632e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c3d632c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c3d617b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c3d2c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c3d2c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb23e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb23e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb23e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c3d2c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c (2706 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | % # | ... # `---data was truncated (10240/18873) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8c92c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8c92c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8c92c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f630d305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f630d35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f630d305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f630d2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8c925de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8c925dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8c9242b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8c8ef20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8c8ef1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f630d2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f630d2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f630d2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8c8ef1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c (2707 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i8m8_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf4_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16mf2_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwredsum_vs_i16m1_i32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, ali # | ... # `---data was truncated (10240/43507) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0c7f6c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a0c7f690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a0c7f6c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb99d505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb99d55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb99d505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb99d4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0c7f01e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a0c7f01c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a0c7ee6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a0c7b960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a0c7b95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb99d4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb99d4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb99d4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0c7b95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c (2708 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c0502e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c0502b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c0502e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff2af133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff2af18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff2af133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff2af11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c04fc3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c04fc3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c04fa8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c04c580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c04c57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff2af11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff2af11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff2af11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c04c57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c (2709 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bcd9d8315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bcd9d800f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bcd9d8389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff8a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff8a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff8a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff8a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bcd9d18e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bcd9d18c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bcd9cfdb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bcd99ad0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bcd99acdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff8a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff8a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff8a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bcd99accc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c (2710 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf4_i8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16mf2_i8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m1_i8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m2_i8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m4_i8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_x_f_w_bf16m8_i8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf4_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16mf2_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m1_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m2_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m4_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16bf16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_xu_f_w_bf16m8_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llv # | ... # `---data was truncated (10240/59779) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc2044715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc204440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc2044789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa71649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa716a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa71649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa71631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc203dce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc203dcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc203c1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc200710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc20070dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa71632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa716330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa716330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc20070cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c (2711 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056055a6cd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056055a6ca0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056055a6cd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe61f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe61f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe61f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe61f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056055a662e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056055a662c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056055a647b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056055a2f70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056055a2f6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe61f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe61f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe61f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056055a2f6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c (2712 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c (2713 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync # | ... # `---data was truncated (10240/10618) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b98c5415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b98c510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b98c5489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1305c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1305ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1305c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1305c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b98be9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b98be9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b98bceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b9887e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b9887ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1305c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1305c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1305c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b9887dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c (2714 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec71ab215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec71aaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec71ab289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8f8049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8f80a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8f8049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8f8031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec71a47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec71a47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec71a2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec716dc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec716dbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd8f8032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8f80330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8f80330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec716dbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c (2715 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc half @test_vgetq_lane_f16(<8 x half> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = extractelement <8 x half> %0, i32 2 # | ret half %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc float @test_vgetq_lane_f32(<4 x float> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = extractelement <4 x float> %0, i32 3 # | ret float %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 4 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 0 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 0 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 10 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = extractelement <8 x i16> %0, i32 3 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = extractelement <4 x i32> %0, i32 3 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | store <2 x i64> %a, ptr %a.addr, align 8 # | %0 = load <2 x i64>, ptr %a.addr, align 8 # | %1 = extractelement <2 x i64> %0, i32 1 # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = extractelement <16 x i8> %0, i32 1 # | ret i8 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vsetq_lane_f16(half noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca <8 x half>, align 8 # | store half %a, ptr %a.addr, align 2 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %b.addr, align 8 # | %1 = load half, ptr %a.addr, align 2 # | %2 = insertelement <8 x half> %0, half %1, i32 4 # | ret <8 x half> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca float, align 4 # | %b.addr = alloca <4 x float>, align 8 # | store float %a, ptr %a.addr, align 4 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %b.addr, align 8 # | %1 = load float, ptr %a.addr, align 4 # | %2 = insertelement <4 x float> %0, float %1, i32 2 # | ret <4 x float> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 12 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 6 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 2 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 0 # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vsetq_lane_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %b.addr, align 8 # | %1 = load i8, ptr %a.addr, align 1 # | %2 = insertelement <16 x i8> %0, i8 %1, i32 2 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vsetq_lane_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %b.addr, align 8 # | %1 = load i16, ptr %a.addr, align 2 # | %2 = insertelement <8 x i16> %0, i16 %1, i32 7 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %b.addr, align 8 # | %1 = load i32, ptr %a.addr, align 4 # | %2 = insertelement <4 x i32> %0, i32 %1, i32 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | %0 = load <2 x i64>, ptr %b.addr, align 8 # | %1 = load i64, ptr %a.addr, align 8 # | %2 = insertelement <2 x i64> %0, i64 %1, i32 1 # | ret <2 x i64> %2 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x00005653d53ee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653d53eb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653d53ee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9b351b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005653d5383e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005653d5383c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005653d5368b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005653d50180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005653d5017dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe9b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9b351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005653d5017cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vorrq.c (2716 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vorrq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = or <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = or <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = or <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = or <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32 # | ... # `---data was truncated (10240/10897) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cd4fdc615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cd4fdc30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cd4fdc689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b3e333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b3e38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b3e333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b3e31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cd4fd5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cd4fd5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cd4fd40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cd4f9f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cd4f9efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b3e31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b3e31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b3e31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cd4f9efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vorrq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c (2717 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ad959f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ad959c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ad959f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd7cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd7cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd7cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd7cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ad9534e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ad9534c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ad9519b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ad91c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ad91c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd7cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd7cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd7cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ad91c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c (2718 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align # | ... # `---data was truncated (10240/19041) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555ea9f5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555ea9f550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555ea9f5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ef8133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ef818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ef8133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ef811b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555ea9eede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555ea9eedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555ea9ed2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555ea9b820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555ea9b81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ef811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ef811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ef811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555ea9b81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c (2719 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c2dbdb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c2dbd80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c2dbdb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ea4b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ea4b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ea4b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ea4b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c2db70e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c2db70c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c2db55b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c2d8050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c2d804dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ea4b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ea4b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ea4b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c2d804cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c (2720 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tupl # | ... # `---data was truncated (10240/53454) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b2045c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b204590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b2045c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5a5cc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5a5cca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5a5cc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5a5cc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b203f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b203f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b203d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b200860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b20085dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5a5cc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5a5cc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5a5cc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b20085cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c (2721 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdm.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdm_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdm.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a6c3b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a6c3b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a6c3b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d23f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d23f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d23f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d23f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a6c34ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a6c34ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a6c32fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a6bfdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a6bfdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d23f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d23f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d23f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a6bfdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c (2722 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f68397015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f68396d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f68397089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99e6249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99e62a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99e6249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99e6231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f683905e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f683905c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6838eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f68359a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f683599dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99e6232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99e62330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99e62330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f683599cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/thinlto-opaque-typed-mix.ll (2723 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-opaque-typed-mix.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 4 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-opaque-typed-mix.ll.tmp/typed.bc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-opaque-typed-mix.ll # | #0 0x0000557ae7a7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557ae7a6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557ae7a7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32ef249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32ef2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32ef249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32ef231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557ae7a07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557ae7a07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557ae79ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557ae769c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557ae769bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f32ef232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32ef2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32ef2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557ae769bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c (2724 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_u16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("ri # | ... # `---data was truncated (10240/47480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c70d3c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c70d390f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c70d3c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe54bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe54bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe54bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe54bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c70cd1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c70cd1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c70cb6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c709660b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c70965dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe54bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe54bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe54bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c70965cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c (2725 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv8f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv16f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv32f16.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsqrt.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff. # | ... # `---data was truncated (10240/128424) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056468da5615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056468da530f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056468da5689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ef1933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ef198a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ef1933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ef191b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056468d9ebe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056468d9ebc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056468d9d0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056468d6800b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056468d67fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ef191cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ef191d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ef191d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056468d67fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c (2726 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function # | ... # `---data was truncated (10240/12439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a4581dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a4581da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a4581dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd837533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd83758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd837533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd83751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a458172e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a458172c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a458157b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a457e070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a457e06dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd83751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd83751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd83751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a457e06cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c (2727 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | stor # | ... # `---data was truncated (10240/29518) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db43db315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db43db00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db43db389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa006533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa00658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa006533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa00651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db43d48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db43d48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db43d2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db439dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db439dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa00651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa00651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa00651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db439dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c (2728 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e74e14615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e74e1430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e74e14689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadd301bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadd30725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadd301ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadd3003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e74e0dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e74e0dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e74e0c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e74dd700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e74dd6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadd3004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadd30050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadd30050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e74dd6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c (2729 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055660fdf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055660fdee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055660fdf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb22a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb22a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb22a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb22a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055660fd86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055660fd86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055660fd6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055660fa1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055660fa1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb22a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb22a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb22a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055660fa1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c (2730 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv64i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv32i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv16i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv8i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv4i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv2i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmmv_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmand.nxv1i1.i64( %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmand.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555fd45e615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555fd45e30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555fd45e689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0af7449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0af74a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0af7449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0af7431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555fd457be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555fd457bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555fd4560b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555fd42100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555fd420fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0af7432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0af74330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0af74330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555fd420fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c (2731 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_tumu( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556263a4f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556263a4c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556263a4f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbfa5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbfa598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbfa5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbfa591b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005562639e4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005562639e4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005562639c9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005562636790b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556263678dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbfa591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbfa591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbfa591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556263678cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c (2732 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv4bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64( poison, %1, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.mask.nxv8bf16.nxv8bf16.i64(, , # | ... # `---data was truncated (10240/13290) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db7d43515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db7d4320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db7d43589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1cd9a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1cd9a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1cd9a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1cd9a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db7d3cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db7d3cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db7d3afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db7d05f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db7d05edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1cd9a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1cd9a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1cd9a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db7d05ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c (2733 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eadb8bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eadb8b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eadb8bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8860533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f886058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8860533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f886051b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eadb850e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eadb850c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eadb835b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eadb4e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eadb4e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f886051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f886051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f886051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eadb4e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c (2734 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5ab9cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5ab9cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5ab9cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07f3449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07f34a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07f3449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07f3431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5ab964e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5ab964c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5ab949b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5ab5f90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5ab5f8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f07f3432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07f34330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07f34330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5ab5f8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c (2735 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv16f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv16f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f16m8_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv32f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv32f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32mf2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv1f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv1f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m1_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 4 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfrsub.nxv2f32.f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsub.nxv2f32.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsub_vf_f32m2_tu( %maskedoff, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = all # | ... # `---data was truncated (10240/147390) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563bfe89415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563bfe8910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563bfe89489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f38ace49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f38acea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f38ace49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38ace31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563bfe829e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563bfe829c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563bfe80eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563bfe4be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563bfe4bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f38ace32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38ace330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38ace330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563bfe4bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c (2736 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %o # | ... # `---data was truncated (10240/29054) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644511ea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644511e70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644511ea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7137933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f713798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7137933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f713791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056445117fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056445117fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564451164b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564450e140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564450e13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f713791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f713791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f713791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564450e13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c (2737 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055905cedf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055905cedc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055905cedf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a12449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a124a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a12449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a12431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055905ce74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055905ce74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055905ce59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055905cb090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055905cb08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a12432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a124330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a124330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055905cb08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c (2738 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @ll # | ... # `---data was truncated (10240/20090) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d8aab015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d8aaad0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d8aab089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f28e7049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f28e70a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f28e7049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f28e7031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d8aa45e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d8aa45c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d8aa2ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d8a6da0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d8a6d9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f28e7032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f28e70330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f28e70330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d8a6d9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c (2739 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_bf16m1x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056023742b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602374280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056023742b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f76d6b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76d6b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f76d6b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f76d6b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602373c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602373c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602373a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602370550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560237054dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f76d6b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76d6b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76d6b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560237054cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c (2740 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005597e5f5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005597e5f4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005597e5f5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb7a5b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb7a5b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb7a5b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb7a5aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005597e5ee7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005597e5ee7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005597e5eccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005597e5b7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005597e5b7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb7a5aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb7a5aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb7a5aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005597e5b7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c (2741 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555dc7a9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555dc7a940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555dc7a9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9c2333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9c238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9c2333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9c231b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555dc7a2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555dc7a2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555dc7a11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555dc76c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555dc76c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9c231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9c231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9c231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555dc76c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c (2742 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv32f16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i16.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | cal # | ... # `---data was truncated (10240/39578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6f4f3b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6f4f380f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6f4f3b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9681d05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9681d5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9681d05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9681ced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c6f4ed0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c6f4ed0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c6f4eb5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6f4b650b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c6f4b64dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9681ceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9681cef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9681cef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c6f4b64cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c (2743 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_i64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_u64m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs # | ... # `---data was truncated (10240/15978) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f33486c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3348690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f33486c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9d83133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9d8318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9d83133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9d8311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f334801e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f334801c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f3347e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f3344960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f334495dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9d8311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9d8311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9d8311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f334495cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminvq.c (2744 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminvq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vminvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vminvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i8 @test_vmaxvq_s8(i8 noundef signext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 0) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v16i8(i32, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc signext i16 @test_vmaxvq_s16(i16 noundef signext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 0) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v8i16(i32, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxv.v4i32(i32, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxvq_u8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v16i8(i32 %1, <16 x i8> %2, i32 1) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxvq_u16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxv.v8i16(i32 %1, <8 x i16> %2, i32 1) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vmaxvq_u32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.maxv.v4i32(i32 %0, <4 x i32> %1, i32 1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vminavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vminavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.minav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v8i16(i32, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc i32 @test_vminavq_s32(i32 noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca <4 x i32>, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call i32 @llvm.arm.mve.minav.v4i32(i32 %0, <4 x i32> %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.minav.v4i32(i32, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i8 @test_vmaxavq_s8(i8 noundef zeroext %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca i8, align 1 # | %b.addr = alloca <16 x i8>, align 8 # | store i8 %a, ptr %a.addr, align 1 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load i8, ptr %a.addr, align 1 # | %1 = zext i8 %0 to i32 # | %2 = load <16 x i8>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v16i8(i32 %1, <16 x i8> %2) # | %4 = trunc i32 %3 to i8 # | ret i8 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.maxav.v16i8(i32, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vmaxavq_s16(i16 noundef zeroext %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | %b.addr = alloca <8 x i16>, align 8 # | store i16 %a, ptr %a.addr, align 2 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = load <8 x i16>, ptr %b.addr, align 8 # | %3 = call i32 @llvm.arm.mve.maxav.v8i16(i32 %1, <8 x i16> %2) # | %4 = trunc i32 %3 to i16 # | ret i16 # | ... # `---data was truncated (10240/39417) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000564d6cce615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d6cce30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d6cce689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde1161bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde116725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde1161ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde11603507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d6cc7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d6cc7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d6cc60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d6c9100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d6c90fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde11604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde116050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde116050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d6c90fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c (2745 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | s # | ... # `---data was truncated (10240/24381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563a20ac915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563a20ac60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563a20ac989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0aaab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0aaab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0aaab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0aaaaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563a20a5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563a20a5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563a20a43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563a206f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563a206f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0aaaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0aaaaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0aaaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563a206f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c (2746 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, targe # | ... # `---data was truncated (10240/70394) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055744a34e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055744a34b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055744a34e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa170c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa170ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa170c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa170c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055744a2e3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055744a2e3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055744a2c8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557449f780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557449f77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa170c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa170c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa170c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557449f77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c (2747 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a26728715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a2672840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a26728789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ba5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ba598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ba5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ba591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a26721ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a26721cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a267201b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a266eb10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a266eb0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ba591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ba591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ba591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a266eb0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c (2748 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv8bf16.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c (2749 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056127ba5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056127ba4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056127ba5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f425a01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f425a0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f425a01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f425a003507 abort ./stdlib/abort.c:85:3 # | #7 0x000056127b9e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056127b9e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056127b9cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056127b67a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056127b679dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f425a004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f425a0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f425a0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056127b679cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c (2750 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv1f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv1f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wv_f32m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_wf_f32m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.w.nxv2f32.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.w.nxv2f32.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vv_f32m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwsub_vf_f32m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2 # | ... # `---data was truncated (10240/151911) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fff492515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fff49220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fff492589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f09a7249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f09a72a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f09a7249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f09a7231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fff48bae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fff48bac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fff489fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fff454f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fff454edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f09a7232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f09a72330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f09a72330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fff454ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c (2751 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf4_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16mf2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m1_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vx_u16m2_tu( %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmulu_vv_u16m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , # | ... # `---data was truncated (10240/154207) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559864f2515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559864f220f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559864f2589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cc5733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cc578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cc5733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cc571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559864ebae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559864ebac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559864e9fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559864b4f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559864b4edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3cc571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cc571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cc571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559864b4ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c (2752 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store targ # | ... # `---data was truncated (10240/14667) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba741c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba741c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba741c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feb19d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feb19d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feb19d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feb19d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba7415ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba7415ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba7413fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba73def0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba73deedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feb19d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feb19d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feb19d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba73deecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c (2753 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmflt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c (2754 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 0, i64 %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 immarg, i64 immarg, i64 immarg, i64, i64 immarg, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 1, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 2, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.x.se.i64.i64.i64(i64 3, i64 31, i64 31, i64 %0, i64 64, i64 3, i64 %1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_se_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m1(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m2(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m4(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_x_u64m8(i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 immarg, i64 immarg, i64, i64) #2 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvcp,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nounwind } # | attributes #2 = { nounwind memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvcp1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005589ded5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005589ded4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005589ded5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f094f533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f094f58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f094f533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f094f51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005589dece5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005589dece5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005589deccab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005589de97a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005589de979dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f094f51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f094f51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f094f51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005589de979cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c (2755 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_f32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_i32m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e32_v_u32m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/26984) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fd4c55415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fd4c5510f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fd4c55489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5f6333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5f638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5f6333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5f631b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fd4c4e9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fd4c4e9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fd4c4ceb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fd4c17e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fd4c17ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb5f631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5f631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5f631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fd4c17dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c (2756 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555acf8da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555acf8d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555acf8da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f43faa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f43faaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f43faa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f43faa31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555acf86fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555acf86fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555acf854b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555acf5040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555acf503dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f43faa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f43faa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f43faa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555acf503cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c (2757 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c2119d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c2119d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c2119d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd429733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd42978a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd429733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd42971b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c21196ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c21196cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c211951b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c2116010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c211600dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd42971cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd42971d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd42971d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c211600cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c (2758 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vect # | ... # `---data was truncated (10240/31946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602778d815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602778d50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602778d889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f722c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f722c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f722c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f722c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056027786de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056027786dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560277852b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602775020b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560277501dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f722c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f722c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f722c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560277501cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c (2759 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557aba97615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557aba9730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557aba97689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3045a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3045aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3045a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3045a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557aba90be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557aba90bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557aba8f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557aba5a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557aba59fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3045a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3045a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3045a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557aba59fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c (2760 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f48388815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4838850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f48388889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf03333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf0338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf03333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf0331b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f48381de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f48381dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f483802b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4834b20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4834b1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf0331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf0331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf0331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4834b1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c (2761 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f03991e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f03991b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f03991e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb1a6d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb1a6d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb1a6d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb1a6d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0398b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0398b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f039898b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0395480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f039547dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb1a6d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb1a6d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb1a6d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f039547cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c (2762 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv # | ... # `---data was truncated (10240/25519) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055730124a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573012470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055730124a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe051849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0518a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe051849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe051831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573011dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005573011dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005573011c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557300e740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557300e73dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe051832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0518330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0518330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557300e73cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c (2763 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_f32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_i32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32mf2x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32ff_v_u32m1x8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv8i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a3fd2415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a3fd210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a3fd2489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c27b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c27b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c27b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c27b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a3fcb9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a3fcb9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a3fc9eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a3f94e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a3f94ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c27b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c27b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c27b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a3f94dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c (2764 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_u64m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_f64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m1x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e64_v_i64m2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 # | ... # `---data was truncated (10240/14036) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c77fd015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561c77fcd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561c77fd089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb5eab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5eab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb5eab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb5eaaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c77f65e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561c77f65c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561c77f4ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561c77bfa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561c77bf9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb5eaaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5eaaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5eaaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c77bf9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c (2765 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei16_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055747ffac15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055747ffa90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055747ffac89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f843bd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f843bd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f843bd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f843bced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055747ff41e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055747ff41c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055747ff26b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055747fbd60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055747fbd5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f843bceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f843bcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f843bcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055747fbd5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c (2766 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 2) %6 # | # | ... # `---data was truncated (10240/34641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a87d62715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a87d6240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a87d62789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f29e3933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29e398a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f29e3933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f29e391b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a87d5bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a87d5bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a87d5a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a87d2510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a87d250dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f29e391cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29e391d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29e391d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a87d250cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c (2767 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff # | ... # `---data was truncated (10240/54702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557cb5cb715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557cb5cb40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557cb5cb789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f40cfc49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f40cfca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f40cfc49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f40cfc31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557cb5c4ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557cb5c4cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557cb5c31b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557cb58e10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557cb58e0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f40cfc32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f40cfc330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f40cfc330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557cb58e0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c (2768 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005583c78f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583c78f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005583c78f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fad28649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fad286a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fad28649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fad28631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583c788de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583c788dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583c7872b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583c75220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005583c7521dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fad28632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fad286330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fad286330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005583c7521cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c (2769 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vloxseg3ei8_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c (2770 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f6db54d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6db54a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f6db54d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc2a6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc2a618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc2a6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc2a611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f6db4e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f6db4e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f6db4c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f6db1770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f6db176dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc2a611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc2a611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc2a611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f6db176cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c (2771 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple" # | ... # `---data was truncated (10240/35929) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005566b4fb515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005566b4fb20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005566b4fb589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1964b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1964b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1964b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1964b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005566b4f4ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005566b4f4ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005566b4f2fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566b4bdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566b4bdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1964b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1964b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1964b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566b4bdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c (2772 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_i32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_u32m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32ff_v_f32mf2x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f93037015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f93036d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f93037089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5eea905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5eea95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5eea905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5eea8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f930305e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f930305c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f9302eab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f92ff9a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f92ff99dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5eea8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5eea8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5eea8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f92ff99cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp (2773 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +f -target-feature +d -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vget_v_i8m2_i8m1u14__rvv_int8m2_t( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | %1 = call @llvm.vector.extract.nxv8i8.nxv16i8( %0, i64 8) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8i8.nxv16i8(, i64 immarg) #1 # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(2,1024) # | define dso_local @_Z21test_vset_v_i8m1_i8m2u14__rvv_int8m2_tu14__rvv_int8m1_t( %dest, %val) #0 { # | entry: # | %dest.addr = alloca , align 1 # | %val.addr = alloca , align 1 # | store %dest, ptr %dest.addr, align 1 # | store %val, ptr %val.addr, align 1 # | %0 = load , ptr %dest.addr, align 1 # | %1 = load , ptr %val.addr, align 1 # | %2 = call @llvm.vector.insert.nxv16i8.nxv8i8( %0, %1, i64 8) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv16i8.nxv8i8(, , i64 immarg) #1 # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bafbf0b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bafbf080f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bafbf0b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f46e6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f46e6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f46e6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46e6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bafbea0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bafbea0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bafbe85b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bafbb350b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bafbb34dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f46e6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46e6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46e6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bafbb34cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c (2774 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1bf16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2bf16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4bf16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8bf16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16bf16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | # | ... # `---data was truncated (10240/23255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d334ca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d334c70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d334ca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f506f21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f506f2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f506f21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f506f203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d3345fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d3345fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d33444b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d330f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d330f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f506f204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f506f2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f506f2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d330f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c (2775 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d10e1c915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d10e1c60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d10e1c989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f856921bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85692725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f856921ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8569203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d10e15ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d10e15ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d10e143b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d10ddf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d10ddf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8569204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85692050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85692050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d10ddf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c (2776 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv1bf16.nxv1f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16mf2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv2bf16.nxv2f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m1_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv4bf16.nxv4f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m2_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv8bf16.nxv8f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfncvt_bf16_s_bf16m4_rm( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.nds.vfncvt.bf16.s.nxv16bf16.nxv16f32.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556e7389715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556e738940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556e7389789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0fd049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0fd0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0fd049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0fd031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e7382ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556e7382cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556e73811b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556e734c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556e734c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0fd032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0fd0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0fd0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e734c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c (2777 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsqrt_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsqrt.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsqrt.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f7f168915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f7f16860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f7f168989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc856133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc85618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc856133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc85611b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f7f161ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f7f161ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f7f1603b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f7f12b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f7f12b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc85611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc85611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc85611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f7f12b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c (2778 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056196a5db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056196a5d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056196a5db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4fcd705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4fcd75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4fcd705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4fcd6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056196a570e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056196a570c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056196a555b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056196a2050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056196a204dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4fcd6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4fcd6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4fcd6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056196a204cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c (2779 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005627f396e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627f396b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005627f396e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa2aae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa2aaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa2aae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa2aae31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005627f3903e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005627f3903c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005627f38e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627f35980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627f3597dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa2aae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa2aae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa2aae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627f3597cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c (2780 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4 # | ... # `---data was truncated (10240/12740) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005649b4f1c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005649b4f190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005649b4f1c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd4f1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd4f178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd4f1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd4f171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005649b4eb1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005649b4eb1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005649b4e96b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005649b4b460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005649b4b45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd4f171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd4f171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd4f171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005649b4b45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c (2781 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv2bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv4bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv8bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv16bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.nxv32bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv2bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv4bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzip.mask.nxv8bf16.nxv4bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vzip_vv_bf16m4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c (2782 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | % # | ... # `---data was truncated (10240/14613) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d48bb9715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d48bb940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d48bb9789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48c3f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48c3f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48c3f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48c3f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d48bb2ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d48bb2cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d48bb11b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d48b7c10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d48b7c0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48c3f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48c3f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48c3f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d48b7c0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c (2783 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f16m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32mf2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f32.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f32.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4f32.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f32m4(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8f32.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m1(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1f64.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vloxei64_v_f64m2(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2f64.p0.nxv2i64.i64(, ptr # | ... # `---data was truncated (10240/91267) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056310b76e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056310b76b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056310b76e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc41ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc41ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc41ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc41ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056310b703e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056310b703c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056310b6e8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056310b3980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056310b397dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc41ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc41ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc41ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056310b397cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c (2784 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m8(ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32bf16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv1bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16mf2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv2bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m1_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv4bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m2_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.mask.nxv8bf16.p0.i64( %2, ptr %1, %0, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.mask.nxv8bf16.p0.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vse16_v_bf16m4_m( %vm, ptr noundef %rs1, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/12652) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055743a1f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055743a1ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055743a1f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a61c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a61ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a61c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a61c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055743a186e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055743a186c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055743a16bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557439e1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557439e1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a61c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a61c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a61c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557439e1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c (2785 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwnmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwnmsac # | ... # `---data was truncated (10240/51796) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e3b8d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559e3b8d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559e3b8d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f741ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f741aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f741ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f741ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e3b86ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559e3b86ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559e3b853b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559e3b5030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559e3b502dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f741ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f741ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f741ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e3b502cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c (2786 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vghsh_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vghsh.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b46b0de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b46b0db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b46b0de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1d51f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1d51f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1d51f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1d51f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b46b073e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b46b073c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b46b058b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b46ad080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b46ad07dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1d51f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1d51f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1d51f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b46ad07cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c (2787 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e64_v_f64m1x6_tumu( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.ve # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563cb634615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563cb63430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563cb634689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe76a333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe76a38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe76a333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe76a31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563cb62dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563cb62dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563cb62c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563cb5f700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563cb5f6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe76a31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe76a31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe76a31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563cb5f6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c (2788 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-feature # | ... # `---data was truncated (10240/10692) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562151a3a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562151a370f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562151a3a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c4d849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c4d8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c4d849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c4d831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005621519cfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005621519cfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005621519b4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621516640b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562151663dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c4d832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c4d8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c4d8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562151663cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c (2789 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8f64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i64.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,10 # | ... # `---data was truncated (10240/48393) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0ae7c415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0ae7c10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0ae7c489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5d4841bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5d484725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5d4841ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5d48403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f0ae759e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f0ae759c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f0ae73eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0ae3ee0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f0ae3eddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5d48404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5d484050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5d484050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f0ae3edcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c (2790 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.v # | ... # `---data was truncated (10240/20439) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562ea194815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562ea19450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562ea194889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7175449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71754a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7175449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7175431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562ea18dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562ea18ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562ea18c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562ea15720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562ea1571dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7175432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71754330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71754330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562ea1571cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c (2791 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg5ei8_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056404cd0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056404cd040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056404cd0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0c8449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0c84a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0c8449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0c8431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056404cc9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056404cc9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056404cc81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056404c9310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056404c930dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd0c8432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0c84330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0c84330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056404c930cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c (2792 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u8m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vabd.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vabd.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vabs_v_u16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c (2793 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ea957b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ea957b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ea957b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff0b2705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff0b275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff0b2705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff0b26ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ea9574ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ea9574ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ea9572fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ea953df0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ea953dedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff0b26eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff0b26ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff0b26ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ea953decc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c (2794 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c (2795 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ae6e21e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ae6e21b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ae6e21e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd074b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd074b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd074b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd074b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ae6e1b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ae6e1b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ae6e198b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ae6de480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ae6de47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd074b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd074b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd074b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ae6de47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c (2796 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dots_vv_i64m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dots.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dots.nxv4 # | ... # `---data was truncated (10240/47636) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aebd06615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aebd0630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aebd06689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3669533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f366958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3669533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f366951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aebcffbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aebcffbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aebcfe0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aebcc900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aebcc8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f366951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f366951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f366951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aebcc8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c (2797 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaeskf1_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaeskf1.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaeskf1.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f98b0b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f98b0b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f98b0b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8af9f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8af9f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8af9f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8af9f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f98b04be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f98b04bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f98b030b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f98ace00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f98acdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8af9f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8af9f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8af9f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f98acdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c (2798 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( poison, %0, i8 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv8i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vrsub.nxv16i16.i16.i64( poison, %0, i16 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = c # | ... # `---data was truncated (10240/41433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555606ef815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555606ef50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555606ef889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d3c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d3c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d3c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d3c431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555606e8de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555606e8dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555606e72b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555606b220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555606b21dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2d3c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d3c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d3c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555606b21cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c (2799 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf8( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.nxv1i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf8( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv1i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf4( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.nxv2i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf4( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv2i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8mf2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.nxv4i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8mf2( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv4i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m1( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.nxv8i8.i64( poison, %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vxm_i8m1( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vadc.nxv8i8.i8.i64( poison, %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vadc.nxv8i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vadc_vvm_i8m2( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/98141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005636d366c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005636d36690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005636d366c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd81333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd8138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd81333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd8131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005636d3601e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005636d3601c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005636d35e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005636d32960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005636d3295dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd8131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd8131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd8131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005636d3295cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c (2800 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565555ef715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565555ef40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565555ef789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efea3049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efea30a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efea3049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efea3031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565555e8ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565555e8cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565555e71b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565555b210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565555b20dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efea3032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efea30330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efea30330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565555b20cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c (2801 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm # | ... # `---data was truncated (10240/53200) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556c8f24015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556c8f23d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556c8f24089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe273333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe27338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe273333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe27331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556c8f1d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556c8f1d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556c8f1bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556c8ee6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556c8ee69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe27331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe27331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe27331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556c8ee69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c (2802 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32mf2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m1_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m2_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vv_f32m4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmul_vf_f32m4_tu( %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load half, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16.i64( %0, %1, half %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofre # | ... # `---data was truncated (10240/183431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559546dc915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559546dc60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559546dc989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a6701bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a670725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a6701ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a67003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559546d5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559546d5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559546d43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595469f30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595469f2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2a67004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a670050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a670050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595469f2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c (2803 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %0, <8 x half> %1) # | ret <8 x half> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %0, <4 x float> %1) # | ret <4 x float> %2 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x half>, ptr %inactive.addr, align 8 # | %6 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> %5) # | ret <8 x half> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> noundef %inactive, <4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x float>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %inactive, ptr %inactive.addr, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x float>, ptr %inactive.addr, align 8 # | %6 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> %5) # | ret <4 x float> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, i32 0, <8 x i1> %4, <8 x half> undef) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, i32 0, <4 x i1> %4, <4 x float> undef) # | ret <4 x float> %5 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a44c4e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a44c4b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a44c4e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf78c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf78ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf78c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf78c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a44be3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a44be3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a44bc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a448780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a44877dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf78c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf78c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf78c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a44877cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c (2804 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a37ffbb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a37ffb80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a37ffbb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd663c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd663c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd663c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd663c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a37ff50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a37ff50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a37ff35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a37fbe50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a37fbe4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd663c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd663c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd663c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a37fbe4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c (2805 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32esmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32esmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32esmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f380b6915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f380b660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f380b6989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f421d533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f421d58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f421d533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f421d51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f380afee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f380afec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f380ae3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f3807930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f380792dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f421d51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f421d51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f421d51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f380792cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c -check-prefix=RV32ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c (2806 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf8_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf8_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv1i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf4_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf4_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv2i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8mf2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8mf2_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv4i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m1_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %shift.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vx_u8m1_tu( %maskedoff, %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %shift.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsrl.nxv8i8.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsrl.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsrl_vv_u8m2_tu( %maskedoff, %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vandq.c (2807 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vandq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = and <16 x i8> %0, %1 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = and <8 x i16> %0, %1 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = and <4 x i32> %0, %1 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = and <4 x i32> %1, %3 # | %5 = bitcast <4 x i32> %4 to <4 x float> # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %5) # | %7 = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x # | ... # `---data was truncated (10240/10901) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055961600f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055961600c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055961600f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8622933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f862298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8622933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f862291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559615fa4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559615fa4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559615f89b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559615c390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559615c38dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f862291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f862291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f862291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559615c38cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vandq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c (2808 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c (2809 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | ... # `---data was truncated (10240/34356) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055920c5f815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055920c5f50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055920c5f889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8d12b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8d12b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8d12b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8d12b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055920c58de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055920c58dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055920c572b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055920c2220b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055920c221dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8d12b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8d12b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8d12b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055920c221cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/idup.c (2810 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/idup.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %0, i32 4) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %0, i32 1) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %0, i32 4) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_n_u8(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %0, i32 2) # | %2 = extractvalue { <16 x i8>, i32 } %1, 0 # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_n_u16(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %0, i32 4) # | %2 = extractvalue { <8 x i16>, i32 } %1, 0 # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_n_u32(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %0, i32 2) # | %2 = extractvalue { <4 x i32>, i32 } %1, 0 # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_viwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.viwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_viwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32 %0, i32 %1, i32 2) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.viwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_viwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.viwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vdwdupq_n_u8(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32 %0, i32 %1, i32 4) # | %3 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <16 x i8>, i32 } @llvm.arm.mve.vdwdup.v16i8(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vdwdupq_n_u16(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32 %0, i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <8 x i16>, i32 } @llvm.arm.mve.vdwdup.v8i16(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vdwdupq_n_u32(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32 %0, i32 %1, i32 1) # | %3 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare { <4 x i32>, i32 } @llvm.arm.mve.vdwdup.v4i32(i32, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vidupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vidup.v16i8(i32 %1, i32 8) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vidupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vidup.v8i16(i32 %1, i32 1) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vidupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 %1, i32 4) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vddupq_wb_u8(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <16 x i8>, i32 } @llvm.arm.mve.vddup.v16i8(i32 %1, i32 2) # | %3 = extractvalue { <16 x i8>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <16 x i8>, i32 } %2, 0 # | ret <16 x i8> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vddupq_wb_u16(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %1, i32 8) # | %3 = extractvalue { <8 x i16>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <8 x i16>, i32 } %2, 0 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vddupq_wb_u32(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load i32, ptr %0, align 4 # | %2 = call { <4 x i32>, i32 } @llvm.arm.mve.vddup.v4i32(i32 %1, i32 2) # | %3 = extractvalue { <4 x i32>, i32 } %2, 1 # | store i32 %3, ptr %0, align 4 # | %4 = extractvalue { <4 x i32>, i32 } %2, 0 # | ret <4 x i3 # | ... # `---data was truncated (10240/57708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556117d2115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556117d1e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556117d2189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4796b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4796b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4796b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4796aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556117cb6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556117cb6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556117c9bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055611794b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055611794add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4796aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4796aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4796aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055611794acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/idup.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c (2811 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056521777d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056521777a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056521777d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6798533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f679858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6798533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f679851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565217712e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565217712c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005652176f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005652173a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005652173a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f679851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f679851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f679851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652173a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c (2812 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | # | ... # `---data was truncated (10240/31868) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a50fdbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a50fdbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a50fdbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9897e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9897e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9897e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9897e03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a50fd53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a50fd53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a50fd38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a50f9e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a50f9e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9897e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9897e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9897e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a50f9e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c (2813 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562bae4df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562bae4dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562bae4df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4512705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f451275c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4512705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45126ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562bae474e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562bae474c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562bae459b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562bae1090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562bae108dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f45126eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45126ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45126ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562bae108cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c (2814 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffb.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i64, align 8 # | %__b.addr.i = alloca i64, align 8 # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | store i64 %0, ptr %__a.addr.i, align 8 # | store i64 %1, ptr %__b.addr.i, align 8 # | %2 = load i64, ptr %__a.addr.i, align 8 # | %3 = load i64, ptr %__b.addr.i, align 8 # | %4 = call i64 @llvm.riscv.nds.flmism.i64(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd7eb1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd7eb0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd7eb1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f3b333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f3b38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f3b333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f3b31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd7eaa7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd7eaa7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd7ea8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd7e73c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd7e73bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f3b31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f3b31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f3b31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd7e73bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c (2815 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8_tu( %maskedoff, half noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load half, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load float, ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( %0, float %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8_tu( %maskedoff, float noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c (2816 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f16m4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei8_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/128444) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561eb353515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561eb35320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561eb353589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f645ae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f645aea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f645ae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f645ae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561eb34cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561eb34cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561eb34afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561eb315f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561eb315edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f645ae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f645ae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f645ae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561eb315ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c (2817 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559c82a7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559c82a6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559c82a7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f156bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f156bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f156bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f156bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559c82a07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559c82a07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559c829ecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559c8269c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559c8269bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f156bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f156bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f156bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559c8269bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c (2818 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei8_v_bf16m1x # | ... # `---data was truncated (10240/25695) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bd8591e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bd8591b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bd8591e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe099305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe09935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe099305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0992ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bd858b3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bd858b3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bd85898b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bd855480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bd85547dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0992eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0992ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0992ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bd85547cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c (2819 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb9c24515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb9c2420f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb9c24589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f950ac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f950aca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f950ac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f950ac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb9c1dae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb9c1dac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb9c1bfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb9be6f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb9be6edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f950ac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f950ac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f950ac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb9be6ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c (2820 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf4x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv2i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16mf2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv4i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m1x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16ff_v_bf16m2x4_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055611af0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055611af070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055611af0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3732933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f373298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3732933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f373291b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055611ae9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055611ae9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055611ae84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055611ab340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055611ab33dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f373291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f373291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f373291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055611ab33cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c (2821 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m1_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m2_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3m4_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf8_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv1bf16.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf4_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.mask.nxv2bf16.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f8e4m3mf2_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4bf16.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/53686) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de6567115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055de6566e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055de6567189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f732bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f732bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f732bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f732bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de65606e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055de65606c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055de655ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055de6529b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055de6529add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f732bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f732bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f732bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de6529acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c (2822 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv1f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv1f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv2f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv2f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv4f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv4f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv8f16.f16.i64( poison, %0, half %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv8f16.f16.i64(, , half, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfdiv_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfdiv.nxv16f16.f16.i64( poison, %0, half %1, i # | ... # `---data was truncated (10240/125641) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d270b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d270b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d270b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2dd3a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2dd3aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2dd3a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2dd3a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d2704de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d2704dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d27032b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d26ce20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d26ce1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2dd3a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2dd3a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2dd3a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d26ce1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c (2823 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ta # | ... # `---data was truncated (10240/47488) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565253fd915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565253fd60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565253fd989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd4e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd4e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd4e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd4e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565253f6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565253f6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565253f53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565253c030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565253c02dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd4e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd4e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd4e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565253c02cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-neon-directed-rounding-constrained.c (2824 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-directed-rounding-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x float> @test_vrndi_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vrndi_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vrndi_v1.i = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %vrndi_v.i) # | store <2 x float> %vrndi_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %2, ptr %__ret.i, align 8 # | %3 = load <2 x float>, ptr %__ret.i, align 8 # | ret <2 x float> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x float> @test_vrndiq_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vrndiq_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vrndiq_v1.i = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %vrndiq_v.i) # | store <4 x float> %vrndiq_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %2, ptr %__ret.i, align 8 # | %3 = load <4 x float>, ptr %__ret.i, align 8 # | ret <4 x float> %3 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1 # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a57" "target-features"="+aes,+armv8-a,+crc,+d32,+dsp,+fp-armv8,+fp-armv8d16,+fp-armv8d16sp,+fp-armv8sp,+fp16,+fp64,+hwdiv,+hwdiv-arm,+neon,+sha2,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,+vfp4,+vfp4d16,+vfp4d16sp,+vfp4sp" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1} # | !llvm.ident = !{!2} # | # | !0 = !{i32 1, !"target-abi", !"aapcs-linux"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000562a5a1b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a5a1ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a5a1b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5dac449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5dac4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5dac449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5dac431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a5a146e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a5a146c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a5a12bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a59ddb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a59ddadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5dac432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5dac4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5dac4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a59ddacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-directed-rounding-constrained.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c (2825 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.qdmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_n_s8(<16 x i8> noundef %a, i8 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vqdmulh.v16i8(<16 x i8> %0, <16 x i8> %.splat) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vqdmulh.v8i16(<8 x i16> %0, <8 x i16> %.splat) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vqdmulhq_n_s32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer # | %2 = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 x i32> %0, <4 x i32> %.splat) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vqdmulhq_m_n_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i8 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.qdmulh.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %.splat, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vqdmulhq_m_n_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef signext %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %.splat, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/11849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055888ea9415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055888ea910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055888ea9489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa5fd905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5fd95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa5fd905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa5fd8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055888ea29e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055888ea29c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055888ea0eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055888e6be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055888e6bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa5fd8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5fd8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5fd8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055888e6bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c (2826 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei64_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b7590315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b759000f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b7590389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1492649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14926a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1492649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1492631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b75898e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b75898c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b7587db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b7552d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b7552cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1492632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14926330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14926330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b7552ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c (2827 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559259bc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559259bc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559259bc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63ad933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63ad98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63ad933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63ad91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559259b58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559259b58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559259b3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005592597ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005592597ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63ad91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63ad91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63ad91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005592597eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c (2828 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store # | ... # `---data was truncated (10240/29296) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad2771f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ad2771c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ad2771f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e9e305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e9e35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e9e305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e9e2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad276b4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ad276b4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ad27699b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ad273490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ad27348dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e9e2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e9e2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e9e2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad27348cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c (2829 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) # | ... # `---data was truncated (10240/27055) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556d2485215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556d2484f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556d2485289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7618849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f76188a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7618849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7618831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556d247e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556d247e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556d247ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556d2447c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556d2447bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7618832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f76188330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f76188330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556d2447bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c (2830 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dc345215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dc344f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dc345289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa2ab05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa2ab5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa2ab05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa2aaed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dc33e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dc33e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dc33ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dc307c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dc307bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa2aaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa2aaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa2aaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dc307bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c (2831 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1efcbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1efcba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1efcbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0384f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0384f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0384f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0384f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1efc52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1efc52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1efc37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1ef8e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b1ef8e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0384f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0384f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0384f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1ef8e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c (2832 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562cb76c215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562cb76bf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562cb76c289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0cacd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0cacd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0cacd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0cacd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562cb7657e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562cb7657c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562cb763cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562cb72ec0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562cb72ebdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0cacd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0cacd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0cacd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562cb72ebcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c (2833 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2 # | ... # `---data was truncated (10240/50524) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff2009115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff2008e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff2009189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f48b4449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f48b44a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f48b4449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f48b4431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff20026e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff20026c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff2000bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff1fcbb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff1fcbadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f48b4432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f48b44330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f48b44330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff1fcbacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c (2834 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv1f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16mf2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv2f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m1( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv4f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m2( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv8f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8f16.f16.i64(, , half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_f16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_f16m4( %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmin.nxv16f16.f16.i64( poison, %0, half %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin. # | ... # `---data was truncated (10240/69313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e96630115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9662fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e96630189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc0ba533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc0ba58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc0ba533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc0ba51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e966296e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e966296c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e96627bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e965f2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e965f2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc0ba51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc0ba51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc0ba51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e965f2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c (2835 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16f32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16f32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i32.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i32.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; # | ... # `---data was truncated (10240/14699) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563b6f9d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563b6f9cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563b6f9d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdb04649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdb046a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdb04649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdb04631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563b6f967e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563b6f967c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563b6f94cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563b6f5fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563b6f5fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdb04632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdb046330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdb046330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563b6f5fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c (2836 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561dd4de715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561dd4de40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561dd4de789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca9649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca96a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca9649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca9631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561dd4d7ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561dd4d7cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561dd4d61b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561dd4a110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561dd4a10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efca9632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca96330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca96330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561dd4a10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c (2837 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562759dbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562759dba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562759dbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3eb5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3eb58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3eb5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3eb5831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562759d52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562759d52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562759d37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005627599e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005627599e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3eb5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3eb58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3eb58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005627599e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c (2838 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16mf2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m1x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_u16m2x3(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = allo # | ... # `---data was truncated (10240/23031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055701934615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570193430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055701934689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f7f933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f7f98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f7f933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f7f91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570192dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570192dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570192c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557018f700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557018f6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f7f91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f7f91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f7f91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557018f6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c (2839 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfge # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555c43c0a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555c43c070f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555c43c0a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3600449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36004a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3600449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3600431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555c43b9fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555c43b9fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555c43b84b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555c438340b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555c43833dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3600432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36004330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36004330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555c43833cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c (2840 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_bf16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32bf16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32f16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16f32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8f64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_i64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u8m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u16m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv32i16.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u32m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv16i32.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_u64m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv8i64.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e4m3m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vtmv_v_t_f8e5m2m8(i64 noundef %tss, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 %0, i64 %1) # | ret %2 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfofp8min,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfhmin1p0_zvfofp8min0p9_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f79ed7515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f79ed720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f79ed7589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde35533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde3558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde35533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde3551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f79ed0ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f79ed0ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f79ecefb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f79e99f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f79e99edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde3551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde3551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde3551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f79e99ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/mozilla-ms-inline-asm.c (2841 of 27911) ******************** TEST 'Clang :: CodeGen/mozilla-ms-inline-asm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c" # | target datalayout = "e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:128-n8:16:32-S128" # | target triple = "i386-apple-darwin10" # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke_copy_to_stack() #0 { # | entry: # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define void @invoke(ptr noundef %that, i32 noundef %methodIndex, i32 noundef %paramCount, ptr noundef %params) #0 { # | entry: # | %that.addr = alloca ptr, align 4 # | %methodIndex.addr = alloca i32, align 4 # | %paramCount.addr = alloca i32, align 4 # | %params.addr = alloca ptr, align 4 # | store ptr %that, ptr %that.addr, align 4 # | store i32 %methodIndex, ptr %methodIndex.addr, align 4 # | store i32 %paramCount, ptr %paramCount.addr, align 4 # | store ptr %params, ptr %params.addr, align 4 # | call void asm sideeffect inteldialect "mov edx,$1\0A\09test edx,edx\0A\09jz L__MSASMLABEL_.${:uid}__noparams\0A\09mov eax,edx\0A\09shl eax,$$3\0A\09sub esp,eax\0A\09mov ecx,esp\0A\09push $0\0A\09call ${2:P}\0A\09L__MSASMLABEL_.${:uid}__noparams:\0A\09mov ecx,$3\0A\09push ecx\0A\09mov edx,[ecx]\0A\09mov eax,$4\0A\09call dword ptr[edx + eax * $$4]\0A\09mov esp,ebp\0A\09pop ebp\0A\09ret", "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %params.addr, ptr elementtype(i32) %paramCount.addr, ptr elementtype(void (...)) @invoke_copy_to_stack, ptr elementtype(ptr) %that.addr, ptr elementtype(i32) %methodIndex.addr) #1, !srcloc !2 # | ret void # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" } # | attributes #1 = { nounwind } # | # | !llvm.module.flags = !{!0} # | !llvm.ident = !{!1} # | # | !0 = !{i32 1, !"NumRegisterParameters", i32 0} # | !1 = !{!"clang version 24.0.0"} # | !2 = !{i64 1623} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=strip -S # | #0 0x000055af66f4a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055af66f470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055af66f4a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8c3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8c36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8c3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8c3631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af66edfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055af66edfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055af66ec4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af66b740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af66b73dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff8c3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8c36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8c36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af66b73cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/mozilla-ms-inline-asm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c (2842 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_u16m1x6_m(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm_acle_swp.c (2843 of 27911) ******************** TEST 'Clang :: CodeGen/arm_acle_swp.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple thumbv7m-none-eabi -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7m-unknown-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_swp(i32 noundef %x, ptr noundef %p) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__p.addr.i = alloca ptr, align 4 # | %__v.i = alloca i32, align 4 # | %.atomictmp.i = alloca i32, align 4 # | %atomic-temp.i = alloca i32, align 4 # | %x.addr = alloca i32, align 4 # | %p.addr = alloca ptr, align 4 # | store i32 %x, ptr %x.addr, align 4 # | store ptr %p, ptr %p.addr, align 4 # | %0 = load i32, ptr %x.addr, align 4 # | %1 = load ptr, ptr %p.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store ptr %1, ptr %__p.addr.i, align 4 # | %2 = load ptr, ptr %__p.addr.i, align 4 # | %3 = load i32, ptr %__x.addr.i, align 4 # | store i32 %3, ptr %.atomictmp.i, align 4 # | %4 = load i32, ptr %.atomictmp.i, align 4 # | %5 = atomicrmw volatile xchg ptr %2, i32 %4 monotonic, align 4 # | store i32 %5, ptr %atomic-temp.i, align 4 # | %6 = load i32, ptr %atomic-temp.i, align 4 # | store i32 %6, ptr %__v.i, align 4 # | %7 = load i32, ptr %__v.i, align 4 # | ret i32 %7 # | } # | # | attributes #0 = { noinline nounwind "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv7-m,+thumb-mode" } # | # | !llvm.module.flags = !{!0, !1, !2, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"aapcs"} # | !1 = !{i32 1, !"min_enum_size", i32 4} # | !2 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !3 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598a174615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005598a17430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005598a174689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f65a1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f65a10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f65a1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f65a1031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598a16dbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598a16dbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598a16c0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598a13700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005598a136fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f65a1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f65a10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f65a10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598a136fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm_acle_swp.c -check-prefix=ATOMIC # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c (2844 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounw # | ... # `---data was truncated (10240/12658) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f985ec15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f985e90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f985ec89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb889933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb88998a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb889933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb88991b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f98581e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f98581c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f98566b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f982160b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f98215dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb88991cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb88991d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb88991d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f98215cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c (2845 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c (2846 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a97b5115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a97b4e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a97b5189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33dd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33dd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33dd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33dd2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a97ae6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a97ae6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a97acbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a9777b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a9777add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f33dd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33dd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33dd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a9777acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c (2847 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c (2848 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv8bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmul.nxv16bf16.nxv16bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmul_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c (2849 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %add = add <32 x i8> %0, %1 # | store <32 x i8> %add, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %add = add <16 x i16> %0, %1 # | store <16 x i16> %add, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %add = add <8 x i32> %0, %1 # | store <8 x i32> %add, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %add = add <4 x i64> %0, %1 # | store <4 x i64> %add, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @add_f32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x float>, align 8 # | %a.addr = alloca <8 x float>, align 8 # | %b.addr = alloca <8 x float>, align 8 # | %a = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %a.coerce, i64 0) # | %b = call <8 x float> @llvm.vector.extract.v8f32.nxv2f32( %b.coerce, i64 0) # | store <8 x float> %a, ptr %a.addr, align 8 # | store <8 x float> %b, ptr %b.addr, align 8 # | %0 = load <8 x float>, ptr %a.addr, align 8 # | %1 = load <8 x float>, ptr %b.addr, align 8 # | %add = fadd <8 x float> %0, %1 # | store <8 x float> %add, ptr %retval, align 8 # | %2 = load <8 x float>, ptr %retval, # | ... # `---data was truncated (10240/145303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x00005572971fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005572971f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005572971fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa476b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa476b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa476b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa476b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055729718fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055729718fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557297174b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557296e240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557296e23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa476b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa476b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa476b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557296e23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-arith-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c (2850 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %sc # | ... # `---data was truncated (10240/52741) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a8df28b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a8df2880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a8df28b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc7b4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc7b4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc7b4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc7b4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a8df220e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a8df220c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a8df205b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8deeb50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8deeb4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc7b4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc7b4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc7b4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8deeb4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c (2851 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettn_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005598e505a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005598e50570f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005598e505a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2b0305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2b035c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2b0305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2b02ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005598e4fefe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005598e4fefc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005598e4fd4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005598e4c840b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005598e4c83dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe2b02eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2b02ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2b02ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005598e4c83cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c (2852 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32, i32, <16 x i8>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32, i32, <8 x i16>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32, i32, <4 x i32>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> %0, <16 x i8> %1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> %0, <8 x i16> %1) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> %0, <4 x i32> %1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot90_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot90_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot270_x_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> %0, <16 x i8> %1, <16 x i1> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhcaddq_rot270_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> %0, <8 x i16> %1, <8 x i1> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhcaddq_rot270_x_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> %0, <4 x i32> %1, <4 x i1> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhcaddq_rot90_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %inactive.addr, align 8 # | # | ... # `---data was truncated (10240/15969) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558f44ad415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558f44ad10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558f44ad489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc8d2449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc8d24a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc8d2449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc8d2431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558f44a69e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558f44a69c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558f44a4eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558f446fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558f446fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc8d2432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc8d24330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc8d24330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558f446fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c (2853 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_tum( %mask, target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 4 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 4 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 5) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c (2854 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %ma # | ... # `---data was truncated (10240/12656) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8733c815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8733c50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8733c889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f63ebb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63ebb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f63ebb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f63ebaed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c87335de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c87335dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c873342b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c872ff20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c872ff1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f63ebaeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63ebaef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63ebaef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c872ff1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c (2855 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b87a21515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b87a2120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b87a21589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f37a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f37aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f37a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f37a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b87a1aae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b87a1aac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b87a18fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b879e3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b879e3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f37a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f37a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f37a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b879e3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c (2856 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvabd -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf4_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv1i16.nxv1i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16mf2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv2i16.nxv2i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m1_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv4i16.nxv4i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load , ptr %vs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vx_u16m2_tu( %vd, %vs2, i8 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 1 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load i8, ptr %rs1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64( %0, %1, i8 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwabda.nxv8i16.nxv8i8.i8.i64(, , i8, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwabda_vv_u16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %v # | ... # `---data was truncated (10240/110062) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005652f366f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005652f366c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005652f366f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ca0533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ca058a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ca0533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ca051b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005652f3604e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005652f3604c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005652f35e9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005652f32990b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005652f3298dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ca051cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ca051d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ca051d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005652f3298cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c (2857 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv1bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv2bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4bf16.bf16.i64(, , bfloat, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfa # | ... # `---data was truncated (10240/65574) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562404f1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562404f0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562404f1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4268449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42684a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4268449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4268431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562404ea7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562404ea7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562404e8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562404b3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562404b3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4268432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42684330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42684330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562404b3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c (2858 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aadb30015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aadb2fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aadb30089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4caf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4caf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4caf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4caf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aadb295e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aadb295c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aadb27ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aadaf2a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aadaf29dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4caf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4caf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4caf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aadaf29cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c (2859 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function # | ... # `---data was truncated (10240/22115) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055805468f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055805468c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055805468f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f216dd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f216dd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f216dd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f216dd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558054624e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558054624c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558054609b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580542b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580542b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f216dd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f216dd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f216dd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580542b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c (2860 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv8i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv8i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv16i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv16i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv32i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv32i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i8m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv64i8.i8.i64( %0, %1, i8 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv64i8.i8.i64(, , i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv1i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv1i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv2i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv2i16.i16.i64(, , i16, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vneg_v_i16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrsub.nxv4i16.i16.i64( %0, %1, i16 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrsub.nxv4 # | ... # `---data was truncated (10240/96257) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562529a4d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562529a4a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562529a4d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f037ec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f037eca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f037ec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f037ec31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005625299e2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005625299e2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005625299c7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005625296770b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562529676dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f037ec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f037ec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f037ec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562529676cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c (2861 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c38a9b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c38a980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c38a9b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1409905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f140995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1409905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14098ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c38a30e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c38a30c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c38a15b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c386c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c386c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14098eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14098ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14098ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c386c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c (2862 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c (2863 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b1_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv64i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b2_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv32i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b4_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv16i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b8_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv8i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b16_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv4i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv4i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b32_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv2i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv2i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsbf_m_b64_mu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmsbf.mask.nxv1i1.i64( %1, %2, %0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsbf.mask.nxv1i1.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555d9710115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555d970fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555d9710189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb546849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5468a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb546849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb546831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555d97096e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555d97096c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555d9707bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555d96d2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555d96d2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb546832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5468330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5468330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555d96d2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c (2864 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { targe # | ... # `---data was truncated (10240/81756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558162bb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558162bb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558162bb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae85133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae8518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae85133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae8511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558162b49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558162b49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558162b2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005581627de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005581627dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae8511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae8511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae8511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005581627ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c (2865 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_f16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_i16m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf4x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e16_v_u16mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/26921) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556de5e4215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556de5e3f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556de5e4289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6188933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f618898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6188933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f618891b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556de5dd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556de5dd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556de5dbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556de5a6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556de5a6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f618891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f618891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f618891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556de5a6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c (2866 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv1i16.nxv1i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv2i16.nxv2i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv4i16.nxv4i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv8i16.nxv8i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vv_u16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vwsll_vx_u16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64( poison, %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwsll.nxv16i16.nxv16i8.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/68141) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb1202815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb120250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb1202889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb8aac49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb8aaca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb8aac49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8aac31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb11fbde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb11fbdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb11fa2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb11c520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb11c51dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8aac32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8aac330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8aac330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb11c51cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c (2867 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056274404715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005627440440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056274404789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ade533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ade58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ade533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ade51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562743fdce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562743fdcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562743fc1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562743c710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562743c70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ade51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ade51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ade51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562743c70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c (2868 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556608bbd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556608bba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556608bbd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ee021bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ee02725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ee021ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ee0203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556608b52e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556608b52c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556608b37b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005566087e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005566087e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ee0204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ee02050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ee02050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005566087e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c (2869 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e10077f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e10077c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e10077f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc438333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc43838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc438333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc43831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e100714e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e100714c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e1006f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e1003a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e1003a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc43831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc43831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc43831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e1003a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c (2870 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf8_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf8_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv1i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv1i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf4_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv2i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv2i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8mf2_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv4i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv4i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load , ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vx_i8m1_tu( %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i8, ptr %op2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vaadd.nxv8i8.i8.i64( %0, %1, i8 %2, i64 0, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaadd.nxv8i8.i8.i64(, , i8, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vaadd_vv_i8m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, al # | ... # `---data was truncated (10240/225213) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056204f29715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056204f2940f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056204f29789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f59505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f5955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f59505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f594ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000056204f22ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056204f22cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056204f211b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056204eec10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056204eec0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5f594eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f594ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f594ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056204eec0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c (2871 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv1bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv2bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv4bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv8bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv16bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8( %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vslidedown.nxv32bf16.i64( poison, %0, i64 %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv2bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_m( %vm, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.mask.nxv4bf16.i64( poison, %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv4bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_m( %vm, %vs2, i64 noundef %rs1, i # | ... # `---data was truncated (10240/14325) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055755ad3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055755ad3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055755ad3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcb34133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcb3418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcb34133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcb3411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055755acd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055755acd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055755acb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055755a9670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055755a966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcb3411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcb3411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcb3411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055755a966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c (2872 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055846404215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055846403f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055846404289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f11cff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f11cff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f11cff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f11cff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558463fd7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558463fd7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558463fbcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558463c6c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558463c6bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f11cff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f11cff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f11cff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558463c6bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c (2873 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei8_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple # | ... # `---data was truncated (10240/31938) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005607c908615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005607c90830f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005607c908689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe1e0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1e0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe1e0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe1e0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005607c901be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005607c901bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005607c9000b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005607c8cb00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005607c8cafdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe1e0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1e0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1e0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005607c8cafcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c (2874 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv16f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv32f16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i16.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv # | ... # `---data was truncated (10240/83637) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055859572015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055859571d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055859572089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f926cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f926cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f926cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f926cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585956b5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585956b5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055859569ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055859534a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558595349dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f926cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f926cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f926cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558595349cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (2875 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfadd_vv_f16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c172b3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c172b350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c172b3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb52e449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb52e4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb52e449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb52e431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c172acde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c172acdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c172ab2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c1727620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c172761dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb52e432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb52e4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb52e4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c172761cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-ZVF /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c (2876 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf4x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f16m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32mf2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m1x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f32m2x4(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsoxseg4ei64_v_f64m1x4(ptr noundef %base, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c (2877 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a7621615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a762130f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a7621689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf48249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf482a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf48249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf48231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a761abe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a761abc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a76190b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a75e400b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a75e3fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf48232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf482330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf482330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a75e3fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c (2878 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8(ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d9d094915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d9d09460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d9d094989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b2a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b2a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b2a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b2a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d9d08dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d9d08dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d9d08c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d9d05730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d9d0572dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b2a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b2a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b2a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d9d0572cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c (2879 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd4877b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd487780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd4877b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6b9849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6b98a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6b9849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6b9831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd48710e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd48710c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd486f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd483a50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd483a4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6b9832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6b98330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6b98330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd483a4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c (2880 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zksed -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ks(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ks(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ks(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sm4ed(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.sm4ed(i32 %0, i32 %1, i32 0) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sm4ed(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zksed" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zksed1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa4a3d315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aa4a3d00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aa4a3d389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f24d4133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f24d418a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f24d4133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f24d411b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa4a368e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aa4a368c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aa4a34db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aa49ffd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aa49ffcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f24d411cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f24d411d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f24d411d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa49ffccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/zksed.c -check-prefix=RV32ZKSED # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c (2881 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582af4ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582af4ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582af4ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb819905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb81995c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb819905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8198ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582af482e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582af482c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582af467b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582af1170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582af116dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8198eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8198ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8198ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582af116cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c (2882 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a3ef44415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a3ef4410f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a3ef44489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2267449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f22674a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2267449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2267431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a3ef3d9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a3ef3d9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a3ef3beb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a3ef06e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a3ef06ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2267432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f22674330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f22674330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a3ef06dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c (2883 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_x_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.x.v.nxv32bf16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv1bf16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv2bf16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv4bf16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv8bf16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.nxv16bf16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_xu_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfwcvt.f.xu.v.nxv32bf16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.xu.v.n # | ... # `---data was truncated (10240/33624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561d33a3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561d33a3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561d33a3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe786049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7860a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe786049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe786031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561d339d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561d339d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561d339b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561d336670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561d33666dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe786032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7860330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7860330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561d33666cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c (2884 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_f16m8(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv32f16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv32f16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv1i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16mf2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv2i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m1(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv4i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv8i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_i16m4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vlse.nxv16i16.p0.i64( poison, ptr %0, i64 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv16i16.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse16_v_ # | ... # `---data was truncated (10240/35087) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582c3e5f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582c3e5c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582c3e5f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87e1a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87e1aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87e1a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87e1a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582c3df4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582c3df4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582c3dd9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582c3a890b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582c3a88dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f87e1a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87e1a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87e1a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582c3a88cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c (2885 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580bf81815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580bf8150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580bf81889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fed99a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fed99aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fed99a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fed99a31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580bf7ade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580bf7adc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580bf792b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580bf4420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580bf441dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fed99a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fed99a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fed99a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580bf441cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c (2886 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/25825) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560094c7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560094c760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560094c7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f82bf333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82bf38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f82bf333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f82bf31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560094c0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560094c0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560094bf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005600948a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005600948a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f82bf31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82bf31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82bf31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005600948a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c (2887 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle # | ... # `---data was truncated (10240/18668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562106ce915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562106ce60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562106ce989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95cf849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95cf8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95cf849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95cf831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562106c7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562106c7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562106c63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005621069130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562106912dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95cf832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95cf8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95cf8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562106912cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c (2888 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +xsfvfwmaccqqq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfwmacc_4x4x4_f32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvfwmaccqqq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfbfmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvfwmaccqqq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005557d1de615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005557d1de30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005557d1de689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f42a7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f42a778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f42a7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f42a771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005557d1d7be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005557d1d7bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005557d1d60b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557d1a100b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557d1a0fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f42a771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f42a771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f42a771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557d1a0fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c (2889 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei8_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 5), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558a1910e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558a1910b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558a1910e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ce781bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ce78725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ce781ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ce7803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558a190a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558a190a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558a19088b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558a18d380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558a18d37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ce7804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ce78050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ce78050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558a18d37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c (2890 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_f16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf4x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16mf2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 3) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_i16m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv8 # | ... # `---data was truncated (10240/15457) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615aa89015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615aa88d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005615aa89089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f135eb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f135eb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f135eb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f135eb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615aa825e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615aa825c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615aa80ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615aa4ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615aa4b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f135eb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f135eb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f135eb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615aa4b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c (2891 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.nxv1i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m1_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv1i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv1i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m2_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.nxv2i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m2_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv2i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv2i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m4_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.nxv4i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m4_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv4i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv4i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m8_tu( %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load , ptr %vs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.nxv8i64.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vx_u64m8_tu( %maskedoff, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vclmul.nxv8i64.i64.i64( %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vclmul.nxv8i64.i64.i64(, , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vclmul_vv_u64m1_tum( %mask, %maskedoff, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c (2892 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d33d3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d33d3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d33d3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fba9d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fba9d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fba9d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fba9d231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d33cd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d33cd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d33cb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d339670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d33966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fba9d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fba9d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fba9d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d33966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c (2893 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c92c7e815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c92c7e50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c92c7e889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f92bdb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92bdb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f92bdb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f92bdb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c92c77de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c92c77dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c92c762b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c92c4120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c92c411dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f92bdb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92bdb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92bdb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c92c411cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c (2894 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(arg # | ... # `---data was truncated (10240/20531) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055de0aac115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055de0aabe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055de0aac189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f658e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f658e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f658e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f658e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055de0aa56e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055de0aa56c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055de0aa3bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055de0a6eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055de0a6eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f658e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f658e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f658e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055de0a6eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c (2895 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | de # | ... # `---data was truncated (10240/12091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c944ce315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c944ce00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c944ce389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98adf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98adf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98adf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98adf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c944c78e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c944c78c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c944c5db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c94490d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c94490cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98adf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98adf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98adf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c94490ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c (2896 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.ris # | ... # `---data was truncated (10240/60220) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573f210e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573f210b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005573f210e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff825333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff82538a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff825333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff82531b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573f20a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005573f20a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005573f2088b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573f1d380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005573f1d37dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff82531cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff82531d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff82531d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573f1d37cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c (2897 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_f16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_i16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf4x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16mf2x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg5e16_v_u16m1x5(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555713aa915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555713aa60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555713aa989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36c2d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36c2d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36c2d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36c2d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555713a3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555713a3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555713a23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557136d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557136d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f36c2d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36c2d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36c2d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557136d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c (2898 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf4x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16mf2x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16ff_v_bf16m1x5_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563529e8815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563529e850f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563529e8889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f23b541bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f23b54725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f23b541ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f23b5403507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563529e1de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563529e1dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563529e02b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563529ab20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563529ab1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f23b5404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f23b54050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f23b54050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563529ab1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c (2899 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmorn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmorn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmorn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bc60fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555bc60f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555bc60fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1722a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1722a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1722a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1722a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bc6091e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555bc6091c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555bc6076b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555bc5d260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555bc5d25dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1722a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1722a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1722a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bc5d25cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c (2900 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056454285715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005645428540f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056454285789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4878133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f487818a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4878133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f487811b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005645427ece2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005645427ecc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005645427d1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005645424810b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564542480dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f487811cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f487811d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f487811d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564542480cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c (2901 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zbkb -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @brev8_32(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.brev8.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @zip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.zip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @unzip(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.unzip.i32(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.brev8.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.zip.i32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.unzip.i32(i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zbkb" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zbkb1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6eae2915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6eae260f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a6eae2989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdab7849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdab78a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdab7849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdab7831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6eadbee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a6eadbec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a6eada3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a6eaa530b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a6eaa52dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdab7832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdab78330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdab78330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6eaa52cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvb-intrinsics/zbkb.c -check-prefix=RV32ZBKB # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c (2902 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvpackfph -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv1f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv2f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv4f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv8f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m4( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv16f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m8( %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.nxv32f16.f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf4_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16mf2_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m1_m( %mask, %op1, float noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store float %op2, ptr %op2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load float, ptr %op2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vfpmadb_vf_f16m2_m( %mask, %op1, float noun # | ... # `---data was truncated (10240/25091) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561c5988115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561c5987e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561c5988189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8056049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f80560a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8056049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8056031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561c59816e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561c59816c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561c597fbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561c594ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561c594aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8056032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f80560330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f80560330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561c594aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c (2903 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none) # | ... # `---data was truncated (10240/30609) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056133916815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613391650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056133916889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f96f9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f96f94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f96f9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f96f9431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613390fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005613390fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005613390e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561338d920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561338d91dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f96f9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f96f94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f96f94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561338d91cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c (2904 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_i8m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf8x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e8_v_u8mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range( # | ... # `---data was truncated (10240/31876) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aa573a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aa5739d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aa573a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff95249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff952a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff95249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff95231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aa57335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aa57335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aa5731ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aa56fca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aa56fc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff95232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff952330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff952330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aa56fc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c (2905 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1_tu( %vd, %vs, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declar # | ... # `---data was truncated (10240/44434) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005614aac7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005614aac760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005614aac7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95f3333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95f338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95f3333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95f331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005614aac0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005614aac0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005614aabf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005614aa8a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005614aa8a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95f331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95f331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95f331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005614aa8a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c (2906 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmin.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmin_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmin.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ... # `---data was truncated (10240/64958) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a6ea22b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a6ea2280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a6ea22b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd807e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd807ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd807e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd807e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a6ea1c0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a6ea1c0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a6ea1a5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a6e9e550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a6e9e54dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd807e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd807e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd807e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a6e9e54cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c (2907 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dc0f9de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dc0f9db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dc0f9de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2897333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f289738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2897333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f289731b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dc0f973e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dc0f973c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dc0f958b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dc0f6080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dc0f607dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f289731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f289731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f289731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dc0f607cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c (2908 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8mf2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m1_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m2_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m4_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u8m8_u8m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vector.addr, align 1 # | %2 = load , ptr %scalar.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredminu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredminu_vs_u16mf4_u16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vredminu.nxv4i16.nxv1i16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a31d6d715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a31d6d40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a31d6d789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0b6c01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0b6c0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0b6c01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0b6c003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a31d66ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a31d66cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a31d651b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a31d3010b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a31d300dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0b6c004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0b6c0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0b6c0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a31d300cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c (2909 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf4x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16mf2x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_f16m1x8_m( %mask, ptr noundef %base, i64 # | ... # `---data was truncated (10240/17523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564efe2bb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564efe2b80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564efe2bb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37b0333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37b038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37b0333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37b031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564efe250e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564efe250c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564efe235b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564efdee50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564efdee4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37b031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37b031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37b031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564efdee4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c (2910 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffb.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.riscv.nds.flmism.i32(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b24029815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2402950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b24029889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f798f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f798f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f798f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f798f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b24022de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b24022dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b240212b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b23fec20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b23fec1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f798f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f798f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f798f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b23fec1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv32.c --check-prefix=CHECK-RV32 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c (2911 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgeu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgeu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c (2912 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf2x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16m1x8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056542205115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056542204e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056542205189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdf2e133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdf2e18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdf2e133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdf2e11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565421fe6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565421fe6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565421fcbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565421c7b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565421c7add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdf2e11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdf2e11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdf2e11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565421c7acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c (2913 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf2_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op # | ... # `---data was truncated (10240/28563) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd3b74c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd3b7490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd3b74c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3529c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3529ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3529c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3529c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd3b6e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd3b6e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd3b6c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd3b3760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd3b375dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3529c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3529c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3529c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd3b375cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c (2914 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv1i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2 # | ... # `---data was truncated (10240/54694) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055685d2a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055685d29d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055685d2a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f33b8933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f33b898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f33b8933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f33b891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055685d235e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055685d235c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055685d21ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055685ceca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055685cec9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f33b891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f33b891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f33b891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055685cec9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c (2915 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_i16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_u16m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e16_v_f16mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.ri # | ... # `---data was truncated (10240/20449) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ba11aca15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ba11ac70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ba11aca89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01ece49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01ecea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01ece49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01ece31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ba11a5fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ba11a5fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ba11a44b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ba116f40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ba116f3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01ece32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01ece330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01ece330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ba116f3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c (2916 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dafca3f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dafca3c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dafca3f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06e0a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06e0aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06e0a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06e0a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dafc9d4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dafc9d4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dafc9b9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dafc6690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dafc668dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f06e0a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06e0a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06e0a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dafc668cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c (2917 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_f16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv32f16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv32f16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv1i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv1i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16mf2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv2i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv2i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m1(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv4i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv4i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m2(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv8i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv8i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m4(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %value.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vse.nxv16i16.p0.i64( %1, ptr %0, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vse.nxv16i16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vse16_v_i16m8(ptr noundef %base, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %value.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | % # | ... # `---data was truncated (10240/33764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633b7a7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633b7a6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633b7a7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f901cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f901cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f901cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f901cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005633b7a06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005633b7a06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005633b79ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005633b769b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005633b769add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f901cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f901cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f901cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005633b769acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c (2918 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv1i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv2i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c76b0c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c76b0c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c76b0c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe2f6849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe2f68a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe2f6849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe2f6831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c76b058e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c76b058c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c76b03db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c76aced0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c76acecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe2f6832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe2f68330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe2f68330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c76aceccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c (2919 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_i32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_u32m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8f35c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8f35be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8f35c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64ff333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64ff38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64ff333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64ff31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8f3556e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8f3556c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8f353bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8f31eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8f31eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64ff31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64ff31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64ff31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8f31eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c (2920 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005618c310115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005618c30fe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005618c310189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fc2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fc2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fc2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fc2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005618c3096e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005618c3096c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005618c307bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005618c2d2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005618c2d2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9fc2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fc2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fc2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005618c2d2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c (2921 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +xsfvfexp32e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.nxv16f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv1f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv2f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv4f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexp.mask.nxv8f32.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f32.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c (2922 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c (2923 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f16m8( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32mf2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m1( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m2( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load , ptr %mask.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vcompress.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vcompress.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vcompress_vm_f32m4( %src, %mask, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c (2924 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/18217) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613a0a2f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613a0a2c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005613a0a2f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007feca461bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007feca46725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007feca461ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007feca4603507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613a09c4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005613a09c4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005613a09a9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005613a06590b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005613a0658dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007feca4604fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007feca46050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007feca46050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613a0658cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/thinlto-funcattr-prop.ll (2925 of 27911) ******************** TEST 'Clang :: CodeGen/thinlto-funcattr-prop.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # executed command: split-file /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/thinlto-funcattr-prop.ll /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp # RUN: at line 6 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.ll -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/thinlto-funcattr-prop.ll.tmp/a.bc # | #0 0x0000557dd9c6e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557dd9c6b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557dd9c6e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f683f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f683f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f683f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f683f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dd9c03e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557dd9c03c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557dd9be8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557dd98980b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557dd9897dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f683f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f683f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f683f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dd9897cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c (2926 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -target-feature +zvfbfmin -target-feature +zvfbfwma -target-feature +zve64x -target-feature +zve64d -target-feature +experimental-zvzip -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16f16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f32.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f32.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f32.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f32m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8f32.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1f64.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2f64.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vunzipe_v_f64m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4f64.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c (2927 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_f32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_i32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32mf2x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv4i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32ff_v_u32m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a73459f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a73459c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a73459f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0343249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03432a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0343249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0343231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a734534e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a734534c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a734519b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a7341c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a7341c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0343232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03432330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03432330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7341c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c (2928 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | # | ... # `---data was truncated (10240/26713) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055923d3a415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055923d3a10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055923d3a489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe002333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe00238a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe002333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe00231b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055923d339e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055923d339c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055923d31eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055923cfce0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055923cfcddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe00231cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe00231d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe00231d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055923cfcdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c (2929 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c (2930 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_f16m4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf4x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16mf2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m1x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg2e16_v_i16m2x2(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.a # | ... # `---data was truncated (10240/38299) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559a0ffea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559a0ffe70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559a0ffea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f53bf049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f53bf0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f53bf049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f53bf031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559a0ff7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559a0ff7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559a0ff64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559a0fc140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559a0fc13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f53bf032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f53bf0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f53bf0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559a0fc13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c (2931 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056443642715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644364240f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056443642789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f41a9249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f41a92a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f41a9249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f41a9231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644363bce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644363bcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644363a1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644360510b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564436050dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f41a9232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f41a92330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f41a92330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564436050cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c (2932 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredor.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredor.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredor_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.add # | ... # `---data was truncated (10240/94157) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005555f371d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005555f371a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005555f371d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b95649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b956a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b95649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b95631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005555f36b2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005555f36b2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005555f3697b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005555f33470b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005555f3346dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b95632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b956330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b956330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005555f3346cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c (2933 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = # | ... # `---data was truncated (10240/26564) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005587cf79515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005587cf7920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005587cf79589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58a1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58a178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58a1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58a171b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005587cf72ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005587cf72ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005587cf70fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005587cf3bf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005587cf3bedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f58a171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58a171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58a171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005587cf3becc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c (2934 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | st # | ... # `---data was truncated (10240/11797) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558dc54e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558dc54e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558dc54e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f64f5049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f64f50a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f64f5049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f64f5031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558dc547ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558dc547ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558dc545fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558dc510f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558dc510edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f64f5032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f64f50330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f64f50330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558dc510ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c (2935 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64_v_i64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c (2936 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, a # | ... # `---data was truncated (10240/43486) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056474ebf415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056474ebf10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056474ebf489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab09b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab09b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab09b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab09b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056474eb89e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056474eb89c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056474eb6eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056474e81e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056474e81ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab09b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab09b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab09b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056474e81dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c (2937 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16mf2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m1(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m2(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m4(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f16m8(half noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store half %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load half, ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv32f16.i64( poison, half %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32f16.i64(, half, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32mf2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m1(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m2(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m4(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv8f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f32m8(float noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store float %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load float, ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv16f32.i64( poison, float %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16f32.i64(, float, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m1(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv1f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m2(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv2f64.i64( poison, double %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2f64.i64(, double, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_f64m4(double noundef %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca double, align 8 # | %vl.addr = alloca i64, align 8 # | store double %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load double, ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfmv.v.f.nxv4f64.i64( poison, double %0, i64 %1) # | # | ... # `---data was truncated (10240/30849) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7a9a9d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7a9a9a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7a9a9d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6dd733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6dd78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6dd733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6dd71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7a9a32e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b7a9a32c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b7a9a17b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7a96c70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b7a96c6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff6dd71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6dd71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6dd71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7a96c6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c (2938 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b3d5fc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b3d5f90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b3d5fc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa97bf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa97bf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa97bf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa97bf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b3d591e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b3d591c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b3d576b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b3d2260b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b3d225dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa97bf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa97bf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa97bf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b3d225cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c (2939 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m4x2(ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | # | ... # `---data was truncated (10240/13255) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c723da15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c723d70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c723da89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f58e4533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f58e458a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f58e4533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f58e451b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c7236fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c7236fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c72354b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c720040b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c72003dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f58e451cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f58e451d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f58e451d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c72003cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c (2940 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.t # | ... # `---data was truncated (10240/48313) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ff2dc6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ff2dc680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ff2dc6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd8e2305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd8e235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd8e2305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd8e22ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ff2dc00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ff2dc00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ff2dbe5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ff2d8950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ff2d894dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd8e22eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd8e22ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd8e22ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ff2d894cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c (2941 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg8ei8_v_bf16m1x8_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 8) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 8), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556cbc59915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556cbc5960f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556cbc59989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1378249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f13782a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1378249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1378231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556cbc52ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556cbc52ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556cbc513b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556cbc1c30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556cbc1c2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1378232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f13782330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f13782330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556cbc1c2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c (2942 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_i64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_u64m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: wri # | ... # `---data was truncated (10240/20523) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f84fab315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f84fab00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f84fab389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd503f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd503f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd503f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd503f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f84fa48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f84fa48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f84fa2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f84f6dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f84f6dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd503f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd503f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd503f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f84f6dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c (2943 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zkne -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64es(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64es(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64esm(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64esm(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64es(i64, i64) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64esm(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zkne" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zkne1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cdf037115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cdf036e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cdf037189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf69533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf6958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf69533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf6951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cdf0306e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cdf0306c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cdf02ebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cdeff9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cdeff9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf6951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf6951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf6951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cdeff9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c -check-prefix=RV64ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c (2944 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3 # | ... # `---data was truncated (10240/64366) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595c66e015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595c66dd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595c66e089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37af01bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37af0725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37af01ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37af003507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595c6675e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595c6675c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595c665ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595c630a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595c6309dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37af004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37af0050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37af0050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595c6309cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c (2945 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_ # | ... # `---data was truncated (10240/10440) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056327dc2b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056327dc280f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056327dc2b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab6d21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab6d2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab6d21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab6d203507 abort ./stdlib/abort.c:85:3 # | #7 0x000056327dbc0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056327dbc0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056327dba5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056327d8550b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056327d854dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab6d204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab6d2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab6d2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056327d854cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c (2946 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_f16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_i16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf4x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16mf2x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg8e16_v_u16m1x8(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", # | ... # `---data was truncated (10240/23365) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e887d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e887cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e887d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3cad21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3cad2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3cad21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3cad203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e88767e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e88767c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e8874cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e883fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e883fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3cad204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3cad2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3cad2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e883fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c (2947 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = al # | ... # `---data was truncated (10240/14209) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d1495af15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d1495ac0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d1495af89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffa4ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffa4ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffa4ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffa4ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d149544e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d149544c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d149529b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d1491d90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d1491d8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffa4ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffa4ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffa4ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d1491d8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c (2948 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a7ab35215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a7ab34f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a7ab35289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f04733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f0478a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f04733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f0471b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a7ab2e7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a7ab2e7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a7ab2ccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a7aaf7c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a7aaf7bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f0471cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f0471d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f0471d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a7aaf7bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c (2949 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmflt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmflt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmflt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willr # | ... # `---data was truncated (10240/44361) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d432b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d432b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d432b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f00f3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f00f3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f00f3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f00f3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d4324be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d4324bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d43230b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d42ee00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d42edfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f00f3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f00f3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f00f3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d42edfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c (2950 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load , ptr %bindex.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_f32m2x4_tu(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c (2951 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf4x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f16m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32mf2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m1x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m2x2(ptr noundef %base, %bindex, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsuxseg2ei64_v_f32m4x2(ptr noundef %base, %binde # | ... # `---data was truncated (10240/110121) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558662d1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558662d140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558662d1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f979e105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f979e15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f979e105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f979e0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558662cace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558662cacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558662c91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005586629410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558662940dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f979e0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f979e0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f979e0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558662940cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c (2952 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056102d87415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056102d8710f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056102d87489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f301a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f301a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f301a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f301a631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056102d809e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056102d809c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056102d7eeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056102d49e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056102d49ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f301a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f301a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f301a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056102d49dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c (2953 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f32m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf4_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rod_f_f_w_f16mf2_m( %mask, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loca # | ... # `---data was truncated (10240/18587) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557585d8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557585d8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557585d8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ab7533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ab758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ab7533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ab751b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557585d24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557585d24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557585d09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575859b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575859b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ab751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ab751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ab751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575859b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c (2954 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e64_v_u64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/47706) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562edbc5215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562edbc4f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562edbc5289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5c12b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5c12b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5c12b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5c12aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562edbbe7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562edbbe7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562edbbccb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562edb87c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562edb87bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5c12aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5c12aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5c12aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562edb87bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c (2955 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_loc # | ... # `---data was truncated (10240/37556) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005633602f515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005633602f20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005633602f589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7442649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f74426a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7442649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7442631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056336028ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056336028ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056336026fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056335ff1f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056335ff1edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7442632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f74426330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f74426330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056335ff1ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c (2956 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c5c76b815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c5c76b50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c5c76b889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8c92c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8c92c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8c92c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8c92c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c5c764de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c5c764dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c5c7632b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c5c72e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c5c72e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8c92c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8c92c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8c92c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c5c72e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c (2957 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565015fd115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565015fce0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565015fd189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f536b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f536b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f536b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f536b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565015f66e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565015f66c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565015f4bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565015bfb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565015bfadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f536b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f536b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f536b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565015bfacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c (2958 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei32_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c (2959 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055595db8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055595db810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055595db8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8fad649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8fad6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8fad649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8fad631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055595db19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055595db19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055595dafeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055595d7ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055595d7addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8fad632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8fad6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8fad6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055595d7adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c (2960 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_f32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv16f32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv16f32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32mf2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i32.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i32.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse32_v_i32m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 4 # | %3 = load i64, p # | ... # `---data was truncated (10240/33198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcfec7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dcfec6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dcfec7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb836d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb836d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb836d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb836d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcfec06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dcfec06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dcfebebb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dcfe89b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dcfe89add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb836d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb836d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb836d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcfe89acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c (2961 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055db0393d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055db0393a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055db0393d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5cc0133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5cc018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5cc0133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5cc011b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055db038d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055db038d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055db038b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055db035670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055db03566dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5cc011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5cc011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5cc011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055db03566cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c (2962 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f088d0715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f088d040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f088d0789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ef8e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ef8ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ef8e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ef8e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f088c9ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f088c9cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f088c81b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f0889310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f088930dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ef8e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ef8e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ef8e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f088930cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c (2963 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfvfexpa,+xsfvfexpa64e,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfvfexpa0p2_xsfvfexpa64e0p2"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055934beb115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055934beae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055934beb189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e5c81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e5c8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e5c81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e5c803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055934be46e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055934be46c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055934be2bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055934badb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055934badadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e5c804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e5c8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e5c8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055934badacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c (2964 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_f32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16f32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16f32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_i32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i32.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32mf2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i32.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle32_v_u32m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv16i32.p0.i64( p # | ... # `---data was truncated (10240/24606) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cf50b9f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cf50b9c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cf50b9f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2a05d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2a05d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2a05d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2a05d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cf50b34e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cf50b34c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cf50b19b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cf507c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cf507c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2a05d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2a05d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2a05d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cf507c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c (2965 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 7) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple # | ... # `---data was truncated (10240/20903) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b59f35515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b59f3520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b59f35589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7f73533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7f7358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7f73533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7f7351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b59f2eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b59f2eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b59f2cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b59ef7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b59ef7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7f7351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7f7351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7f7351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b59ef7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c (2966 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_i32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_u32m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32ff_v_f32mf2x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedof # | ... # `---data was truncated (10240/40734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005588f3a5015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005588f3a4d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005588f3a5089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7c05249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7c052a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7c05249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7c05231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005588f39e5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005588f39e5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005588f39cab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005588f367a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005588f3679dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7c05232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7c052330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7c052330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005588f3679cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c (2967 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_i8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf8x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf4x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8mf2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m1x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg3e8_v_u8m2x3(ptr noundef %base, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @ # | ... # `---data was truncated (10240/23479) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cca4d215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555cca4cf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555cca4d289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe197249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe1972a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe197249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe197231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cca467e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555cca467c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555cca44cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555cca0fc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555cca0fbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe197232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe1972330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe1972330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cca0fbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c (2968 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_f64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_i64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64ff_v_u64m1x6_tum( %mask, target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 6) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c (2969 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpairo.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpairo.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpairo.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpairo_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/32646) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055823234815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582323450f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055823234889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcffeb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcffeb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcffeb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcffeb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582322dde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582322ddc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582322c2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558231f720b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558231f71dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcffeb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcffeb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcffeb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558231f71cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c (2970 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zve64x -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.sf.vsettnt.i64(i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e8w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 0, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e16w4(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 1, i64 3) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 1) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e32w2(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 2, i64 2) # | ret i64 %1 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local i64 @test_sf_vsettnt_e64w1(i64 noundef %tn) #0 { # | entry: # | %tn.addr = alloca i64, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | %0 = load i64, ptr %tn.addr, align 8 # | %1 = call i64 @llvm.riscv.sf.vsettnt.i64(i64 %0, i64 3, i64 1) # | ret i64 %1 # | } # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zve64x,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005593922b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005593922b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005593922b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe9b6e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe9b6ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe9b6e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe9b6e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055939224ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055939224ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055939222fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559391edf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559391ededd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe9b6e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe9b6e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe9b6e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559391edecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c (2971 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_i8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_u8m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16.i64(, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c (2972 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557f4596015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557f4595d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557f4596089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faa60d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faa60d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faa60d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faa60d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557f458f5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557f458f5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557f458dab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557f4558a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557f45589dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faa60d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faa60d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faa60d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557f45589cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c (2973 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8_tu( %maskedoff, %vs2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bce2fba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bce2fb70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bce2fba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5975649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59756a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5975649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5975631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bce2f4fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bce2f4fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bce2f34b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bce2be40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bce2be3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5975632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59756330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59756330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bce2be3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c (2974 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c (2975 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwin # | ... # `---data was truncated (10240/13581) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056195c2bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056195c2ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056195c2bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa8d5249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa8d52a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa8d5249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa8d5231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056195c252e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056195c252c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056195c237b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056195bee70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056195bee6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa8d5232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa8d52330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa8d52330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056195bee6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c (2976 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv1i64.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv2i64.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv4i64.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsext.nxv8i64.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m8_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsext_vf8_i64m1_tumu( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 8 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c (2977 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv1i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv1i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv2i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv2i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv4i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv4i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv8i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv8i32.i64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4k_vi_u32m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vsm4k.nxv16i32.i64.i64( poison, %0, i64 0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4k.nxv16i32.i64.i64(, , i64 immarg, i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005606a526115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005606a525e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005606a526189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbc69133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbc6918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbc69133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbc6911b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005606a51f6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005606a51f6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005606a51dbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005606a4e8b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005606a4e8add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbc6911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbc6911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbc6911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005606a4e8acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c (2978 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmxor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmxor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmxor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a5c7d3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a5c7d2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a5c7d3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce63133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce6318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce63133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce6311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a5c7cc6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a5c7cc6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a5c7cabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a5c795b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a5c795add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce6311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce6311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce6311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a5c795acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c (2979 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 2, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: # | ... # `---data was truncated (10240/12431) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562c1816c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562c181690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562c1816c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5f50333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5f5038a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5f50333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5f5031b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562c18101e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562c18101c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562c180e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562c17d960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562c17d95dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5f5031cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5f5031d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5f5031d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562c17d95cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c (2980 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf4x4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_u16mf2x4_m( %mask, ptr nound # | ... # `---data was truncated (10240/13515) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056241819b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624181980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056241819b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f47b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f47b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f47b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f47aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562418130e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562418130c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562418115b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562417dc50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562417dc4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f47aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f47aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f47aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562417dc4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c (2981 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557a9cc2015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557a9cc1d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557a9cc2089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3958733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f395878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3958733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f395871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557a9cbb5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557a9cbb5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557a9cb9ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557a9c84a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557a9c849dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f395871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f395871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f395871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557a9c849cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c (2982 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i16.i8.nxv1i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16mf2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i16.i8.nxv2i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m1( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv4i16.i8.nxv4i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m2( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv8i16.i8.nxv8i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m4( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv16i16.i8.nxv16i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i16m8( %vd, i8 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca i8, align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store i8 %rs1, ptr %rs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load i8, ptr %rs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64( %0, i8 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv32i16.i8.nxv32i8.i64(, i8, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32mf2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv1i32.i16.nxv1i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m1( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64( %0, i16 %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vwmaccus.nxv2i32.i16.nxv2i16.i64(, i16, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vwmaccus_vx_i32m2( %vd, i16 noundef zeroext %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %rs1.addr = alloca i16, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store i16 %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load i16, ptr %rs1.addr, align # | ... # `---data was truncated (10240/39226) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a094a715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a094a40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a094a789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ed2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ed2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ed2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ed2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a0943ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a0943cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a09421b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a090d10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a090d0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ed2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ed2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ed2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a090d0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c (2983 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf8x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv1i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_u8m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e8_v_i8mf8x8_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f65abc315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f65abc00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f65abc389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1301e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1301ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1301e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1301e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f65ab58e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f65ab58c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f65ab3db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f65a7ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f65a7ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1301e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1301e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1301e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f65a7eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c (2984 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055da2353915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055da235360f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055da2353989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3408333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f340838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3408333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f340831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055da234cee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055da234cec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055da234b3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055da231630b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055da23162dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f340831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f340831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f340831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055da23162cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c (2985 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_f16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_i16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_u16m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_ # | ... # `---data was truncated (10240/10396) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e8ca29215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8ca28f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e8ca29289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85a6705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85a675c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85a6705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85a66ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8ca227e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8ca227c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e8ca20cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8c9ebc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e8c9ebbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85a66eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85a66ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85a66ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e8c9ebbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c (2986 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_f64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8f64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m2_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv2i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m4_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv4i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_i64m8_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv8i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse64_v_u64m1_tu( %maskedoff, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.nxv1i64.p0.i64( %0, ptr %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c (2987 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16mf2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m1_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m4_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vlse16_v_bf16m8_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv32bf16.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv32bf16.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fad5dbe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fad5dbb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fad5dbe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77d1b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77d1b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77d1b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77d1aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fad5d53e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fad5d53c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fad5d38b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fad59e80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fad59e7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f77d1aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77d1aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77d1aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fad59e7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c (2988 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple aarch64-linux -target-feature +neon -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-linux" # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8(<8 x i8> %x) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %x.addr, align 8 # | %shuffle = shufflevector <8 x i8> %0, <8 x i8> %1, <8 x i32> # | ret <8 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <8 x i8> @test_8x8_v(<8 x i8> %x, <8 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <8 x i8>, align 8 # | %p.addr = alloca <8 x i8>, align 8 # | store <8 x i8> %x, ptr %x.addr, align 8 # | store <8 x i8> %p, ptr %p.addr, align 8 # | %0 = load <8 x i8>, ptr %x.addr, align 8 # | %1 = load <8 x i8>, ptr %p.addr, align 8 # | %mask = and <8 x i8> %1, splat (i8 7) # | %shuf_idx = extractelement <8 x i8> %mask, i64 0 # | %shuf_elt = extractelement <8 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <8 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <8 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <8 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <8 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <8 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <8 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <8 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <8 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <8 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <8 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <8 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <8 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <8 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <8 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <8 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <8 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <8 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <8 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <8 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <8 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <8 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <8 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | ret <8 x i8> %shuf_ins21 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16(<16 x i8> %x) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %x.addr, align 16 # | %shuffle = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> # | ret <16 x i8> %shuffle # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <16 x i8> @test_8x16_v(<16 x i8> %x, <16 x i8> noundef %p) #0 { # | entry: # | %x.addr = alloca <16 x i8>, align 16 # | %p.addr = alloca <16 x i8>, align 16 # | store <16 x i8> %x, ptr %x.addr, align 16 # | store <16 x i8> %p, ptr %p.addr, align 16 # | %0 = load <16 x i8>, ptr %x.addr, align 16 # | %1 = load <16 x i8>, ptr %p.addr, align 16 # | %mask = and <16 x i8> %1, splat (i8 15) # | %shuf_idx = extractelement <16 x i8> %mask, i64 0 # | %shuf_elt = extractelement <16 x i8> %0, i8 %shuf_idx # | %shuf_ins = insertelement <16 x i8> poison, i8 %shuf_elt, i64 0 # | %shuf_idx1 = extractelement <16 x i8> %mask, i64 1 # | %shuf_elt2 = extractelement <16 x i8> %0, i8 %shuf_idx1 # | %shuf_ins3 = insertelement <16 x i8> %shuf_ins, i8 %shuf_elt2, i64 1 # | %shuf_idx4 = extractelement <16 x i8> %mask, i64 2 # | %shuf_elt5 = extractelement <16 x i8> %0, i8 %shuf_idx4 # | %shuf_ins6 = insertelement <16 x i8> %shuf_ins3, i8 %shuf_elt5, i64 2 # | %shuf_idx7 = extractelement <16 x i8> %mask, i64 3 # | %shuf_elt8 = extractelement <16 x i8> %0, i8 %shuf_idx7 # | %shuf_ins9 = insertelement <16 x i8> %shuf_ins6, i8 %shuf_elt8, i64 3 # | %shuf_idx10 = extractelement <16 x i8> %mask, i64 4 # | %shuf_elt11 = extractelement <16 x i8> %0, i8 %shuf_idx10 # | %shuf_ins12 = insertelement <16 x i8> %shuf_ins9, i8 %shuf_elt11, i64 4 # | %shuf_idx13 = extractelement <16 x i8> %mask, i64 5 # | %shuf_elt14 = extractelement <16 x i8> %0, i8 %shuf_idx13 # | %shuf_ins15 = insertelement <16 x i8> %shuf_ins12, i8 %shuf_elt14, i64 5 # | %shuf_idx16 = extractelement <16 x i8> %mask, i64 6 # | %shuf_elt17 = extractelement <16 x i8> %0, i8 %shuf_idx16 # | %shuf_ins18 = insertelement <16 x i8> %shuf_ins15, i8 %shuf_elt17, i64 6 # | %shuf_idx19 = extractelement <16 x i8> %mask, i64 7 # | %shuf_elt20 = extractelement <16 x i8> %0, i8 %shuf_idx19 # | %shuf_ins21 = insertelement <16 x i8> %shuf_ins18, i8 %shuf_elt20, i64 7 # | %shuf_idx22 = extractelement <16 x i8> %mask, i64 8 # | %shuf_elt23 = extractelement <16 x i8> %0, i8 %shuf_idx22 # | %shuf_ins24 = insertelement <16 x i8> %shuf_ins21, i8 %shuf_elt23, i64 8 # | %shuf_idx25 = extractelement <16 x i8> %mask, i64 9 # | %shuf_elt26 = extractelement <16 x i8> %0, i8 %shuf_idx25 # | %shuf_ins27 = insertelement <16 x i8> %shuf_ins24, i8 %shuf_elt26, i64 9 # | %shuf_idx28 = extractelement <16 x i8> %mask, i64 10 # | %shuf_elt29 = extractelement <16 x i8> %0, i8 %shuf_idx28 # | %shuf_ins30 = insertelement <16 x i8> %shuf_ins27, i8 %shuf_elt29, i64 10 # | %shuf_idx31 = extractelement <16 x i8> %mask, i64 11 # | %shuf_elt32 = extractelement <16 x i8> %0, i8 %shuf_idx31 # | %shuf_ins33 = insertelement <16 x i8> %shuf_ins30, i8 %shuf_elt32, i64 11 # | %shuf_idx34 = extractelement <16 x i8> %mask, i64 12 # | %shuf_elt35 = extractelement <16 x i8> %0, i8 %shuf_idx34 # | %shuf_ins36 = insertelement <16 x i8> %shuf_ins33, i8 %shuf_elt35, i64 12 # | %shuf_idx37 = extractelement <16 x i8> %mask, i64 13 # | %shuf_elt38 = extractelement <16 x i8> %0, i8 %shuf_idx37 # | %shuf_ins39 = insertelement <16 x i8> %shuf_ins36, i8 %shuf_elt38, i64 13 # | %shuf_idx40 = extractelement <16 x i8> %mask, i64 14 # | %shuf_elt41 = extractelement <16 x i8> %0, i8 %shuf_idx40 # | %shuf_ins42 = insertelement <16 x i8> %shuf_ins39, i8 %shuf_elt41, i64 14 # | %shuf_idx43 = extractelement <16 x i8> %mask, i64 15 # | %shuf_elt44 = extractelement <16 x i8> %0, i8 %shuf_idx43 # | %shuf_ins45 = insertelement <16 x i8> %shuf_ins42, i8 %shuf_elt44, i64 15 # | ret <16 x i8> %shuf_ins45 # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon" } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d0b3f615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d0b3f30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d0b3f689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff41d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff41d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff41d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff41d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d0b38be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d0b38bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d0b370b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d0b0200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d0b01fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff41d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff41d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff41d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d0b01fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/builtin-shufflevector-fp8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c (2989 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056442fec015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056442febd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056442fec089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007febc9449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007febc94a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007febc9449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007febc9431507 abort ./stdlib/abort.c:85:3 # | #7 0x000056442fe55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056442fe55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056442fe3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056442faea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056442fae9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007febc9432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007febc94330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007febc94330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056442fae9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c (2990 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b663fff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b663ffc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b663fff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3c93a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3c93a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3c93a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3c93a03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b663f94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b663f94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b663f79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b663c290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b663c28dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3c93a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3c93a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3c93a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b663c28cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c (2991 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c17a1c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c17a1c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c17a1c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f725d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f725d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f725d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f725d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c17a158e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c17a158c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c17a13db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c179ded0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c179decdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f725d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f725d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f725d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c179deccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c (2992 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055963a7d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055963a7d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055963a7d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbec2e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbec2ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbec2e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbec2e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055963a769e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055963a769c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055963a74eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055963a3fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055963a3fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbec2e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbec2e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbec2e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055963a3fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c (2993 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564806f3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564806f350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564806f3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75f1049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75f10a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75f1049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75f1031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564806ecde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564806ecdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564806eb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564806b620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564806b61dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f75f1032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75f10330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75f10330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564806b61cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c (2994 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557dce79f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557dce79c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557dce79f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6ecfe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6ecfea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6ecfe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6ecfe31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557dce734e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557dce734c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557dce719b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557dce3c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557dce3c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6ecfe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6ecfe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6ecfe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557dce3c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c (2995 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/25086) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056508531315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650853100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056508531389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b62533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b6258a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b62533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b6251b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650852a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650852a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056508528db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565084f3d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565084f3cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b6251cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b6251d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b6251d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565084f3ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c (2996 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_f16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_i16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf4x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16mf2x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_u16m1x6(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, pt # | ... # `---data was truncated (10240/24016) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555b42a1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555b42a110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555b42a1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fadce849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fadce8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fadce849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fadce831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555b429a9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555b429a9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555b4298eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555b4263e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555b4263ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fadce832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fadce8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fadce8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555b4263dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c (2997 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556688c6415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556688c610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556688c6489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb2c4905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb2c495c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb2c4905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb2c48ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556688bf9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556688bf9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556688bdeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055668888e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055668888ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb2c48eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb2c48ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb2c48ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055668888dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c (2998 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055897eec915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055897eec60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055897eec989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbd35133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbd3518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbd35133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbd3511b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055897ee5ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055897ee5ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055897ee43b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055897eaf30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055897eaf2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbd3511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbd3511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbd3511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055897eaf2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c (2999 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei8_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, p # | ... # `---data was truncated (10240/14521) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005650bd6a915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005650bd6a60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005650bd6a989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3addd05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3addd5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3addd05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3addced507 abort ./stdlib/abort.c:85:3 # | #7 0x00005650bd63ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005650bd63ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005650bd623b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005650bd2d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005650bd2d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3addceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3addcef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3addcef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005650bd2d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c (3000 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-neon-vcadd.c (3001 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vcadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple armv8.3a-arm-none-eabi -target-cpu generic -target-feature +fullfp16 -mfloat-abi soft -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "armv8.3a-arm-none-eabi" # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot90(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot90_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot90_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot90.v4f16(<4 x half> %vcadd_rot90_f16.i, <4 x half> %vcadd_rot90_f161.i) # | %vcadd_rot90_f163.i = bitcast <4 x half> %vcadd_rot90_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot90(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot90_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot90_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot90_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot90.v2f32(<2 x float> %vcadd_rot90_f32.i, <2 x float> %vcadd_rot90_f321.i) # | %vcadd_rot90_f323.i = bitcast <2 x float> %vcadd_rot90_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot90(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot90_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot90_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot90.v8f16(<8 x half> %vcaddq_rot90_f16.i, <8 x half> %vcaddq_rot90_f161.i) # | %vcaddq_rot90_f163.i = bitcast <8 x half> %vcaddq_rot90_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot90(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__p1.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x float>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %result = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | store <4 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot90_f32.i = bitcast <16 x i8> %2 to <4 x float> # | %vcaddq_rot90_f321.i = bitcast <16 x i8> %3 to <4 x float> # | %vcaddq_rot90_f322.i = call <4 x float> @llvm.arm.neon.vcadd.rot90.v4f32(<4 x float> %vcaddq_rot90_f32.i, <4 x float> %vcaddq_rot90_f321.i) # | %vcaddq_rot90_f323.i = bitcast <4 x float> %vcaddq_rot90_f322.i to <16 x i8> # | store <16 x i8> %vcaddq_rot90_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x float>, ptr %ref.tmp.i, align 8 # | store <4 x float> %4, ptr %__ret.i, align 8 # | %5 = load <4 x float>, ptr %__ret.i, align 8 # | store <4 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x4_rot270(<4 x half> noundef %a, <4 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <4 x half>, align 8 # | %__p1.addr.i = alloca <4 x half>, align 8 # | %__ret.i = alloca <4 x half>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <4 x half>, align 8 # | %b.addr = alloca <4 x half>, align 8 # | %result = alloca <4 x half>, align 8 # | store <4 x half> %a, ptr %a.addr, align 8 # | store <4 x half> %b, ptr %b.addr, align 8 # | %0 = load <4 x half>, ptr %a.addr, align 8 # | %1 = load <4 x half>, ptr %b.addr, align 8 # | store <4 x half> %0, ptr %__p0.addr.i, align 8 # | store <4 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f16.i = bitcast <8 x i8> %2 to <4 x half> # | %vcadd_rot270_f161.i = bitcast <8 x i8> %3 to <4 x half> # | %vcadd_rot270_f162.i = call <4 x half> @llvm.arm.neon.vcadd.rot270.v4f16(<4 x half> %vcadd_rot270_f16.i, <4 x half> %vcadd_rot270_f161.i) # | %vcadd_rot270_f163.i = bitcast <4 x half> %vcadd_rot270_f162.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <4 x half>, ptr %ref.tmp.i, align 8 # | store <4 x half> %4, ptr %__ret.i, align 8 # | %5 = load <4 x half>, ptr %__ret.i, align 8 # | store <4 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x2_rot270(<2 x float> noundef %a, <2 x float> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__p1.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x float>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | %b.addr = alloca <2 x float>, align 8 # | %result = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | store <2 x float> %b, ptr %b.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | %1 = load <2 x float>, ptr %b.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | store <2 x float> %1, ptr %__p1.addr.i, align 8 # | %2 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <8 x i8>, ptr %__p1.addr.i, align 8 # | %vcadd_rot270_f32.i = bitcast <8 x i8> %2 to <2 x float> # | %vcadd_rot270_f321.i = bitcast <8 x i8> %3 to <2 x float> # | %vcadd_rot270_f322.i = call <2 x float> @llvm.arm.neon.vcadd.rot270.v2f32(<2 x float> %vcadd_rot270_f32.i, <2 x float> %vcadd_rot270_f321.i) # | %vcadd_rot270_f323.i = bitcast <2 x float> %vcadd_rot270_f322.i to <8 x i8> # | store <8 x i8> %vcadd_rot270_f323.i, ptr %ref.tmp.i, align 8 # | %4 = load <2 x float>, ptr %ref.tmp.i, align 8 # | store <2 x float> %4, ptr %__ret.i, align 8 # | %5 = load <2 x float>, ptr %__ret.i, align 8 # | store <2 x float> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo16x8_rot270(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %__p0.addr.i = alloca <8 x half>, align 8 # | %__p1.addr.i = alloca <8 x half>, align 8 # | %__ret.i = alloca <8 x half>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %result = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | store <8 x half> %0, ptr %__p0.addr.i, align 8 # | store <8 x half> %1, ptr %__p1.addr.i, align 8 # | %2 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %3 = load <16 x i8>, ptr %__p1.addr.i, align 8 # | %vcaddq_rot270_f16.i = bitcast <16 x i8> %2 to <8 x half> # | %vcaddq_rot270_f161.i = bitcast <16 x i8> %3 to <8 x half> # | %vcaddq_rot270_f162.i = call <8 x half> @llvm.arm.neon.vcadd.rot270.v8f16(<8 x half> %vcaddq_rot270_f16.i, <8 x half> %vcaddq_rot270_f161.i) # | %vcaddq_rot270_f163.i = bitcast <8 x half> %vcaddq_rot270_f162.i to <16 x i8> # | store <16 x i8> %vcaddq_rot270_f163.i, ptr %ref.tmp.i, align 8 # | %4 = load <8 x half>, ptr %ref.tmp.i, align 8 # | store <8 x half> %4, ptr %__ret.i, align 8 # | %5 = load <8 x half>, ptr %__ret.i, align 8 # | store <8 x half> %5, ptr %result, align 8 # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @foo32x4_rot270(<4 x float> noundef %a, <4 # | ... # `---data was truncated (10240/13572) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa -o - # | #0 0x0000559073b1715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559073b140f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559073b1789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8b2a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8b2aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8b2a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8b2a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559073aace2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559073aacc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559073a91b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005590737410b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559073740dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff8b2a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8b2a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8b2a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559073740cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c (3002 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055834a29515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055834a2920f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055834a29589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4cad533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4cad58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4cad533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4cad51b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055834a22ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055834a22ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055834a20fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558349ebf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558349ebedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4cad51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4cad51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4cad51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558349ebecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c (3003 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_f16(<8 x half> noundef %a, <8 x half> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0) # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %2) # | %4 = call <8 x half> @llvm.minnum.v8f16(<8 x half> %1, <8 x half> %3) # | ret <8 x half> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.fabs.v8f16(<8 x half>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0) # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %2) # | %4 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %1, <4 x float> %3) # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1 # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmaq_m_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = load <8 x half>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half> %0, <8 x half> %1, <8 x i1> %4) # | ret <8 x half> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x half> @llvm.arm.mve.vminnma.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmaq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = load <4 x float>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float> %0, <4 x float> %1, <4 x i1> %4) # | ret <4 x float> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x float> @llvm.arm.mve.vminnma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>) #2 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055831755815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005583175550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055831755889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe583f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe583f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe583f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe583f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005583174ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005583174edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005583174d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005583171820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558317181dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe583f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe583f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe583f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558317181cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c --check-prefixes=CHECK,CHECK-NOSTRICT # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c (3004 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i32. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc954ba15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc954b70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc954ba89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9b6ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9b6ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9b6ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9b6ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc9544fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc9544fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc95434b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc950e40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc950e3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9b6ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9b6ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9b6ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc950e3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c (3005 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not=' @llvm.fma.' --implicit-check-not=' @llvm.sqrt.' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +neon -o - -target-feature +fullfp16 -ffp-exception-behavior=strict -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vsqrth_f16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %__s0, align 2 # | %vsqrt = call half @llvm.experimental.constrained.sqrt.f16(half %1, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %vsqrt, ptr %ref.tmp, align 2 # | %2 = load half, ptr %ref.tmp, align 2 # | store half %2, ptr %__ret, align 2 # | %3 = load half, ptr %__ret, align 2 # | store half %3, ptr %tmp, align 2 # | %4 = load half, ptr %tmp, align 2 # | ret half %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata) #1 # | # | ; Function Attrs: noinline nounwind strictfp # | define dso_local half @test_vfmah_f16(half noundef %a, half noundef %b, half noundef %c) #0 { # | entry: # | %a.addr = alloca half, align 2 # | %b.addr = alloca half, align 2 # | %c.addr = alloca half, align 2 # | %__ret = alloca half, align 2 # | %__s0 = alloca half, align 2 # | %__s1 = alloca half, align 2 # | %__s2 = alloca half, align 2 # | %ref.tmp = alloca half, align 2 # | %tmp = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | store half %b, ptr %b.addr, align 2 # | store half %c, ptr %c.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | store half %0, ptr %__s0, align 2 # | %1 = load half, ptr %b.addr, align 2 # | store half %1, ptr %__s1, align 2 # | %2 = load half, ptr %c.addr, align 2 # | store half %2, ptr %__s2, align 2 # | %3 = load half, ptr %__s0, align 2 # | %4 = load half, ptr %__s1, align 2 # | %5 = load half, ptr %__s2, align 2 # | %6 = call half @llvm.experimental.constrained.fma.f16(half %4, half %5, half %3, metadata !"round.tonearest", metadata !"fpexcept.strict") #2 # | store half %6, ptr %ref.tmp, align 2 # | %7 = load half, ptr %ref.tmp, align 2 # | store half %7, ptr %__ret, align 2 # | %8 = load half, ptr %__ret, align 2 # | store half %8, ptr %tmp, align 2 # | %9 = load half, ptr %tmp, align 2 # | ret half %9 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) # | declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1 # | # | attributes #0 = { noinline nounwind strictfp "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon" } # | attributes #1 = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) } # | attributes #2 = { strictfp } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,simplifycfg # | #0 0x000055c39f11915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c39f1160f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c39f11989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff56b249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff56b2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff56b249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff56b231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c39f0aee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c39f0aec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c39f093b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c39ed430b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c39ed42dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff56b232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff56b2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff56b2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c39ed42cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM '--implicit-check-not= @llvm.fma.' '--implicit-check-not= @llvm.sqrt.' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/neon/fullfp16-constrained.c --check-prefixes=ALL,LLVM --implicit-check-not= @llvm.fma. --implicit-check-not= @llvm.sqrt. # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c (3006 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei8_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558063b7015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558063b6d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558063b7089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5012505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f501255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5012505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f50124ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558063b05e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558063b05c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558063aeab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055806379a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558063799dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f50124eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f50124ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f50124ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558063799cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c (3007 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e32_v_i32m1x7_m( %mask, ptr noundef % # | ... # `---data was truncated (10240/14001) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558da7c6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558da7c620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558da7c6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdcdce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdcdcea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdcdce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdcdce31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558da7bfae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558da7bfac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558da7bdfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558da788f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558da788edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdcdce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdcdce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdcdce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558da788ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c (3008 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocall # | ... # `---data was truncated (10240/12425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b6dbd7915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b6dbd760f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b6dbd7989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd20d449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd20d4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd20d449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd20d431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b6dbd0ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b6dbd0ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b6dbcf3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b6db9a30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b6db9a2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd20d432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd20d4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd20d4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b6db9a2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c (3009 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfwma -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32mf2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m1_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m2_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vv_f32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmaccbf16.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwmaccbf16_vf_f32m4_tu( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c (3010 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u8m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv64i8.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv64i8.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u16m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv32i16.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv32i16.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32mf2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv1i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv1i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv2i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv2i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m2(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv4i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv4i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m4(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv8i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv8i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u32m8(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %vl.addr, align 8 # | %1 = call @llvm.riscv.vid.nxv16i32.i64( poison, i64 %0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vid.nxv16i32.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vid_v_u64m1(i64 noundef %vl) #0 { # | entry: # | %vl.addr = alloca i64, align 8 # | store i64 %vl, ptr %vl.addr, align # | ... # `---data was truncated (10240/30303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c8ce07815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c8ce0750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c8ce07889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f06c8733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f06c878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f06c8733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f06c871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c8ce00de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c8ce00dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c8cdff2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c8cdca20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c8cdca1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f06c871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f06c871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f06c871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c8cdca1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c (3011 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei64_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005623a403f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005623a403c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005623a403f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1dcce49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1dccea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1dcce49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1dcce31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005623a3fd4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005623a3fd4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005623a3fb9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005623a3c690b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005623a3c68dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1dcce32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1dcce330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1dcce330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005623a3c68cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c (3012 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_i8m1x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv8i8_6t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf8x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv1i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf4x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %3, i64 3, i64 3) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8ff_v_u8mf2x6_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , # | ... # `---data was truncated (10240/12668) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b85637a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8563770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b85637a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1405105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f140515c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1405105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14050ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b85630fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b85630fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8562f4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b855fa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b855fa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14050eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14050ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14050ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b855fa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c (3013 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 3) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = c # | ... # `---data was truncated (10240/16451) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0e440815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d0e44050f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d0e440889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0ca7b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0ca7b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0ca7b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0ca7b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0e439de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d0e439dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d0e4382b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d0e40320b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d0e4031dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0ca7b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0ca7b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0ca7b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0e4031cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c (3014 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv1bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16mf2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv2bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m1( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv4bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m2( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv8bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vunzipe_v_bf16m4( %vs, i64 noundef %vl) #0 { # | entry: # | %vs.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs, ptr %vs.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vunzipe.nxv16bf16.nxv32bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvzip,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0_zvzip0p3"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c03bc7315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c03bc700f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c03bc7389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f07bac1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f07bac725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f07bac1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f07bac03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c03bc08e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c03bc08c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c03bbedb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c03b89d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c03b89cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f07bac04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f07bac050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f07bac050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c03b89ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c (3015 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561aa220715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561aa22040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561aa220789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8868d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8868d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8868d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8868d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561aa219ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561aa219cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561aa2181b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561aa1e310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561aa1e30dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8868d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8868d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8868d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561aa1e30cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c (3016 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, al # | ... # `---data was truncated (10240/12389) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6f6cb815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6f6cb50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6f6cb889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9e94a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9e94aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9e94a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9e94a31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6f6c4de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6f6c4dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6f6c32b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6f68e20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6f68e1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9e94a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9e94a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9e94a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6f68e1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c (3017 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv1i32.nxv1i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv2i32.nxv2i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv4i32.nxv4i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv8i32.nxv8i32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm3me_vv_u32m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm3me.nxv16i32.nxv16i32.i64(, , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005570ae34015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005570ae33d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005570ae34089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fddb0b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fddb0b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fddb0b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fddb0aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005570ae2d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005570ae2d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005570ae2bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005570adf6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005570adf69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fddb0aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fddb0aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fddb0aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005570adf69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c (3018 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562dc301215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562dc300f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562dc301289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4ff1f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4ff1f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4ff1f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4ff1f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562dc2fa7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562dc2fa7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562dc2f8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562dc2c3c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562dc2c3bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4ff1f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4ff1f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4ff1f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562dc2c3bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c (3019 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056014ff3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056014ff330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056014ff3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa607f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa607f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa607f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa607f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056014fecbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056014fecbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056014feb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056014fb600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056014fb5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa607f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa607f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa607f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056014fb5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c (3020 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575eefe215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575eefdf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575eefe289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fae17f05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fae17f5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fae17f05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fae17eed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575eef77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575eef77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575eef5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575eec0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575eec0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fae17eeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fae17eef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fae17eef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575eec0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c (3021 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m2( %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load float, ptr %rs1.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64( poison, %0, float %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf8_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf4_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8mf2_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_x_f_qf_i8m1_m( %mask, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.i64( poison, %1, float %2, %0, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/12433) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560c320ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560c320ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560c320ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4a48d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4a48d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4a48d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4a48d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560c32084e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560c32084c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560c32069b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560c31d190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560c31d18dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4a48d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4a48d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4a48d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560c31d18cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c (3022 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target # | ... # `---data was truncated (10240/10700) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e66b7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e66b7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e66b7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc742933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc74298a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc742933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc74291b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e66b13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e66b13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e66af8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e667a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e667a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc74291cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc74291d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc74291d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e667a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c (3023 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.nxv1f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf4_b64_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.nxv2f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16mf2_b32_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.nxv4f16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_f16m1_b16_mu( %mask, %maskedoff, %op1, half noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load half, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64( %1, %2, half %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.mask.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_f16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfgt.mask.nxv8f16.nxv8f16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwi # | ... # `---data was truncated (10240/44369) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565033fe815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565033fe50f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565033fe889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3a38849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3a388a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3a38849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3a38831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565033f7de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565033f7dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565033f62b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565033c120b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565033c11dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3a38832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3a388330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3a388330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565033c11cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c (3024 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv64i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv32i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv16i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv8i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv4i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv2i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vmsof.nxv1i1.i64( %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv64i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv64i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv32i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv32i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv16i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv16i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv8i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsof.mask.nxv8i1.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsof_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmsof.mask.nxv4i1.i64( poison, %1, %0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback n # | ... # `---data was truncated (10240/13031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005644d900615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644d90030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005644d900689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fec4d105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fec4d15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fec4d105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fec4d0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005644d8f9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005644d8f9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005644d8f80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644d8c300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644d8c2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fec4d0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fec4d0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fec4d0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644d8c2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c (3025 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf8( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf8( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf4( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf4( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8mf2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8mf2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m1( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m1( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wv_u8m2( %op1, %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %shift, ptr %shift.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %shift.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vnclipu_wx_u8m2( %op1, i64 noundef %shift, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %shift.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %shift, ptr %shift.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %shift.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i64.i64( poison, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c (3026 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei8_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 8), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb734b915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb734b60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb734b989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb337933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb33798a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb337933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb33791b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb7344ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb7344ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb73433b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb730e30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb730e2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb33791cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb33791d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb33791d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb730e2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm64-crc32.c (3027 of 27911) ******************** TEST 'Clang :: CodeGen/arm64-crc32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple arm64-none-linux-gnu -target-feature +crc -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "arm64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32b(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32b(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32b(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cb(i32 noundef %a, i8 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i8, align 1 # | store i32 %a, ptr %a.addr, align 4 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i8, ptr %b.addr, align 1 # | %2 = zext i8 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32cb(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cb(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32h(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32h(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32h(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32ch(i32 noundef %a, i16 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i16, ptr %b.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call i32 @llvm.aarch64.crc32ch(i32 %0, i32 %2) # | ret i32 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32ch(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32w(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32w(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32w(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cw(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | %2 = call i32 @llvm.aarch64.crc32cw(i32 %0, i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cw(i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32d(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32x(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32x(i32, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @crc32cd(i32 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i64, align 8 # | store i32 %a, ptr %a.addr, align 4 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i32 @llvm.aarch64.crc32cx(i32 %0, i64 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.aarch64.crc32cx(i32, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4, !5} # | !llvm.ident = !{!6} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{i32 1, !"ptrauth-sign-personality", i32 0} # | !4 = !{i32 1, !"aarch64-elf-pauthabi-platform", i32 268435458} # | !5 = !{i32 1, !"aarch64-elf-pauthabi-version", i32 0} # | !6 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cde0f8e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cde0f8b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cde0f8e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8761849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87618a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8761849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8761831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cde0f23e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cde0f23c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cde0f08b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cde0bb80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cde0bb7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8761832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87618330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87618330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cde0bb7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm64-crc32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c (3028 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 5), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f37273e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f37273b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f37273e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f99cbb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f99cbb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f99cbb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f99cbb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3726d3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f3726d3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f3726b8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f3723680b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f372367dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f99cbb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f99cbb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f99cbb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f372367cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c (3029 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m4_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f16m8_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32mf2_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64( %0, %1, %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredusum_vs_f32m1_f64m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca # | ... # `---data was truncated (10240/60342) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c7067515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c706720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c7067589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f081b21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f081b2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f081b21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f081b203507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c7060ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c7060ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c705efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c7029f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c7029edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f081b204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f081b2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f081b2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c7029ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c (3030 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrsqrt7.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16mf2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrsqrt7.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrsqrt7_v_bf16m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c (3031 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560d7c74c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560d7c7490f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560d7c74c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2cb3b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2cb3b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2cb3b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2cb3aed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560d7c6e1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560d7c6e1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560d7c6c6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560d7c3760b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560d7c375dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2cb3aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2cb3aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2cb3aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560d7c375cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c (3032 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei8_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 5), ptr captures(none), ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c (3033 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | % # | ... # `---data was truncated (10240/39922) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c486ac615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c486ac30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c486ac689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5624449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56244a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5624449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5624431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c486a5be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c486a5bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c486a40b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4866f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4866efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5624432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56244330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56244330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4866efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c (3034 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmslt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmslt.mask.nxv8i8.nxv8i8.i64(, , , , i64) #1 # | # | # | ... # `---data was truncated (10240/63571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564254d3d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564254d3a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564254d3d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffb57649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffb576a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffb57649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffb57631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564254cd2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564254cd2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564254cb7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005642549670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564254966dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffb57632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffb576330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffb576330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564254966cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c (3035 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_s_u_w4_i8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.s.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a3cf9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a3cf930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a3cf9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f988d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f988d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f988d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f988d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a3cf2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a3cf2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a3cf10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a3cbc00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a3cbbfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f988d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f988d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f988d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a3cbbfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/predicates.c (3036 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/predicates.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes='mem2reg,sroa,early-cse<>' | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %3) # | %5 = and <8 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %3) # | %5 = and <4 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.vctp64(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <2 x i1> @llvm.arm.mve.vctp64(i32 %3) # | %5 = and <2 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v2i1(<2 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %0) # | %2 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %1) # | %3 = trunc i32 %2 to i16 # | ret i16 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.vctp8(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | %p.addr = alloca i16, align 2 # | store i32 %a, ptr %a.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %1) # | %3 = load i32, ptr %a.addr, align 4 # | %4 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %3) # | %5 = and <16 x i1> %2, %4 # | %6 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %5) # | %7 = trunc i32 %6 to i16 # | ret i16 %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc zeroext i16 @test_vpnot(i16 noundef zeroext %a) #0 { # | entry: # | %a.addr = alloca i16, align 2 # | store i16 %a, ptr %a.addr, align 2 # | %0 = load i16, ptr %a.addr, align 2 # | %1 = xor i16 %0, -1 # | ret i16 %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x half>, ptr %a.addr, align 8 # | %4 = load <8 x half>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x half> %3, <8 x half> %4 # | ret <8 x half> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x float>, ptr %a.addr, align 8 # | %4 = load <4 x float>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x float> %3, <4 x float> %4 # | ret <4 x float> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vpselq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = load <8 x i16>, ptr %b.addr, align 8 # | %5 = select <8 x i1> %2, <8 x i16> %3, <8 x i16> %4 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vpselq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = load <4 x i32>, ptr %b.addr, align 8 # | %5 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %4 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vpselq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 8 # | %b.addr = alloca <2 x i64>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %a, ptr %a.addr, align 8 # | store <2 x i64> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <2 x i64>, ptr %a.addr, align 8 # | %4 = bitcast <2 x i64> %3 to <4 x i32> # | %5 = load <2 x i64>, ptr %b.addr, align 8 # | %6 = bitcast <2 x i64> %5 to <4 x i32> # | %7 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %6 # | %8 = bitcast <4 x i32> %7 to <2 x i64> # | ret <2 x i64> %8 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vpselq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, ali # | ... # `---data was truncated (10240/13928) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S '-passes=mem2reg,sroa,early-cse<>' # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa,early-cse<> # | #0 0x0000556e47c6b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556e47c680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556e47c6b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa50db05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa50db5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa50db05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa50daed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556e47c00e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556e47c00c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556e47be5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556e478950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556e47894dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa50daeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa50daef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa50daef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556e47894cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/predicates.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c (3037 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ed98fd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ed98fa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ed98fd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb809505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb80955c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb809505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb8094ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ed9892e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ed9892c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ed9877b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ed95270b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ed9526dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb8094eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb8094ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb8094ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ed9526cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c (3038 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfvfexpa64e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f64.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f64.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv1f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv2f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv4f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m8_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.mask.nxv8f64.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f64m1_tumu( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 # | ... # `---data was truncated (10240/18303) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9333e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9333e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9333e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f59d7733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f59d778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f59d7733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f59d771b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e93337ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e93337ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e93335fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e93300f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e93300edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f59d771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f59d771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f59d771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e93300ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vldr.c (3039 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vldr.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %1, i32 80) # | %3 = extractvalue { <4 x i32>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x i32>, <4 x i32> } %2, 0 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(ptr noundef %addr) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | store ptr %addr, ptr %addr.addr, align 4 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <4 x i32>, ptr %0, align 8 # | %2 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %1, i32 64) # | %3 = extractvalue { <4 x float>, <4 x i32> } %2, 1 # | store <4 x i32> %3, ptr %0, align 8 # | %4 = extractvalue { <4 x float>, <4 x i32> } %2, 0 # | ret <4 x float> %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(ptr noundef %addr, i16 noundef zeroext %p) #0 { # | entry: # | %addr.addr = alloca ptr, align 4 # | %p.addr = alloca i16, align 2 # | store ptr %addr, ptr %addr.addr, align 4 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load ptr, ptr %addr.addr, align 4 # | %1 = load <2 x i64>, ptr %0, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %1, i32 656, <2 x i1> %4) # | %6 = extractvalue { <2 x i64>, <2 x i64> } %5, 1 # | store <2 x i64> %6, ptr %0, align 8 # | %7 = extractvalue { <2 x i64>, <2 x i64> } %5, 0 # | ret <2 x i64> %7 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i1>) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+armv8.1-m.main,+mve.fp,+thumb-mode" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | attributes #2 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !2, !3, !4} # | !llvm.ident = !{!5} # | # | !0 = !{i32 1, !"float-abi", !"hard"} # | !1 = !{i32 1, !"target-abi", !"aapcs"} # | !2 = !{i32 1, !"min_enum_size", i32 4} # | !3 = !{i32 4, !"arm-eabi-fp-denormal", i32 1} # | !4 = !{i32 8, !"arm-eabi-fp-number-model", i32 3} # | !5 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055951908c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595190890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055951908c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd106a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd106aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd106a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd106a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559519021e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559519021c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559519006b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559518cb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559518cb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd106a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd106a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd106a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559518cb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vldr.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c (3040 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3bf6bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3bf6b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3bf6bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc11ed33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc11ed8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc11ed33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc11ed1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3bf651e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3bf651c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3bf636b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3bf2e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3bf2e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc11ed1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc11ed1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc11ed1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3bf2e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c (3041 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_f32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv4i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_i32m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 4 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 4 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e32ff_v_u32mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | ... # `---data was truncated (10240/60691) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ce4359015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ce4358d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ce4359089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa85fb05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa85fb5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa85fb05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa85faed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ce43525e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ce43525c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ce4350ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ce431ba0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ce431b9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa85faeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa85faef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa85faef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ce431b9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c (3042 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_u_u_w4_u8m8_u8m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.u.u.i64.nxv64i8.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmm32a8i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmm32a8i0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056151e99615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056151e9930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056151e99689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f16fae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f16faea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f16fae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f16fae31507 abort ./stdlib/abort.c:85:3 # | #7 0x000056151e92be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056151e92bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056151e910b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056151e5c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056151e5bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f16fae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f16fae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f16fae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056151e5bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c (3043 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564be45c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564be45c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564be45c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4632305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f463235c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4632305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f46322ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564be455be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564be455bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564be4540b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564be41f00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564be41efdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f46322eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f46322ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f46322ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564be41efcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c (3044 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d51189815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5118950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d51189889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ab1705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ab175c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ab1705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ab16ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d51182de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d51182dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d511812b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5114c20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5114c1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ab16eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ab16ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ab16ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5114c1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c (3045 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmandn_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmandn.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmandn.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556a62eea15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556a62ee70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556a62eea89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4b8c249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4b8c2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4b8c249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4b8c231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556a62e7fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556a62e7fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556a62e64b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556a62b140b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556a62b13dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4b8c232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4b8c2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4b8c2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556a62b13cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c (3046 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8f64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8i64.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m1(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv1i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_u64m2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { , i64 } @llvm.riscv.vleff.nxv2i64.i64.p0( poison, ptr %0, i64 %2) # | %4 = extractvalue { , i64 } %3, 0 # | %5 = extractvalue { , i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret %4 # | } # | # | ; Function Attrs # | ... # `---data was truncated (10240/26996) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564179b7c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564179b790f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564179b7c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff6f1c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff6f1c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff6f1c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff6f1c03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564179b11e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564179b11c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564179af6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005641797a60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005641797a5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff6f1c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff6f1c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff6f1c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005641797a5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c (3047 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64( poison, %0, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfabs_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1. # | ... # `---data was truncated (10240/30869) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556b5044015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556b5043d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556b5044089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1a8b133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1a8b18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1a8b133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1a8b11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556b503d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556b503d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556b503bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556b5006a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556b50069dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1a8b11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1a8b11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1a8b11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556b50069cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c (3048 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e64_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("r # | ... # `---data was truncated (10240/36023) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c78740715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7874040f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c78740789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb45cf05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb45cf5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb45cf05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb45ceed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c78739ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c78739cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c787381b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7870310b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c787030dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb45ceeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb45ceef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb45ceef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c787030cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c (3049 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u3 # | ... # `---data was truncated (10240/11880) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ac1d8715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ac1d840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ac1d8789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0115c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0115ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0115c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0115c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ac1d1ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ac1d1cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ac1d01b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ac19b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ac19b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0115c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0115c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0115c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ac19b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c (3050 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmsub.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmsub_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmsub.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret < # | ... # `---data was truncated (10240/34430) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f2c6d2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f2c6d200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f2c6d2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f01c9333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f01c938a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f01c9333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f01c931b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f2c6cb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f2c6cb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f2c6c9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f2c694d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f2c694cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f01c931cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f01c931d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f01c931d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2c694ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c (3051 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m1_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vv_u32m2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c (3052 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_bf16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte16.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_f16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_i16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte16_u16(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte16.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvfbfmin,+zvfhmin,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfhmin1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a9346c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a934690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a9346c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff98d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff98d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff98d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff98d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a93401e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a93401c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a933e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a930960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a93095dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff98d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff98d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff98d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a93095cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c (3053 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei64_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055635360c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005563536090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055635360c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd634449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd6344a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd634449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd634431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005563535a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005563535a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556353586b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005563532360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556353235dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd634432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd6344330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd6344330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556353235cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c (3054 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 6) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_f64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_i64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e64ff_v_u64m1x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.mask.triscv.vector.tuple_nxv8i8_5t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a24a6de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a24a6db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a24a6de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff559c1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff559c725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff559c1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff559c03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a24a673e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a24a673c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a24a658b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a24a3080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a24a307dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff559c04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff559c050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff559c050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a24a307cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c (3055 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2_tu(target("riscv.vector.tuple", , 2) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv # | ... # `---data was truncated (10240/53548) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558e9dd3815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558e9dd350f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558e9dd3889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c90133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c9018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c90133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c9011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558e9dccde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558e9dccdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558e9dcb2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558e9d9620b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558e9d961dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c9011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c9011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c9011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558e9d961cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c (3056 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", # | ... # `---data was truncated (10240/19492) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d8cf2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d8cf200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d8cf2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3268049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32680a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3268049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3268031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d8ceb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d8ceb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d8ce9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d8cb4d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d8cb4cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3268032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32680330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32680330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d8cb4ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c (3057 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005612a096215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005612a095f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005612a096289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcbed449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcbed4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcbed449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcbed431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005612a08f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005612a08f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005612a08dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005612a058c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005612a058bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcbed432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcbed4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcbed4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005612a058bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c (3058 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a16f -target-feature +xsfmm32a32f -target-feature +xsfmm64a64f -target-feature +zvfhmin -target-feature +zve64d -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w2_f16m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f32m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 4 # | %1 = load , ptr %vs1.addr, align 4 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv16f32(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_sf_mm_f_f_w1_f64m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 8 # | %vs1.addr = alloca , align 8 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store %vs1, ptr %vs1.addr, align 8 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 8 # | %1 = load , ptr %vs1.addr, align 8 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 1) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.f.f.i64.nxv8f64(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+xsfmm32a16f,+xsfmm32a32f,+xsfmm64a64f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfhmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvl32b1p0_zvl64b1p0_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm64a64f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055598e17815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055598e1750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055598e17889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b46d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b46d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b46d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b46d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055598e10de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055598e10dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055598e0f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055598dda20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055598dda1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6b46d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b46d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b46d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055598dda1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c (3059 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_i64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv8i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_u64m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 3), i64 } @llvm.riscv.vlseg3ff.triscv.vector.tuple_nxv16i8_3t.i64.p0(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 3), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e64ff_v_f64m1x3_tum( %mask, target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563caab8b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563caab880f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563caab8b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff87e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff87e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff87e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff87e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563caab20e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563caab20c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563caab05b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563caa7b50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563caa7b4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff87e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff87e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff87e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563caa7b4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c (3060 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv8i8_4t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.mask.triscv.vector.tuple_nxv16i8_4t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 4) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558af5d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558af5d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558af5d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd219a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd219a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd219a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd219a03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558af569e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005558af569c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005558af54eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558af1fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558af1fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd219a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd219a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd219a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558af1fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c (3061 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei32_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i32.i64( %1, ptr %2, %3, %0, i64 %4, i # | ... # `---data was truncated (10240/25624) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559d8682415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559d868210f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559d8682489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1223f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1223f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1223f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1223f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559d867b9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559d867b9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559d8679eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559d8644e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559d8644ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1223f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1223f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1223f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559d8644dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c (3062 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback # | ... # `---data was truncated (10240/15245) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055aec62ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055aec62aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055aec62ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f817da49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f817daa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f817da49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f817da31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055aec6242e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055aec6242c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055aec6227b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055aec5ed70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055aec5ed6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f817da32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f817da330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f817da330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055aec5ed6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c (3063 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector. # | ... # `---data was truncated (10240/16808) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055968c2f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055968c2f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055968c2f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fde4f649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fde4f6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fde4f649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fde4f631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055968c28ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055968c28ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055968c273b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055968bf230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055968bf22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fde4f632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fde4f6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fde4f6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055968bf22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c (3064 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16mf2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv2f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m1_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv4f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m2_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv8f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m4_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv16f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f16m8_f16m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %vector.addr, align 2 # | %2 = load , ptr %scalar.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv4f16.nxv32f16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32mf2_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %vector.addr, align 4 # | %2 = load , ptr %scalar.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfredmax_vs_f32m1_f32m1_tu( %maskedoff, %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, a # | ... # `---data was truncated (10240/44177) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563d1876c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563d187690f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563d1876c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5ec4d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5ec4d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5ec4d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5ec4d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563d18701e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563d18701c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563d186e6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563d183960b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563d18395dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5ec4d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5ec4d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5ec4d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563d18395cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c (3065 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e9c8e7a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e9c8e770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e9c8e7a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93ef449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93ef4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93ef449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93ef431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e9c8e0fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e9c8e0fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e9c8df4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e9c8aa40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e9c8aa3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93ef432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93ef4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93ef4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e9c8aa3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c (3066 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_i16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf4x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16mf2x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_u16m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e16_v_f16mf4x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005582a8d7e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005582a8d7b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005582a8d7e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f872ff33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f872ff8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f872ff33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f872ff1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005582a8d13e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005582a8d13c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005582a8cf8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005582a89a80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005582a89a7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f872ff1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f872ff1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f872ff1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005582a89a7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/linker-diagnostic.ll (3067 of 27911) ******************** TEST 'Clang :: CodeGen/linker-diagnostic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 2 mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # executed command: mkdir -p /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -module-summary -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/linker-diagnostic.ll.tmp/foo.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/linker-diagnostic.ll # | #0 0x000056343fbc015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056343fbbd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056343fbc089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f03b7133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f03b718a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f03b7133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f03b711b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056343fb55e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056343fb55c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056343fb3ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056343f7ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056343f7e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f03b711cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f03b711d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f03b711d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056343f7e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c (3068 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv8f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv8f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_f32m8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv16f32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv16f32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32mf2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv1i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv1i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m1_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv2i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv2i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vlse.mask.nxv4i32.p0.i64( poison, ptr %1, i64 %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vlse.mask.nxv4i32.p0.i64(, ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlse32_v_i32m4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstrid # | ... # `---data was truncated (10240/17118) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ded09db15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ded09d80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ded09db89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f71b8c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f71b8ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f71b8c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f71b8c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ded0970e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ded0970c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ded0955b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ded06050b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ded0604dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f71b8c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f71b8c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f71b8c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ded0604cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c (3069 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfge.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfge.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfge_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c (3070 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f97743715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f9774340f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f97743789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a3a705b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a3a75c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a3a705a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a3a6ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f9773cce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f9773ccc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f9773b1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f9770610b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f977060dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9a3a6eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a3a6ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a3a6ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f977060cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c (3071 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv1bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv2bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv4bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv8bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m4_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv16bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_bf16m8_tu( %maskedoff, %op1, bfloat noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load , ptr %mask.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfmerge.nxv32bf16.bf16.i64( %0, %1, bfloat %2, %3, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32bf16.bf16.i64(, , bfloat, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+experimental-zvfbfa,+f,+i,+v,+zfbfmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b091b4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b091b440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b091b4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e43133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e4318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e43133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e4311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b091adce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b091adcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b091ac1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b0917710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b091770dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e4311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e4311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e4311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b091770cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c (3072 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 5) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 5) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 5), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555bd7c6115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555bd7c5e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555bd7c6189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9775d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9775d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9775d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9775d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555bd7bf6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555bd7bf6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555bd7bdbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555bd788b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555bd788add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9775d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9775d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9775d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555bd788acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/builtin-cpu-is.c (3073 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/builtin-cpu-is.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-unknown-linux-gnu" # | # | @__riscv_cpu_model = external dso_local global { i32, i64, i64 } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_spacemit_x60() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1808 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372035378380799 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 1152921505839391232 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p550() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775800 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 102892581 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local signext i32 @test_cpu_is_sifive_p870_d() #0 { # | entry: # | %0 = load i32, ptr @__riscv_cpu_model, align 4 # | %1 = icmp eq i32 %0, 1161 # | %2 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8 # | %3 = icmp eq i64 %2, -9223372036854775543 # | %4 = and i1 %1, %3 # | %5 = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8 # | %6 = icmp eq i64 %5, 337970694 # | %7 = and i1 %4, %6 # | %conv = zext i1 %7 to i32 # | ret i32 %conv # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c8d30d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c8d30a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c8d30d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb559d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb559d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb559d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb559d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c8d2a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c8d2a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c8d287b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c8cf370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c8cf36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb559d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb559d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb559d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c8cf36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/builtin-cpu-is.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c (3074 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005558d18a115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005558d189e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005558d18a189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4103333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f410338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4103333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f410331b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005558d1836e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005558d1836c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005558d181bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005558d14cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005558d14cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f410331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f410331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f410331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005558d14cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c (3075 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei32_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556599df615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556599df30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556599df689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbdb5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbdb5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbdb5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbdb5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556599d8be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556599d8bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556599d70b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556599a200b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556599a1fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbdb5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbdb5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbdb5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556599a1fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c (3076 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_f16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_i16m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf4x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e16_v_u16mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_ # | ... # `---data was truncated (10240/26936) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf76f9815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bf76f950f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bf76f9889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95e5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95e5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95e5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95e5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf76f2de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bf76f2dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bf76f12b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bf76bc20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bf76bc1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95e5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95e5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95e5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf76bc1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c (3077 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055569f69f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055569f69c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055569f69f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f348df33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f348df8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f348df33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f348df1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055569f634e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055569f634c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055569f619b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055569f2c90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055569f2c8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f348df1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f348df1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f348df1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055569f2c8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c (3078 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_f16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_i16m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e16_v_u16mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | s # | ... # `---data was truncated (10240/30826) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557bb3de215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557bb3ddf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557bb3de289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9c22649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9c226a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9c22649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9c22631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557bb3d77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557bb3d77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557bb3d5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557bb3a0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557bb3a0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9c22632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9c226330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9c226330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557bb3a0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c (3079 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f0090e715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f0090e40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f0090e789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f56b3e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f56b3ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f56b3e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f56b3e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f00907ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f00907cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f009061b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f008d110b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f008d10dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f56b3e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f56b3e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f56b3e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f008d10cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c (3080 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.sf.vste8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vste8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vste8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555774da915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555774da60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555774da989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8a48533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8a4858a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8a48533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8a4851b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555774d3ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555774d3ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555774d23b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005557749d30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005557749d2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8a4851cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8a4851d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8a4851d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005557749d2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c (3081 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 11007) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -252) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = and <8 x i16> %0, splat (i16 -243) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = and <4 x i32> %0, splat (i32 -8193) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 195) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 65536) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_n_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = or <8 x i16> %0, splat (i16 -4096) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_n_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = or <4 x i32> %0, splat (i32 8978432) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_s16() #0 { # | entry: # | ret <8 x i16> splat (i16 27391) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_s32() #0 { # | entry: # | ret <4 x i32> splat (i32 -5570561) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_n_u16() #0 { # | entry: # | ret <8 x i16> splat (i16 -18689) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_n_u32() #0 { # | entry: # | ret <4 x i32> splat (i32 1023410175) # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -11265) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -13893633) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vbicq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = and <8 x i16> %3, splat (i16 -37) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = and <4 x i32> %3, splat (i32 -1644167169) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_s16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 13568) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_s32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 654311424) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vorrq_m_n_u16(<8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %a.addr, align 8 # | %4 = or <8 x i16> %3, splat (i16 175) # | %5 = select <8 x i1> %2, <8 x i16> %4, <8 x i16> %3 # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_n_u32(<4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %a.addr, align 8 # | %4 = or <4 x i32> %3, splat (i32 89) # | %5 = select <4 x i1> %2, <4 x i32> %4, <4 x i32> %3 # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_s16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> %2, <8 x i16> splat (i16 -3841), <8 x i16> %3 # | ret <8 x i16> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmvnq_m_n_s32(<4 x i32> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) # | %3 = load <4 x i32>, ptr %inactive.addr, align 8 # | %4 = select <4 x i1> %2, <4 x i32> splat (i32 -18945), <4 x i32> %3 # | ret <4 x i32> %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmvnq_m_n_u16(<8 x i16> noundef %inactive, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load i16, ptr %p.addr, align 2 # | %1 = zext i16 %0 to i32 # | %2 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %1) # | %3 = load <8 x i16>, ptr %inactive.addr, align 8 # | %4 = select <8 x i1> % # | ... # `---data was truncated (10240/13125) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3fd3cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3fd3c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3fd3cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff17533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff1758a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff17533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff1751b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3fd360e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3fd360c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3fd345b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3fcff50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3fcff4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff1751cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff1751d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff1751d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3fcff4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c (3082 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks1i(i64 noundef %rs1) #0 { # | entry: # | %rs1.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = call i64 @llvm.riscv.aes64ks1i(i64 %0, i32 0) # | ret i64 %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks1i(i64, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @aes64ks2(i64 noundef %rs1, i64 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i64, align 8 # | %__y.addr.i = alloca i64, align 8 # | %rs1.addr = alloca i64, align 8 # | %rs2.addr = alloca i64, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | %0 = load i64, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | store i64 %0, ptr %__x.addr.i, align 8 # | store i64 %1, ptr %__y.addr.i, align 8 # | %2 = load i64, ptr %__x.addr.i, align 8 # | %3 = load i64, ptr %__y.addr.i, align 8 # | %4 = call i64 @llvm.riscv.aes64ks2(i64 %2, i64 %3) # | ret i64 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i64 @llvm.riscv.aes64ks2(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b1b03a015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b1b039d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b1b03a089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7b1d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7b1d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7b1d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7b1d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b1b0335e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b1b0335c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b1b031ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b1affca0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b1affc9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7b1d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7b1d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7b1d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b1affc9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c -check-prefix=RV64ZKND-ZKNE # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c (3083 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ... # `---data was truncated (10240/12732) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055582d18415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055582d1810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055582d18489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3158049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f31580a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3158049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3158031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055582d119e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055582d119c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055582d0feb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055582cdae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055582cdaddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3158032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f31580330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f31580330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055582cdadcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c (3084 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564da8c8415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564da8c810f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564da8c8489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcd26649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcd266a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcd26649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcd26631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564da8c19e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564da8c19c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564da8bfeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564da88ae0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564da88addd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcd26632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcd266330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcd266330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564da88adcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c (3085 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_f64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64ff_v_i64m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 # | ... # `---data was truncated (10240/15508) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563aa8d3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563aa8d330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563aa8d3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc003a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc003a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc003a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc003a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563aa8ccbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563aa8ccbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563aa8cb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563aa89600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563aa895fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc003a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc003a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc003a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563aa895fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c (3086 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005613d817e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005613d817b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005613d817e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc303e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc303ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc303e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc303e31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005613d8113e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005613d8113c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005613d80f8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005613d7da80b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005613d7da7dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc303e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc303e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc303e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005613d7da7cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c (3087 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvfbfmin -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e4m3mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e4m3mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e4m3mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e4m3m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e4m3m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e4m3m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e4m3m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e4m3m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf8_f8e5m2mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf4_f8e5m2mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8mf2_f8e5m2mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m1_f8e5m2m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m2_f8e5m2m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m4_f8e5m2m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_u8m8_f8e5m2m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf8_u8mf8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf4_u8mf4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2mf2_u8mf2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m1_u8m1( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m2_u8m2( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m4_u8m4( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align 1 # | %0 = load , ptr %src.addr, align 1 # | ret %0 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vreinterpret_v_f8e5m2m8_u8m8( %src) #0 { # | entry: # | %src.addr = alloca , align 1 # | store %src, ptr %src.addr, align # | ... # `---data was truncated (10240/10944) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f78ca5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f78ca550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f78ca5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3759533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f375958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3759533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f375951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f78c9ede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f78c9edc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f78c9d2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f78c6820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f78c681dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f375951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f375951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f375951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f78c681cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll (3088 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 7 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi-devirt.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi-devirt.ll # | #0 0x000055e77cddf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e77cddc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e77cddf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f79db933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f79db98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f79db933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f79db91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e77cd74e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e77cd74c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e77cd59b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e77ca090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e77ca08dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f79db91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f79db91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f79db91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e77ca08cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c (3089 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_f32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_i32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32mf2x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e32_v_u32m1x8_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055eb5faee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055eb5faeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055eb5faee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe696249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6962a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe696249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe696231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055eb5fa83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055eb5fa83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055eb5fa68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055eb5f7180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055eb5f717dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe696232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6962330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6962330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055eb5f717cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c (3090 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) # | ... # `---data was truncated (10240/25094) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e2be16b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e2be1680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e2be16b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dc5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dc558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dc5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dc551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e2be100e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e2be100c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e2be0e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e2bdd950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e2bdd94dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dc551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dc551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dc551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e2bdd94cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c (3091 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_u8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e8_v_i8mf8x7_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c (3092 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei32_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562b6f89415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562b6f8910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562b6f89489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a8c333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a8c38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a8c333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a8c31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562b6f829e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562b6f829c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562b6f80eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562b6f4be0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562b6f4bddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9a8c31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a8c31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a8c31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562b6f4bdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c (3093 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei8_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c (3094 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_i64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m1x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m2x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_u64m4x2(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e64_v_f64m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llv # | ... # `---data was truncated (10240/20513) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005635318cb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005635318c80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005635318cb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff01a649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff01a6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff01a649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff01a631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563531860e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563531860c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563531845b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005635314f50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005635314f4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff01a632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff01a6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff01a6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005635314f4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c (3095 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr % # | ... # `---data was truncated (10240/20631) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559e108c015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559e108bd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559e108c089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1799133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f179918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1799133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f179911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559e10855e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559e10855c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559e1083ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559e104ea0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559e104e9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f179911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f179911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f179911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559e104e9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c (3096 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmacc_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c (3097 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vmull.v8i16.v16i8(<16 x i8>, <16 x i8>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1, i32 0) # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.vmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <2 x i64>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <2 x i64> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32 %3) # | %5 = load <2 x i64>, ptr %inactive.addr, align 8 # | %6 = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32> %0, <4 x i32> %1, i32 0, i32 0, <2 x i1> %4, <2 x i64> %5) # | ret <2 x i64> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i1> @llvm.arm.mve.pred.i2v.v2i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v2i1(<4 x i32>, <4 x i32>, i32, i32, <2 x i1>, <2 x i64>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 0, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %0, <16 x i8> %1, i32 1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %0, <8 x i16> %1, i32 0, i32 0, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | # | ... # `---data was truncated (10240/12050) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3b198215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3b197f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3b198289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f891b849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f891b8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f891b849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f891b831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3b1917e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3b1917c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3b18fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3b15ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3b15abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f891b832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f891b8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f891b8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3b15abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vclz.c (3098 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vclz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_u8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %0, i1 false) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_u16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %0, i1 false) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_u32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %0, i1 false) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> noundef %a) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %0) # | ret <16 x i8> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> noundef %a) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %0) # | ret <8 x i16> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> noundef %a) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %0) # | ret <4 x i32> %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclsq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclsq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.cls.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclsq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vclzq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %2) # | %4 = load <16 x i8>, ptr %inactive.addr, align 8 # | %5 = call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i1> %3, <16 x i8> %4) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vclzq_m_s16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2) # | %4 = load <8 x i16>, ptr %inactive.addr, align 8 # | %5 = call <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i1> %3, <8 x i16> %4) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.clz.predicated.v8i16.v8i1(<8 x i16>, <8 x i1>, <8 x i16>) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vclzq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i16, ptr %p.addr, align 2 # | %2 = zext i16 %1 to i32 # | %3 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) # | %4 = load <4 x i32>, ptr %inactive.addr, align 8 # | %5 = call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i1> %3, <4 x i32> %4) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x # | ... # `---data was truncated (10240/18674) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3d96b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3d96ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3d96b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f583af33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f583af8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f583af33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f583af1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3d9646e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3d9646c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3d962bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3d92db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3d92dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f583af1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f583af1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f583af1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3d92dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vclz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c (3099 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_i8m2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf8x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf4x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8mf2x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg4e8_v_u8m1x4(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558d4403615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558d440330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558d4403689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f273b905b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f273b95c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f273b905a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f273b8ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558d43fcbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558d43fcbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558d43fb0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558d43c600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558d43c5fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f273b8eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f273b8ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f273b8ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558d43c5fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c (3100 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store %vs3, ptr %vs # | ... # `---data was truncated (10240/15504) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055872af5915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055872af560f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055872af5989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa26d733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa26d78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa26d733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa26d71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055872aeeee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055872aeeec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055872aed3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055872ab830b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055872ab82dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa26d71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa26d71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa26d71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055872ab82cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c (3101 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055919e94a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055919e9470f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055919e94a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0518f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0518f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0518f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0518f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055919e8dfe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055919e8dfc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055919e8c4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055919e5740b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055919e573dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0518f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0518f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0518f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055919e573cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c (3102 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m4( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m8( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4aus.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32mf2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m1_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4aus_vx_i32m2_m( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4aus.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: # | ... # `---data was truncated (10240/13649) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005577a97e315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005577a97e00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005577a97e389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3803505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f380355c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3803505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f38034ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005577a9778e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005577a9778c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005577a975db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005577a940d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005577a940cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f38034eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f38034ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f38034ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005577a940ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c (3103 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m2x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m4x2(ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) %3, ptr %1, i64 %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vssseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store target("risc # | ... # `---data was truncated (10240/14659) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564d5dd4b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564d5dd480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564d5dd4b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc33bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc33bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc33bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc33bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564d5dce0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564d5dce0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564d5dcc5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564d5d9750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564d5d974dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc33bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc33bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc33bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564d5d974cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c (3104 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedo # | ... # `---data was truncated (10240/30751) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005602e3ffa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005602e3ff70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005602e3ffa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa28f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa28f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa28f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa28f231507 abort ./stdlib/abort.c:85:3 # | #7 0x00005602e3f8fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005602e3f8fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005602e3f74b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005602e3c240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005602e3c23dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa28f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa28f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa28f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005602e3c23cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c (3105 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +xandesvdot -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_nds_vd4dotsu_vv_i64m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vd4 # | ... # `---data was truncated (10240/25575) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d85e97515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d85e9720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d85e97589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f214d933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f214d98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f214d933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f214d91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d85e90ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d85e90ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d85e8efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d85e59f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d85e59edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f214d91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f214d91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f214d91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d85e59ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c (3106 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/26748) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dea0e7115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dea0e6e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dea0e7189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6525533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f652558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6525533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f652551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dea0e06e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dea0e06c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dea0debb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dea0a9b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dea0a9add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f652551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f652551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f652551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dea0a9acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c (3107 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), pt # | ... # `---data was truncated (10240/19484) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f5c70f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f5c70c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f5c70f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f95e7333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f95e738a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f95e7333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f95e731b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f5c6a4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f5c6a4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f5c689b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f5c3390b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f5c338dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f95e731cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f95e731d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f95e731d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f5c338cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c (3108 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6(ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005648a308c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005648a30890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005648a308c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fab02e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fab02e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fab02e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fab02e03507 abort ./stdlib/abort.c:85:3 # | #7 0x00005648a3021e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005648a3021c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005648a3006b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005648a2cb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005648a2cb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fab02e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fab02e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fab02e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005648a2cb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c (3109 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m1_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m2_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m4_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv16bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16m8_tu( %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %src.addr, align 2 # | %2 = load bfloat, ptr %value.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.nxv32bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf4_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %src.addr, align 2 # | %3 = load bfloat, ptr %value.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfslide1up.mask.nxv1bf16.bf16.i64(, , bfloat, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfslide1up_vf_bf16mf2_tum( %mask, %maskedoff, %src, bfloat noundef %value, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca , align 2 # | %value.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %src, ptr %src.addr, align 2 # | store bfloat %value, ptr %value.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, alig # | ... # `---data was truncated (10240/32578) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e52a7f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e52a7c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e52a7f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fda7d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fda7d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fda7d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fda7d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e52a14e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e52a14c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e529f9b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e526a90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e526a8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fda7d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fda7d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fda7d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e526a8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c (3110 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv16bf16.p0.nxv16i32.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei32_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i32.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fun # | ... # `---data was truncated (10240/12067) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005624cb60d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005624cb60a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005624cb60d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb9ea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb9ea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb9ea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb9ea431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005624cb5a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005624cb5a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005624cb587b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005624cb2370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005624cb236dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb9ea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb9ea4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb9ea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005624cb236cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c (3111 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 # | ... # `---data was truncated (10240/32709) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055700adbc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055700adb90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055700adbc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1db1733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1db178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1db1733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1db171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055700ad51e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055700ad51c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055700ad36b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055700a9e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055700a9e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1db171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1db171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1db171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055700a9e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c (3112 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f16m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32mf2x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f32m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_f64m1x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf8x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv1i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_i8mf4x5(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv2i32.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596cdeb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596cdeaf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596cdeb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f012a505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f012a55c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f012a505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f012a4ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596cde47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596cde47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596cde2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596cdadc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596cdadbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f012a4eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f012a4ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f012a4ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596cdadbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c (3113 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xandesvbfhcvt -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_nds_vfwcvt_s_bf16_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xandesvbfhcvt,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xandesvbfhcvt5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005643fd01c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005643fd0190f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005643fd01c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f66a2b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f66a2b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f66a2b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f66a2b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005643fcfb1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005643fcfb1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005643fcf96b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005643fcc460b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005643fcc45dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f66a2b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f66a2b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f66a2b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005643fcc45cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c (3114 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_f16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_i16m1x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf4x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv2i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlsseg5e16_v_u16mf2x5_tu(target("riscv.vector.tuple", , 5) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 5), # | ... # `---data was truncated (10240/53330) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5d15ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5d15ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5d15ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2bc5449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2bc54a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2bc5449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2bc5431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5d1582e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5d1582c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5d1567b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5d12170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5d1216dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2bc5432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2bc54330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2bc54330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5d1216cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c (3115 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei8_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 8), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056088c35515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056088c3520f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056088c35589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9508733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f950878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9508733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f950871b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056088c2eae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056088c2eac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056088c2cfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056088bf7f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056088bf7edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f950871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f950871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f950871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056088bf7ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c (3116 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf4_f32mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf4_f32mf2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv1f32.bf16.nxv1bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16mf2_f32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16mf2_f32m1( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv2f32.bf16.nxv2bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m1_f32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m1_f32m2( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv4f32.bf16.nxv4bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vv_bf16m2_f32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwmsac.nxv8f32.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwmsac_vf_bf16m2_f32m4( %vd, bfloat noundef %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store bfloat %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load bfloat, ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwmsac.nxv8f32.bf16.nxv # | ... # `---data was truncated (10240/51702) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d3f34ed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d3f34ea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d3f34ed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb656649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6566a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb656649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb656631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d3f3482e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d3f3482c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d3f3467b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d3f31170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d3f3116dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb656632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6566330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6566330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d3f3116cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c (3117 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfh -target-feature +xsfvfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8f16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_f16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv16f16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c (3118 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i32.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i32.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i32.nxv4i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i32.nxv8i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv16i32.nxv16i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv1i64.nxv1i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv2i64.nxv2i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv4i64.nxv4i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u64m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.nxv8i64.nxv8i16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf4_u32mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 4 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call # | ... # `---data was truncated (10240/39914) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dcdce0c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dcdce090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dcdce0c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe40cb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe40cb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe40cb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe40cb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dcdcda1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dcdcda1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dcdcd86b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dcdca360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dcdca35dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe40cb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe40cb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe40cb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dcdca35cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c (3119 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf8_b64( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf8_b64( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv1i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf8_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf8_b64( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv1i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv1i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf4_b32( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf4_b32( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64( %0, i8 %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv2i8.i8.i64(, i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vv_i8mf4_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vx_i8mf4_b32( %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i8, ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmadc.nxv2i8.i8.i64( %0, i8 %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.nxv2i8.i8.i64(, i8, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vvm_i8mf2_b16( %op1, %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %carryin.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store %carryin, ptr %carryin.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load , ptr %carryin.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmadc_vxm_i8mf2_b16( %op1, i8 noundef signext %op2, %carryin, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, al # | ... # `---data was truncated (10240/169925) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ece77ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ece77aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ece77ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9a63133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9a6318a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9a63133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9a6311b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ece7742e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ece7742c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ece7727b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ece73d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ece73d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9a6311cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9a6311d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9a6311d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ece73d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c (3120 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16mf2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m1( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv4f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv4f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m2( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv8f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv8f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m4( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv16f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv16f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f16m8( %op1, half noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca half, align 2 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store half %op2, ptr %op2.addr, align 2 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load half, ptr %op2.addr, align 2 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv32f16.f16.i64( poison, %0, half %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv32f16.f16.i64(, , half, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32mf2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv1f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv1f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m1( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store float %op2, ptr %op2.addr, align 4 # | store %mask, ptr %mask.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load float, ptr %op2.addr, align 4 # | %2 = load , ptr %mask.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmerge.nxv2f32.f32.i64( poison, %0, float %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmerge.nxv2f32.f32.i64(, , float, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmerge_vfm_f32m2( %op1, float noundef %op2, %mask, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %op2.addr = alloca float, align 4 # | %mask.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c (3121 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv1bf16.p0.nxv1i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv2bf16.p0.nxv2i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv4bf16.p0.nxv4i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vluxei64_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vluxei.mask.nxv8bf16.p0.nxv8i64.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557c40ea415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557c40ea10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557c40ea489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2615249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f26152a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2615249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2615231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557c40e39e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557c40e39c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557c40e1eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557c40ace0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557c40acddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2615232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f26152330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f26152330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557c40acdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c (3122 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561b9216415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561b921610f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561b9216489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd115a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd115aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd115a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd115a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561b920f9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561b920f9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561b920deb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561b91d8e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561b91d8ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd115a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd115a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd115a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561b91d8dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c (3123 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_f16m4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf4x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16mf2x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_i16m1x2_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | # | ... # `---data was truncated (10240/19083) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4afbb315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4afbb00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4afbb389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7747449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77474a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7747449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7747431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f4afb48e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f4afb48c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f4afb2db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f4af7dd0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f4af7dcdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7747432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77474330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77474330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f4af7dccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c (3124 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv64i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv64i8.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8i8.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m2_tu( %maskedoff, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = l # | ... # `---data was truncated (10240/54480) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005585e8a8915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005585e8a860f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005585e8a8989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7579533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f757958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7579533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f757951b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005585e8a1ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005585e8a1ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005585e8a03b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005585e86b30b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005585e86b2dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f757951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f757951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f757951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005585e86b2cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c (3125 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_f16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16mf2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m1x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m2x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg2e16_v_i16m4x2(ptr noundef %base, target("riscv.vector.tuple", , 2) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 2) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 2), ptr %v_tuple.addr, align 2 # | %2 = load i64, p # | ... # `---data was truncated (10240/33435) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e83990c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e8399090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e83990c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe433305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe43335c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe433305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe4332ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e8398a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e8398a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e839886b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e8395360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e839535dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe4332eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe4332ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe4332ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e839535cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c (3126 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei64_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556afbdb415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556afbdb10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556afbdb489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f37dd933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f37dd98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f37dd933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f37dd91b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556afbd49e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556afbd49c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556afbd2eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556afb9de0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556afb9dddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f37dd91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f37dd91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f37dd91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556afb9ddcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c (3127 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf8x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf4x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8mf2x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_u8m1x7(ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, pt # | ... # `---data was truncated (10240/18980) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055670e2dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055670e2d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055670e2dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f1c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f1c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f1c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f1c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055670e271e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055670e271c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055670e256b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055670df060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055670df05dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f1c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f1c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f1c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055670df05cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c (3128 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv1i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/48305) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005556bb16215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005556bb15f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005556bb16289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4c61333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4c6138a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4c61333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4c6131b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005556bb0f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005556bb0f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005556bb0dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005556bad8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005556bad8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4c6131cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4c6131d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4c6131d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005556bad8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c (3129 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c (3130 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf8x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf4x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8mf2x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_u8m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e8_v_i8mf8x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, al # | ... # `---data was truncated (10240/21566) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b8ba01f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b8ba01c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b8ba01f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa9db849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa9db8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa9db849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa9db831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b8b9fb4e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b8b9fb4c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b8b9f99b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b8b9c490b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b8b9c48dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa9db832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa9db8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa9db8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b8b9c48cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c (3131 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 %3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_tum( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_tumu( %mask, target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %bstride.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target(" # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056156114015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056156113d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056156114089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2ec6133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2ec618a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2ec6133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2ec611b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615610d5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615610d5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615610bab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561560d6a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561560d69dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2ec611cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2ec611d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2ec611d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561560d69cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c (3132 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i64.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i64.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i64.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i64.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i64.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i64.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv1i64.nxv1i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv2i64.nxv2i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv4i64.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf8_u64m8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.mask.nxv8i64.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f8c13b515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f8c13b20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f8c13b589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4e96849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4e968a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4e96849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4e96831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f8c134ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f8c134ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f8c132fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f8c0fdf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f8c0fdedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4e96832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4e968330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4e968330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f8c0fdecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c (3133 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_f64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_i64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e64ff_v_u64m1x7_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.mask.triscv.vector.tuple_nxv8i8_7t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %3, i64 3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056475666615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005647566630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056475666689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc91fb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc91fb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc91fb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc91fb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005647565fbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005647565fbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005647565e0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005647562900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056475628fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc91fb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc91fb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc91fb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056475628fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c (3134 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnj.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnj_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load # | ... # `---data was truncated (10240/29128) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c4c61315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c4c6100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c4c61389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9fe1249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9fe12a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9fe1249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9fe1231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c4c5a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c4c5a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c4c58db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c4c23d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c4c23cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9fe1232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9fe12330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9fe12330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c4c23ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c (3135 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m1x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m2x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16m4x2(ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 4) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf4x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_bf16mf2x2_m( %vm, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c (3136 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb3f7d015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb3f7cd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb3f7d089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf8ee49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf8eea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf8ee49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf8ee31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb3f765e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb3f765c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb3f74ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb3f3fa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb3f3f9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf8ee32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf8ee330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf8ee330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb3f3f9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c (3137 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | decl # | ... # `---data was truncated (10240/20497) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055855aa4115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055855aa3e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055855aa4189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f97ac249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97ac2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f97ac249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f97ac231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055855a9d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055855a9d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055855a9bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055855a66b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055855a66add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f97ac232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97ac2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97ac2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055855a66acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c (3138 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf4_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16mf2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16mf2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m1_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vv_bf16m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmadd.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmadd_vf_bf16m2_tu( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmadd.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7 # | ... # `---data was truncated (10240/64374) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056336d76d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056336d76a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056336d76d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f424e41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f424e4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f424e41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f424e403507 abort ./stdlib/abort.c:85:3 # | #7 0x000056336d702e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056336d702c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056336d6e7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056336d3970b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056336d396dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f424e404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f424e4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f424e4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056336d396cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c (3139 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_f16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_i16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf4x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e16_v_u16m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c (3140 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounw # | ... # `---data was truncated (10240/15952) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555f477ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555f477ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555f477ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b12133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b1218a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b12133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b1211b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555f47784e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555f47784c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555f47769b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555f474190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555f47418dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b1211cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b1211d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b1211d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555f47418cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c (3141 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( poison, ptr %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64( poison, ptr %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c (3142 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvfnrclipxfqf -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m1_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8m2_tu( %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 1 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load float, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64( %0, %1, float %2, i64 7, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.i64(, , float, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf8_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf4_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load float, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64( %1, %2, float %3, %0, i64 7, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.i64(, , float, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vfnrclip_xu_f_qf_u8mf2_tum( %mask, %maskedoff, %vs2, float noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca float, align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %vs2, ptr %vs2.addr, align 4 # | store float %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, al # | ... # `---data was truncated (10240/26756) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580336ad15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580336aa0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580336ad89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0eae49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0eaea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0eae49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0eae31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558033642e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558033642c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558033627b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580332d70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580332d6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd0eae32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0eae330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0eae330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580332d6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c (3143 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 4 # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 4 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 4 # | %1 = load , ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m1_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m2_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m4_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f64m8_tu( %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 8 # | %src.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 8 # | store %src, ptr %src.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 8 # | %1 = load , ptr %src.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwcvt_f_f_v_f32mf2_tum( %mask, %maskedoff, %src, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 4 # | %src.addr = al # | ... # `---data was truncated (10240/41670) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559b6c79115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559b6c78e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559b6c79189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f30e0b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f30e0b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f30e0b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f30e0b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559b6c726e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559b6c726c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559b6c70bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559b6c3bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559b6c3badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f30e0b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f30e0b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f30e0b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559b6c3bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c (3144 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580e9b8015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580e9b7d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580e9b8089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc28c933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc28c98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc28c933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc28c91b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580e9b15e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580e9b15c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580e9afab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580e97aa0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580e97a9dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc28c91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc28c91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc28c91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580e97a9cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c (3145 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32m1x7(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 7) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_f32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_i32m1x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e32_v_u32mf2x7_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e36d00615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e36d0030f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e36d00689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f98a9d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f98a9d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f98a9d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f98a9d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e36cf9be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e36cf9bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e36cf80b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e36cc300b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e36cc2fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f98a9d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f98a9d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f98a9d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e36cc2fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c (3146 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv8i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv16i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv16i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv32i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv32i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_i8m8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv64i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv64i8.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf4_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8mf2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv4i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle8_v_u8m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv8i8.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c (3147 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64f -target-feature +zvfh -target-feature +xsfvfexpa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv16f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f16m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv32f16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv1f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv1f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv2f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv2f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv4f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv4f32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexpa_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexpa.nxv8f32.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexpa.nxv8f32.i64(, # | ... # `---data was truncated (10240/47764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b9eb68c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b9eb6890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b9eb68c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2925c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2925ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2925c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2925c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b9eb621e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b9eb621c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b9eb606b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b9eb2b60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b9eb2b5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2925c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2925c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2925c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b9eb2b5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c (3148 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmsac.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmsac_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfmsac.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c (3149 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f708e0515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f708e020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f708e0589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6321249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f63212a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6321249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6321231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f708d9ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f708d9ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f708d7fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f708a2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f708a2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6321232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f63212330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f63212330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f708a2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c (3150 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %0, i64 %3, i64 2, i64 6) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64_v_f64m2x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %2 = load ptr, ptr %base.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, # | ... # `---data was truncated (10240/32133) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ef025f115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ef025ee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ef025f189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc10a733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc10a78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc10a733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc10a71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ef02586e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ef02586c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ef0256bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ef0221b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ef0221add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc10a71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc10a71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc10a71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ef0221acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c (3151 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei32_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dae4a6715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dae4a640f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dae4a6789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93ffe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93ffea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93ffe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93ffe31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dae49fce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dae49fcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dae49e1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dae46910b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dae4690dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93ffe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93ffe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93ffe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dae4690cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c (3152 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf4_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.nxv1bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf4_b64_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv1bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16mf2_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.nxv2bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16mf2_b32_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv2bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m1_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.nxv4bf16.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vf_bf16m1_b16_mu( %mask, %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load bfloat, ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64( %1, %2, bfloat %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfle.mask.nxv4bf16.bf16.i64(, , bfloat, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfle_vv_bf16m2_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load , ptr %op2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmfle.mask.nx # | ... # `---data was truncated (10240/18660) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f20c97515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f20c9720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f20c97589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6663d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6663d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6663d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6663d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f20c90ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f20c90ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f20c8efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f20c59f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f20c59edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6663d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6663d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6663d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f20c59ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c (3153 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_i32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32mf2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m1x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_u32m2x4(ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 4) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 4 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 4) %v_tuple, ptr %v_tuple.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %v_tuple.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 5) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void # | ... # `---data was truncated (10240/20489) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562e715e115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562e715de0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562e715e189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f1a249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f1a2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f1a249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f1a231507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562e71576e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562e71576c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562e7155bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562e7120b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562e7120add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f1a232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f1a2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f1a2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562e7120acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/packed-structure.c (3154 of 27911) ******************** TEST 'Clang :: CodeGen/packed-structure.c' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/packed-structure.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64" # | # | %struct.s0 = type { i32, i32 } # | %struct.s1 = type { i32, i32 } # | %struct.s2 = type { i32, i32 } # | %struct.s3 = type <{ i16, i32, [10 x i8] }> # | # | @s0_align_x = global i32 4, align 4 # | @s0_align_y = global i32 1, align 4 # | @s0_align = global i32 4, align 4 # | @s1_align_x = global i32 1, align 4 # | @s1_align_y = global i32 1, align 4 # | @s1_align = global i32 1, align 4 # | @s2_align_x = global i32 2, align 4 # | @s2_align_y = global i32 2, align 4 # | @s2_align = global i32 2, align 4 # | @s3_1 = global i32 1, align 4 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s0_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s0, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 4 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s0_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) # | declare void @llvm.memcpy.p0.p0.i64(ptr noalias writeonly captures(none), ptr noalias readonly captures(none), i64, i1 immarg) #1 # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s1_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s1, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 1 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s1_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_x(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %x = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 0 # | %1 = load i32, ptr %x, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @s2_load_y(ptr noundef %a) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | %0 = load ptr, ptr %a.addr, align 8 # | %y = getelementptr inbounds nuw %struct.s2, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %y, align 2 # | ret i32 %1 # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local void @s2_copy(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 8 # | %b.addr = alloca ptr, align 8 # | store ptr %a, ptr %a.addr, align 8 # | store ptr %b, ptr %b.addr, align 8 # | %0 = load ptr, ptr %b.addr, align 8 # | %1 = load ptr, ptr %a.addr, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 2 %0, ptr align 2 %1, i64 8, i1 false) # | ret void # | } # | # | ; Function Attrs: noinline nounwind optnone # | define dso_local i32 @test3(ptr noundef %ptr) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | store ptr %ptr, ptr %ptr.addr, align 8 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %anInt = getelementptr inbounds nuw %struct.s3, ptr %0, i32 0, i32 1 # | %1 = load i32, ptr %anInt, align 2 # | ret i32 %1 # | } # | # | attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=strip -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/Output/packed-structure.c.tmp # | #0 0x0000557fdce7b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557fdce780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557fdce7b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0f8b105b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0f8b15c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0f8b105a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0f8b0ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557fdce10e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557fdce10c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557fdcdf5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557fdcaa50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557fdcaa4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0f8b0eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0f8b0ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0f8b0ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557fdcaa4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c (3155 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv64i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv64i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv32i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv32i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv16i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv16i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv8i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv8i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv4i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv4i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv2i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv2i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b64( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call i64 @llvm.riscv.vfirst.nxv1i1.i64( %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.nxv1i1.i64(, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b1_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b2_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b4_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b8_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b16_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64( %1, %0, i64 %2) # | ret i64 %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local i64 @test_vfirst_m_b32_m( %mask, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64( %1, %0, i64 %2) # | ret i6 # | ... # `---data was truncated (10240/11946) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005596c2e6615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005596c2e630f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005596c2e6689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff63f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff63f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff63f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff63f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005596c2dfbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005596c2dfbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005596c2de0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005596c2a900b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005596c2a8fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff63f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff63f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff63f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005596c2a8fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c (3156 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv16bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv16bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_v_f_bf16m8_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.v.f.nxv32bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.v.f.nxv32bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv1bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv1bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16mf2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv2bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv2bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m1_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv4bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv4bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m2_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %src.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store bfloat %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load bfloat, ptr %src.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfmv.s.f.nxv8bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfmv.s.f.nxv8bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfmv_s_f_bf16m4_tu( %maskedoff, bfloat noundef %src, i64 noundef %vl) #0 { # | entry: # | %maskedoff. # | ... # `---data was truncated (10240/12648) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b0447d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b0447d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b0447d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb99de1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb99de725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb99de1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb99de03507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b04476ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b04476ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b044753b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b0444030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b044402dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb99de04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb99de050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb99de050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b044402cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c (3157 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564b9cdff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564b9cdfc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564b9cdff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff646e1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff646e725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff646e1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff646e03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564b9cd94e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564b9cd94c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564b9cd79b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564b9ca290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564b9ca28dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff646e04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff646e050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff646e050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564b9ca28cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c (3158 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e62d3df15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e62d3dc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e62d3df89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f45d9533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f45d958a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f45d9533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f45d951b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e62d374e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e62d374c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e62d359b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e62d0090b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e62d008dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f45d951cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f45d951d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f45d951d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e62d008cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c (3159 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv4bf16.p0.nxv4i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m2(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv8bf16.p0.nxv8i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m4(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv16bf16.p0.nxv16i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m8(ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load , ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64( %2, ptr %0, %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.nxv32bf16.p0.nxv32i16.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf4_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv1bf16.p0.nxv1i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16mf2_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load , ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64( %3, ptr %1, %2, %0, i64 %4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxei.mask.nxv2bf16.p0.nxv2i16.i64(, ptr captures(none), , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxei16_v_bf16m1_m( %vm, ptr noundef %rs1, %rs2, %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vs3.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c (3160 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f16m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32mf2x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f32m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_f64m1x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf8x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv1i8_8t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei64_v_i8mf4x8(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv2i64. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bf489c115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bf489be0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bf489c189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5466d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5466d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5466d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5466d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bf48956e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bf48956c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bf4893bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bf485eb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bf485eadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5466d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5466d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5466d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bf485eacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c (3161 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vloxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055837bd6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055837bd5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055837bd6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf1b049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf1b0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf1b049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf1b031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055837bcf7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055837bcf7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055837bcdcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055837b98c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055837b98bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf1b032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf1b0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf1b0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055837b98bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-neon-vcvtX.c (3162 of 27911) ******************** TEST 'Clang :: CodeGen/arm-neon-vcvtX.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8-unknown-linux-gnueabihf" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %vcvta_s32_v.i) # | store <2 x i32> %vcvta_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvta_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvta_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvta_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %vcvta_u32_v.i) # | store <2 x i32> %vcvta_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %vcvtaq_s32_v.i) # | store <4 x i32> %vcvtaq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtaq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtaq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtaq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %vcvtaq_u32_v.i) # | store <4 x i32> %vcvtaq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %vcvtn_s32_v.i) # | store <2 x i32> %vcvtn_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtn_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtn_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtn_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %vcvtn_u32_v.i) # | store <2 x i32> %vcvtn_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %vcvtnq_s32_v.i) # | store <4 x i32> %vcvtnq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtnq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtnq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtnq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %vcvtnq_u32_v.i) # | store <4 x i32> %vcvtnq_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_s32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_s32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_s32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %vcvtp_s32_v.i) # | store <2 x i32> %vcvtp_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i32> @test_vcvtp_u32_f32(<2 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <2 x float>, align 8 # | %__ret.i = alloca <2 x i32>, align 8 # | %ref.tmp.i = alloca <8 x i8>, align 8 # | %a.addr = alloca <2 x float>, align 8 # | store <2 x float> %a, ptr %a.addr, align 8 # | %0 = load <2 x float>, ptr %a.addr, align 8 # | store <2 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <8 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtp_u32_v.i = bitcast <8 x i8> %1 to <2 x float> # | %vcvtp_u32_v1.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %vcvtp_u32_v.i) # | store <2 x i32> %vcvtp_u32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <2 x i32>, ptr %ref.tmp.i, align 8 # | store <2 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <2 x i32>, ptr %__ret.i, align 8 # | ret <2 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_s32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_s32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_s32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %vcvtpq_s32_v.i) # | store <4 x i32> %vcvtpq_s32_v1.i, ptr %ref.tmp.i, align 8 # | %2 = load <4 x i32>, ptr %ref.tmp.i, align 8 # | store <4 x i32> %2, ptr %__ret.i, align 8 # | %3 = load <4 x i32>, ptr %__ret.i, align 8 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <4 x i32> @test_vcvtpq_u32_f32(<4 x float> noundef %a) #0 { # | entry: # | %__p0.addr.i = alloca <4 x float>, align 8 # | %__ret.i = alloca <4 x i32>, align 8 # | %ref.tmp.i = alloca <16 x i8>, align 8 # | %a.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | store <4 x float> %0, ptr %__p0.addr.i, align 8 # | %1 = load <16 x i8>, ptr %__p0.addr.i, align 8 # | %vcvtpq_u32_v.i = bitcast <16 x i8> %1 to <4 x float> # | %vcvtpq_u32_v1.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %vcvtpq_u32_v.i) # | st # | ... # `---data was truncated (10240/16770) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg,sroa # | #0 0x0000555a9987d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555a9987a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555a9987d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4770505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f477055c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4770505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f47704ed507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555a99812e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555a99812c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555a997f7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555a994a70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555a994a6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f47704eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f47704ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f47704ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555a994a6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-neon-vcvtX.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c (3163 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei32_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fa29fb215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fa29faf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fa29fb289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3b29133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3b2918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3b29133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3b2911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fa29f47e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fa29f47c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fa29f2cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fa29bdc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fa29bdbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3b2911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3b2911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3b2911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fa29bdbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c (3164 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64( %1, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfwcvtbf16_f_f_v_f32m4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, # | ... # `---data was truncated (10240/23056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b936f5b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b936f580f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b936f5b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007eff21849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007eff218a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007eff21849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007eff21831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b936ef0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b936ef0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b936ed5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b936b850b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b936b84dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007eff21832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007eff218330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007eff218330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b936b84cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c (3165 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e16_v_bf16m1x5_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575da5a515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575da5a20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575da5a589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9aaba49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9aabaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9aaba49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9aaba31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575da53ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575da53ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575da51fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575da1cf0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575da1cedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9aaba32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9aaba330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9aaba330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575da1cecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c (3166 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 2 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb8d66915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb8d6660f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb8d66989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6f401bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6f40725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6f401ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6f4003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb8d5fee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb8d5fec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb8d5e3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb8d2930b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb8d292dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa6f4004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6f40050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6f40050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb8d292cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c (3167 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv4i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv4i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv8i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv8i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vgmul_vv_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vgmul.vv.nxv16i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vgmul.vv.nxv16i32.i64(, , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(8,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkned,+zvknha,+zvknhb,+zvksed,+zvksh,+zvl128b,+zvl256b,+zvl32b,+zvl512b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvksed1p0_zvksh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557992a2c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557992a290f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557992a2c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0a0c21bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0a0c2725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0a0c21ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0a0c203507 abort ./stdlib/abort.c:85:3 # | #7 0x00005579929c1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005579929c1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005579929a6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005579926560b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557992655dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0a0c204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0a0c2050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0a0c2050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557992655cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c (3168 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 6) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005603642e515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005603642e20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005603642e589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa6d5533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa6d558a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa6d5533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa6d551b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056036427ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056036427ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056036425fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560363f0f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560363f0edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa6d551cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa6d551d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa6d551d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560363f0ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c (3169 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv1bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv2bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv4bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv8bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m4_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv16bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv16bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m8_tu( %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.nxv32bf16.p0.i64( %0, ptr %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv32bf16.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv1bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv2bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m1_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vle.mask.nxv4bf16.p0.i64( %1, ptr %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv4bf16.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16_v_bf16m2_tum( %vm, %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, # | ... # `---data was truncated (10240/24959) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e50aa6515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e50aa620f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e50aa6589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbe421bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbe42725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbe421ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbe4203507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e50a9fae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e50a9fac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e50a9dfb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e50a68f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e50a68edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbe4204fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbe42050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbe42050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e50a68ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c (3170 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv8i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m1_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesz.vs.nxv16i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesz_vs_u32m2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesz.vs.nxv4i32.nxv4i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willret # | ... # `---data was truncated (10240/15203) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557849f1e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557849f1b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557849f1e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f633c733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f633c78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f633c733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f633c71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557849eb3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557849eb3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557849e98b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557849b480b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557849b47dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f633c71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f633c71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f633c71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557849b47cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c (3171 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, i64 %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b7f76ef15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b7f76ec0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b7f76ef89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6c92b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6c92b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6c92b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6c92b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b7f7684e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b7f7684c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b7f7669b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b7f73190b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b7f7318dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6c92b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6c92b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6c92b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b7f7318cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c (3172 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i32.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vluxseg2ei32_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c (3173 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_i8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf8x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv1i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf4x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8mf2x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 7) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 3) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlsseg7e8_v_u8m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv8i1(target("riscv.vector.tup # | ... # `---data was truncated (10240/11031) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005574c63b215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005574c63af0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005574c63b289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe0a3649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe0a36a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe0a3649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe0a3631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005574c6347e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005574c6347c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005574c632cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005574c5fdc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005574c5fdbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe0a3632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe0a36330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe0a36330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005574c5fdbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c (3174 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c28d5fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c28d5f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c28d5fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e11733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e1178a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e11733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e1171b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c28d590e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c28d590c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c28d575b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c28d2250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c28d224dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e1171cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e1171d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e1171d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c28d224cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c (3175 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_i8m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf8x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv1i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e8_v_u8mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ad69c1215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ad69c0f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ad69c1289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4376533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f437658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4376533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f437651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ad69ba7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ad69ba7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ad69b8cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ad6983c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ad6983bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f437651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f437651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f437651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ad6983bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/bfloat16-convert-half.c (3176 of 27911) ******************** TEST 'Clang :: CodeGen/X86/bfloat16-convert-half.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | ; Function Attrs: noinline nounwind # | define dso_local half @test_convert_from_bf16_to_fp16(bfloat noundef %a) #0 { # | entry: # | %a.addr = alloca bfloat, align 2 # | store bfloat %a, ptr %a.addr, align 2 # | %0 = load bfloat, ptr %a.addr, align 2 # | %fpext = fpext bfloat %0 to float # | %fptrunc = fptrunc float %fpext to half # | ret half %fptrunc # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local bfloat @test_convert_from_fp16_to_bf16(half noundef %a) #0 { # | entry: # | %a.addr = alloca half, align 2 # | store half %a, ptr %a.addr, align 2 # | %0 = load half, ptr %a.addr, align 2 # | %fpext = fpext half %0 to float # | %fptrunc = fptrunc float %fpext to bfloat # | ret bfloat %fptrunc # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556ff5a0015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556ff59fd0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556ff5a0089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa895733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa89578a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa895733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa89571b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556ff5995e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556ff5995c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556ff597ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556ff562a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556ff5629dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa89571cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa89571d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa89571d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556ff5629cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/bfloat16-convert-half.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c (3177 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32mf2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32mf2_u32m8( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vv_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vv.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m1( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m2( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesdf.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesdf_vs_u32m1_u32m4( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesdf.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | ... # `---data was truncated (10240/20149) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560e055f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560e055f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560e055f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1072c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1072ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1072c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1072c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560e0558ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560e0558cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560e05571b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560e052210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560e05220dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1072c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1072c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1072c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560e05220cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/builtin-align.c (3178 of 27911) ******************** TEST 'Clang :: CodeGen/builtin-align.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple=x86_64-unknown-unknown -DTEST_VOID_PTR -o - -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | @aligned_true = global i8 1, align 1 # | @aligned_false = global i8 0, align 1 # | @down_1 = global i32 992, align 4 # | @down_2 = global i32 256, align 4 # | @up_1 = global i32 1024, align 4 # | @up_2 = global i32 256, align 4 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @get_type() #0 { # | entry: # | ret ptr null # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local zeroext i1 @is_aligned(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %src_addr = ptrtoint ptr %0 to i64 # | %set_bits = and i64 %src_addr, %mask # | %is_aligned = icmp eq i64 %set_bits, 0 # | ret i1 %is_aligned # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_up(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %over_boundary = getelementptr inbounds i8, ptr %0, i64 %mask # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %over_boundary, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare ptr @llvm.ptrmask.p0.i64(ptr, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @align_down(ptr noundef %ptr, i32 noundef %align) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %align.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %align, ptr %align.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %align.addr, align 4 # | %alignment = zext i32 %1 to i64 # | %mask = sub i64 %alignment, 1 # | %inverted_mask = xor i64 %mask, -1 # | %aligned_result = call ptr @llvm.ptrmask.p0.i64(ptr %0, i64 %inverted_mask) # | ret ptr %aligned_result # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } # | attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa # | #0 0x000055fb73df115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb73dee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb73df189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f77f2505b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f77f255c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f77f2505a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f77f24ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb73d86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb73d86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb73d6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb73a1b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb73a1add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f77f24eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f77f24ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f77f24ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb73a1acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope '-D$PTRTYPE=i8' # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtin-align.c -check-prefixes CHECK,CHECK-VOID_PTR -enable-var-scope -D$PTRTYPE=i8 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/AArch64/atomic-hint-template.cpp (3179 of 27911) ******************** TEST 'Clang :: CodeGen/AArch64/atomic-hint-template.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple aarch64-none-elf -target-feature +v9.4a -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" # | target triple = "aarch64-unknown-none-elf" # | # | $_Z37test_atomic_store_hint_template_orderILj3EEvPii = comdat any # | # | $_Z36test_atomic_store_hint_template_hintILj1EEvPii = comdat any # | # | $_Z37test_atomic_fetch_hint_template_orderILj2EEiPii = comdat any # | # | $_Z36test_atomic_fetch_hint_template_hintILj4EEiPii = comdat any # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z37test_atomic_store_hint_template_orderILj3EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 release, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr void @_Z36test_atomic_store_hint_template_hintILj1EEvPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | store atomic i32 %1, ptr %0 seq_cst, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z43test_atomic_store_hint_array_consexpr_orderPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !4 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define dso_local void @_Z42test_atomic_store_hint_array_consexpr_hintPii(ptr noundef %ptr, i32 noundef %value) #0 { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %value.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %value, ptr %value.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %value.addr, align 4 # | store atomic i32 %1, ptr %0 monotonic, align 4, !mem.cache_hint !6 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z37test_atomic_fetch_hint_template_orderILj2EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw add ptr %0, i32 %1 acquire, align 4, !mem.cache_hint !8 # | ret i32 %2 # | } # | # | ; Function Attrs: mustprogress noinline nounwind vscale_range(1,16) # | define weak_odr noundef i32 @_Z36test_atomic_fetch_hint_template_hintILj4EEiPii(ptr noundef %ptr, i32 noundef %val) #0 comdat { # | entry: # | %ptr.addr = alloca ptr, align 8 # | %val.addr = alloca i32, align 4 # | store ptr %ptr, ptr %ptr.addr, align 8 # | store i32 %val, ptr %val.addr, align 4 # | %0 = load ptr, ptr %ptr.addr, align 8 # | %1 = load i32, ptr %val.addr, align 4 # | %2 = atomicrmw xor ptr %0, i32 %1 seq_cst, align 4, !mem.cache_hint !10 # | ret i32 %2 # | } # | # | attributes #0 = { mustprogress noinline nounwind vscale_range(1,16) "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+cssc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+hbc,+i8mm,+jsconv,+lse,+mec,+mops,+neon,+pauth,+predres,+ras,+rasv2,+rcpc,+rdm,+rme,+sb,+spe-eef,+specres2,+ssbs,+sve,+sve2,+sve2p1,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v8.9a,+v8a,+v9.1a,+v9.2a,+v9.3a,+v9.4a,+v9a,+wfxt" } # | # | !llvm.module.flags = !{!0, !1, !2} # | !llvm.ident = !{!3} # | # | !0 = !{i32 1, !"ptrauth-elf-got", i32 0} # | !1 = !{i32 1, !"ptrauth-init-fini", i32 0} # | !2 = !{i32 1, !"ptrauth-init-fini-address-discrimination", i32 0} # | !3 = !{!"clang version 24.0.0"} # | !4 = !{i32 1, !5} # | !5 = !{!"aarch64.mem_hint", i32 0} # | !6 = !{i32 1, !7} # | !7 = !{!"aarch64.mem_hint", i32 1} # | !8 = !{i32 0, !9} # | !9 = !{!"aarch64.mem_hint", i32 3} # | !10 = !{i32 0, !11} # | !11 = !{!"aarch64.mem_hint", i32 4} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a883c8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a883c8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a883c8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa0c5649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa0c56a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa0c5649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa0c5631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a883c24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a883c24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a883c09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a8838b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a8838b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa0c5632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa0c56330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa0c56330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a8838b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/AArch64/atomic-hint-template.cpp # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c (3180 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmmbase -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_i8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.vlte8.i64(i64, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_vlte8_u8(i64 noundef %tss, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %tss.addr = alloca i64, align 8 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store i64 %tss, ptr %tss.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load i64, ptr %tss.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vlte8.i64(i64 %0, ptr %1, i64 %2) # | ret void # | } # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xsfmmbase,+zicsr,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055df0562815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055df056250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055df0562889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f442be49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f442bea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f442be49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f442be31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055df055bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055df055bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055df055a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055df052520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055df05251dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f442be32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f442be330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f442be330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055df05251cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c (3181 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei8_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 7), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ed1034915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ed103460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ed1034989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe96d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe96d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe96d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe96d031507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ed102dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ed102dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ed102c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ed0ff730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ed0ff72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe96d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe96d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe96d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ed0ff72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c (3182 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tu(target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf2x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16m1x7_tum( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16_v_bf16mf4x7_tumu( %vm, target("riscv.vector.tuple", , 7) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 7) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %1, ptr %2, %0, i64 %3, i64 0, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", # | ... # `---data was truncated (10240/16800) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563ba5cf115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563ba5cee0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563ba5cf189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa05e049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa05e0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa05e049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa05e031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563ba5c86e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563ba5c86c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563ba5c6bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563ba591b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563ba591add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa05e032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa05e0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa05e0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563ba591acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c (3183 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknh -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sig1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sig1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum0(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum0(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha256sum1(i32 noundef %rs1) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | %1 = load i32, ptr %__x.addr.i, align 4 # | %2 = call i32 @llvm.riscv.sha256sum1(i32 %1) # | ret i32 %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig0l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig0l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1h(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1h(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sig1l(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sig1l(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum0r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum0r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @sha512sum1r(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %__x.addr.i = alloca i32, align 4 # | %__y.addr.i = alloca i32, align 4 # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | store i32 %0, ptr %__x.addr.i, align 4 # | store i32 %1, ptr %__y.addr.i, align 4 # | %2 = load i32, ptr %__x.addr.i, align 4 # | %3 = load i32, ptr %__y.addr.i, align 4 # | %4 = call i32 @llvm.riscv.sha512sum1r(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sig1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum0(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha256sum1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig0l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1h(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sig1l(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum0r(i32, i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.sha512sum1r(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknh" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknh1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005608b4b9c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005608b4b990f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005608b4b9c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdbea533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdbea58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdbea533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdbea51b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005608b4b31e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005608b4b31c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005608b4b16b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005608b47c60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005608b47c5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdbea51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdbea51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdbea51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005608b47c5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c -check-prefix=RV32ZKNH # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c (3184 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei64_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bbbf3b615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bbbf3b30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bbbf3b689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4eaf33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4eaf8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4eaf33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4eaf1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bbbf34be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bbbf34bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bbbf330b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bbbefe00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bbbefdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4eaf1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4eaf1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4eaf1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bbbefdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c (3185 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056412f6e915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056412f6e60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056412f6e989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fabd4f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fabd4f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fabd4f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fabd4f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056412f67ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056412f67ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056412f663b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056412f3130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056412f312dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fabd4f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fabd4f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fabd4f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056412f312cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c (3186 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8f64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8f64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv1i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv2i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv4i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_i64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.nxv8i64.p0.i64(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv1i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv2i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv4i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_u64m8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vle.nxv8i64.p0.i64( poison, ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m1_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv1f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv1f64.p0.i64(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle64_v_f64m2_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vle.mask.nxv2f64.p0.i64( poison, ptr %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vle.mask.nxv2f64.p0.i64(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c (3187 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_f32m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 5) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e32ff_v_i32m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv. # | ... # `---data was truncated (10240/17879) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056552ca8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056552ca8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056552ca8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0d40249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0d402a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0d40249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0d40231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056552ca22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056552ca22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056552ca07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056552c6b70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056552c6b6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0d40232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0d402330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0d402330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056552c6b6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c (3188 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_i64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_u64m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m1x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e64_v_f64m2x3_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Functi # | ... # `---data was truncated (10240/15986) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056309703515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005630970320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056309703589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8ba4649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8ba46a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8ba4649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8ba4631507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563096fcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563096fcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563096fafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563096c5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563096c5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8ba4632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8ba46330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8ba46330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563096c5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c (3189 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_f64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_i64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg7e64_v_u64m1x7_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 7) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 7) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 7) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005604e279b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604e27980f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005604e279b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff8ed849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff8ed8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff8ed849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff8ed831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604e2730e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604e2730c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604e2715b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604e23c50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005604e23c4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff8ed832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff8ed8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff8ed8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005604e23c4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c (3190 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv1bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv1bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv2bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv2bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m1_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv4bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv4bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m2_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv8bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv8bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m4_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv16bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv16bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16m8_tu( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vslidedown.nxv32bf16.i64( %0, %1, i64 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.nxv32bf16.i64(, , i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv1bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vslidedown.mask.nxv1bf16.i64(, , i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vslidedown_vx_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %rs1.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vslidedown.mask.nxv2bf16.i64( %1, %2, i64 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv. # | ... # `---data was truncated (10240/30759) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005572f98d915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005572f98d60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005572f98d989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f32f7b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32f7b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f32f7b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f32f7aed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005572f986ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005572f986ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005572f9853b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005572f95030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005572f9502dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f32f7aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32f7aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32f7aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005572f9502cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c (3191 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei64_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 6) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i64.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558477c3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558477c320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558477c3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcf8f133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcf8f18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcf8f133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcf8f11b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558477bcae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558477bcac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558477bafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055847785f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055847785edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcf8f11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcf8f11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcf8f11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055847785ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c (3192 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m2_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m4_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m8_tu( %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64( %0, %1, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv32bf16.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf4_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv1bf16.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16mf2_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 2 # | %2 = load , ptr %op1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64( %1, %2, %2, %0, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.mask.nxv2bf16.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfneg_v_bf16m1_tum( %mask, %maskedoff, %op1, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | ... # `---data was truncated (10240/29304) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556465c6015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556465c5d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556465c6089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ef5e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ef5ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ef5e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ef5e31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556465bf5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556465bf5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556465bdab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055646588a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556465889dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ef5e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ef5e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ef5e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556465889cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c (3193 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16mf2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m1x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m2x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv16i8_2t.p0.i64.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlsseg2e16_v_bf16m4x2_m( %vm, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.i64.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005622e20c515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005622e20c20f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005622e20c589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe678d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe678d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe678d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe678d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005622e205ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005622e205ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005622e203fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005622e1cef0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005622e1ceedd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe678d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe678d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe678d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005622e1ceecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c (3194 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffb(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffb.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffb.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffzmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffzmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffzmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_ffmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.ffmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.ffmism.i64(i64, i64) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i64 @test_flmism(i64 noundef %a, i64 noundef %b) #0 { # | entry: # | %a.addr = alloca i64, align 8 # | %b.addr = alloca i64, align 8 # | store i64 %a, ptr %a.addr, align 8 # | store i64 %b, ptr %b.addr, align 8 # | %0 = load i64, ptr %a.addr, align 8 # | %1 = load i64, ptr %b.addr, align 8 # | %2 = call i64 @llvm.riscv.nds.flmism.i64(i64 %0, i64 %1) # | ret i64 %2 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i64 @llvm.riscv.nds.flmism.i64(i64, i64) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564c8e07a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564c8e0770f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564c8e07a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ff3c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ff3ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ff3c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ff3c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564c8e00fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564c8e00fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564c8dff4b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564c8dca40b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564c8dca3dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7ff3c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ff3c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ff3c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564c8dca3cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-rv64.c --check-prefix=CHECK-RV64 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c (3195 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8mf2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv4i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m1x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv8i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m2x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv16i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_i8m4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t.i64.p0(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf8x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t.i64.p0(target("riscv.vector.tuple", , 2) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e8ff_v_u8mf4x2(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv2i8_2t.i64.p0(target("riscv.vect # | ... # `---data was truncated (10240/32932) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056047066815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005604706650f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056047066889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fca28049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fca280a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fca28049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fca28031507 abort ./stdlib/abort.c:85:3 # | #7 0x00005604705fde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005604705fdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005604705e2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005604702920b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560470291dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fca28032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fca280330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fca280330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560470291cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c (3196 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f16m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32mf2x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f32m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_f64m1x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf8x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv1i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_i8mf4x6(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none # | ... # `---data was truncated (10240/61673) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ef86f715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558ef86f40f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ef86f789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa22c533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa22c58a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa22c533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa22c51b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558ef868ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558ef868cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558ef8671b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ef83210b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ef8320dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa22c51cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa22c51d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa22c51d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ef8320cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c (3197 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tu(target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf4x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16mf2x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vluxseg5ei32_v_bf16m1x5_tum( %vm, target("riscv.vector.tuple", , 5) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 5) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 5), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 5) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64 # | ... # `---data was truncated (10240/19582) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5622cf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5622cc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5622cf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd64bd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd64bd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd64bd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd64bd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d562264e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d562264c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d562249b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d561ef90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d561ef8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd64bd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd64bd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd64bd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d561ef8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c (3198 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8mf2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m1_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m2_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m4_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u8m8_u8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf4_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16mf2_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmaxu.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmaxu_vs_u16m1_u16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, pt # | ... # `---data was truncated (10240/52733) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d88501115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d88500e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d88501189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fce98333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fce9838a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fce98333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fce9831b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d884fa6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d884fa6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d884f8bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d884c3b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d884c3add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fce9831cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fce9831d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fce9831d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d884c3acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c (3199 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccus_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bc598dc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bc598d90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bc598dc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd0bd133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd0bd18a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd0bd133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd0bd11b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bc59871e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bc59871c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bc59856b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bc595060b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bc59505dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd0bd11cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd0bd11d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd0bd11d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bc59505cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c (3200 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564f3366315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564f336600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564f3366389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3dea449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3dea4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3dea449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3dea431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564f335f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564f335f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564f335ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564f3328d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564f3328cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3dea432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3dea4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3dea4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564f3328ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c (3201 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( poison, %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv16bf16.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 % # | ... # `---data was truncated (10240/29210) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b5bc89115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b5bc88e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b5bc89189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7ebd305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7ebd35c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7ebd305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7ebd2ed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b5bc826e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b5bc826c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b5bc80bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b5bc4bb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b5bc4badd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7ebd2eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7ebd2ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7ebd2ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b5bc4bacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c (3202 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8(ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 8) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 8) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 8), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005638e450e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005638e450b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005638e450e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f86fc849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f86fc8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f86fc849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f86fc831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005638e44a3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005638e44a3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005638e4488b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005638e41380b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005638e4137dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f86fc832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f86fc8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f86fc8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005638e4137cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c (3203 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m1_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv4bf16.p0.nxv4i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m2_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv8bf16.p0.nxv8i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m4_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv16bf16.p0.nxv16i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16m8_tu( %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64( %0, ptr %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.nxv32bf16.p0.nxv32i8.i64(, ptr captures(none), , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv1bf16.p0.nxv1i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vloxei8_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64( %1, ptr %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare @llvm.riscv.vloxei.mask.nxv2bf16.p0.nxv2i8.i64(, ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Fu # | ... # `---data was truncated (10240/30423) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc7266215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc7265f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc7266289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff99ed05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff99ed5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff99ed05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff99eced507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc725f7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc725f7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc725dcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc7228c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc7228bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff99eceefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff99ecef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff99ecef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc7228bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGenCoroutines/pr65054.cpp (3204 of 27911) ******************** TEST 'Clang :: CodeGenCoroutines/pr65054.cpp' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 4 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes='sroa,mem2reg,simplifycfg' -S | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple x86_64-unknown-linux-gnu -std=c++20 -O0 -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-linux-gnu" # | # | %struct.MyTask = type { %"struct.std::coroutine_handle" } # | %"struct.std::coroutine_handle" = type { ptr } # | %"struct.std::suspend_always" = type { i8 } # | %struct.Awaiter = type { ptr } # | %"struct.std::coroutine_handle.0" = type { %"struct.std::coroutine_handle" } # | # | $_ZN6MyTask12promise_type17get_return_objectEv = comdat any # | # | $_ZN6MyTask12promise_type15initial_suspendEv = comdat any # | # | $_ZNSt14suspend_always11await_readyEv = comdat any # | # | $_ZNSt14suspend_always13await_suspendESt16coroutine_handleIvE = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv = comdat any # | # | $_ZNSt14suspend_always12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type15await_transformERKi = comdat any # | # | $_ZN7Awaiter11await_readyEv = comdat any # | # | $_ZNKSt16coroutine_handleIvE7addressEv = comdat any # | # | $_ZN7Awaiter12await_resumeEv = comdat any # | # | $_ZN6MyTask12promise_type13final_suspendEv = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_ = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC1Ev = comdat any # | # | $_ZNSt16coroutine_handleIN6MyTask12promise_typeEEC2Ev = comdat any # | # | $_ZNSt16coroutine_handleIvEC2Ev = comdat any # | # | @g_array = global [32 x i32] zeroinitializer, align 16 # | # | ; Function Attrs: mustprogress noinline nounwind # | define dso_local ptr @_Z6FooBarv() #0 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %undef.agg.tmp = alloca %"struct.std::suspend_always", align 1 # | %undef.agg.tmp19 = alloca %"struct.std::suspend_always", align 1 # | %call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 64) #6 # | store ptr @_Z6FooBarv.resume, ptr %call, align 8 # | %0 = select i1 true, ptr @_Z6FooBarv.destroy, ptr @_Z6FooBarv.cleanup # | %destroy.addr = getelementptr inbounds i8, ptr %call, i64 8 # | store ptr %0, ptr %destroy.addr, align 8 # | %ref.tmp.reload.addr = getelementptr inbounds i8, ptr %call, i64 18 # | %__range1.reload.addr = getelementptr inbounds i8, ptr %call, i64 24 # | %__begin1.reload.addr = getelementptr inbounds i8, ptr %call, i64 32 # | %__end1.reload.addr = getelementptr inbounds i8, ptr %call, i64 40 # | %x.reload.addr = getelementptr inbounds i8, ptr %call, i64 48 # | %ref.tmp4.reload.addr = getelementptr inbounds i8, ptr %call, i64 56 # | %ref.tmp18.reload.addr = getelementptr inbounds i8, ptr %call, i64 19 # | %__promise.reload.addr = getelementptr inbounds i8, ptr %call, i64 16 # | %call1 = call ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %coerce.dive = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call1, ptr %coerce.dive2, align 8 # | call void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) # | %call3 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | br i1 %call3, label %init.ready, label %CoroSave # | # | CoroSave: ; preds = %entry # | %index.addr39 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 0, ptr %index.addr39, align 1 # | call void @_Z6FooBarv.__await_suspend_wrapper__init(ptr %ref.tmp.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | init.ready: ; preds = %entry # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp.reload.addr) #7 # | store ptr @g_array, ptr %__range1.reload.addr, align 8 # | store ptr @g_array, ptr %__begin1.reload.addr, align 8 # | store ptr getelementptr inbounds nuw (i8, ptr @g_array, i64 128), ptr %__end1.reload.addr, align 8 # | br label %for.cond # | # | for.cond: ; preds = %for.inc, %init.ready # | %1 = load ptr, ptr %__begin1.reload.addr, align 8 # | %2 = load ptr, ptr %__end1.reload.addr, align 8 # | %cmp = icmp ne ptr %1, %2 # | br i1 %cmp, label %for.body, label %coro.final # | # | for.body: ; preds = %for.cond # | %3 = load ptr, ptr %__begin1.reload.addr, align 8 # | store ptr %3, ptr %x.reload.addr, align 8 # | %4 = load ptr, ptr %x.reload.addr, align 8, !nonnull !1, !align !2 # | %call5 = call ptr @_ZN6MyTask12promise_type15await_transformERKi(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr, ptr noundef nonnull align 4 dereferenceable(4) %4) # | %coerce.dive6 = getelementptr inbounds nuw %struct.Awaiter, ptr %ref.tmp4.reload.addr, i32 0, i32 0 # | store ptr %call5, ptr %coerce.dive6, align 8 # | %call7 = call noundef zeroext i1 @_ZN7Awaiter11await_readyEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | br i1 %call7, label %await.ready, label %CoroSave27 # | # | CoroSave27: ; preds = %for.body # | %index.addr40 = getelementptr inbounds i8, ptr %call, i64 17 # | store i8 1, ptr %index.addr40, align 1 # | %5 = call ptr @_Z6FooBarv.__await_suspend_wrapper__await(ptr %ref.tmp4.reload.addr, ptr %call) # | %6 = getelementptr inbounds { ptr, ptr }, ptr %5, i32 0, i32 0 # | %7 = load ptr, ptr %6, align 8 # | call void %7(ptr %5) # | br label %AfterCoroEnd # | # | await.ready: ; preds = %for.body # | call void @_ZN7Awaiter12await_resumeEv(ptr noundef nonnull align 8 dereferenceable(8) %ref.tmp4.reload.addr) # | %cond = icmp eq i32 0, 0 # | %cond26 = icmp eq i32 0, 0 # | br i1 %cond26, label %for.inc, label %coro.final # | # | for.inc: ; preds = %await.ready # | %8 = load ptr, ptr %__begin1.reload.addr, align 8 # | %incdec.ptr = getelementptr inbounds nuw i32, ptr %8, i32 1 # | store ptr %incdec.ptr, ptr %__begin1.reload.addr, align 8 # | br label %for.cond # | # | coro.final: ; preds = %await.ready, %for.cond # | call void @_ZN6MyTask12promise_type13final_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %__promise.reload.addr) #7 # | %call20 = call noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | br i1 %call20, label %final.ready, label %CoroSave31 # | # | CoroSave31: ; preds = %coro.final # | store ptr null, ptr %call, align 8 # | call void @_Z6FooBarv.__await_suspend_wrapper__final(ptr %ref.tmp18.reload.addr, ptr %call) #7 # | br label %AfterCoroEnd # | # | final.ready: ; preds = %coro.final # | call void @_ZNSt14suspend_always12await_resumeEv(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp18.reload.addr) #7 # | %9 = icmp ne ptr %call, null # | br i1 %9, label %coro.free, label %AfterCoroEnd # | # | coro.free: ; preds = %final.ready # | call void @_ZdlPvm(ptr noundef %call, i64 noundef 64) #7 # | br label %AfterCoroEnd # | # | AfterCoroEnd: ; preds = %coro.free, %final.ready, %CoroSave27, %CoroSave31, %CoroSave # | %coerce.dive24 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive25 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive24, i32 0, i32 0 # | %10 = load ptr, ptr %coerce.dive25, align 8 # | ret ptr %10 # | } # | # | ; Function Attrs: nobuiltin allocsize(0) # | declare noundef nonnull ptr @_Znwm(i64 noundef) #1 # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr ptr @_ZN6MyTask12promise_type17get_return_objectEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %retval = alloca %struct.MyTask, align 8 # | %this.addr = alloca ptr, align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | %h = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_promiseERS1_(ptr noundef nonnull align 1 dereferenceable(1) %this1) # | %coerce.dive = getelementptr inbounds nuw %"struct.std::coroutine_handle.0", ptr %ref.tmp, i32 0, i32 0 # | %coerce.dive2 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive, i32 0, i32 0 # | store ptr %call, ptr %coerce.dive2, align 8 # | call void @llvm.memcpy.p0.p0.i64(ptr align 8 %h, ptr align 8 %ref.tmp, i64 8, i1 false) # | %coerce.dive3 = getelementptr inbounds nuw %struct.MyTask, ptr %retval, i32 0, i32 0 # | %coerce.dive4 = getelementptr inbounds nuw %"struct.std::coroutine_handle", ptr %coerce.dive3, i32 0, i32 0 # | %0 = load ptr, ptr %coerce.dive4, align 8 # | ret ptr %0 # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr void @_ZN6MyTask12promise_type15initial_suspendEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret void # | } # | # | ; Function Attrs: mustprogress noinline nounwind # | define linkonce_odr noundef zeroext i1 @_ZNSt14suspend_always11await_readyEv(ptr noundef nonnull align 1 dereferenceable(1) %this) #0 comdat align 2 { # | entry: # | %this.addr = alloca ptr, align 8 # | store ptr %this, ptr %this.addr, align 8 # | %this1 = load ptr, ptr %this.addr, align 8 # | ret i1 false # | } # | # | ; Function Attrs: alwaysinline mustprogress nounwind # | define internal void @_Z6FooBarv.__await_suspend_wrapper__init(ptr noundef nonnull %0, ptr noundef %1) #2 { # | entry: # | %.addr = alloca ptr, align 8 # | %.addr1 = alloca ptr, align 8 # | %agg.tmp = alloca %"struct.std::coroutine_handle", align 8 # | %ref.tmp = alloca %"struct.std::coroutine_handle.0", align 8 # | store ptr %0, ptr %.addr, align 8 # | store ptr %1, ptr %.addr1, align 8 # | %2 = load ptr, ptr %.addr, align 8 # | %3 = load ptr, ptr %.addr1, align 8 # | %call = call ptr @_ZNSt16coroutine_handleIN6MyTask12promise_typeEE12from_addressEPv(ptr noundef %3) #7 # | # | ... # `---data was truncated (10240/37953) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -passes=sroa,mem2reg,simplifycfg -S # | #0 0x000055877104e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055877104b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055877104e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5793b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5793b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5793b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5793b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558770fe3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558770fe3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558770fc8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558770c780b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558770c77dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5793b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5793b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5793b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558770c77cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGenCoroutines/pr65054.cpp --check-prefix=CHECK-O0 # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c (3205 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv2i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv4i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.triscv.vector.tuple_nxv8i8_6t.i64.p0(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv2i8_6t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 6), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 6) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 6), i64 } @llvm.riscv.vlseg6ff.mask.triscv.vector.tuple_nxv4i8_6t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e16ff_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("risc # | ... # `---data was truncated (10240/21103) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000559f9a03415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000559f9a0310f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000559f9a03489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efef3a1bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efef3a725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efef3a1ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efef3a03507 abort ./stdlib/abort.c:85:3 # | #7 0x0000559f99fc9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000559f99fc9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000559f99faeb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000559f99c5e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000559f99c5ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efef3a04fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efef3a050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efef3a050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000559f99c5dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c (3206 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf4_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf4_b64( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv1bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv1bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16mf2_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16mf2_b32( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv2bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv2bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m1_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m1_b16( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv4bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv4bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m2_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m2_b8( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv8bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv8bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m4_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load , ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vf_bf16m4_b4( %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load bfloat, ptr %op2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmfgt.nxv16bf16.bf16.i64( %0, bfloat %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmfgt.nxv16bf16.bf16.i64(, bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmfgt_vv_bf16m8_b2( %op1, ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c (3207 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3(ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, i64 %1, i64 4) # | ret target("riscv.vector.tuple", , 3) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m1x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_bf16m2x3_m( %vm, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b794e5815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b794e550f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b794e5889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc6f0933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc6f098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc6f0933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc6f091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b794dede2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b794dedc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b794dd2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b794a820b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b794a81dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc6f091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc6f091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc6f091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b794a81cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c (3208 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsuxseg6ei32_v_bf16m1x6_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 6) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 4 # | %vs3.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 4 # | store target("riscv.vector.tuple", , 6) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load target("riscv.vector.tuple", , 6), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557105c5c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557105c590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557105c5c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe018733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe01878a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe018733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe01871b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557105bf1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557105bf1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557105bd6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005571058860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557105885dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe01871cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe01871d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe01871d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557105885cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c (3209 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f505ecc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f505ec90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f505ecc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f87d3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f87d358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f87d3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f87d351b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f505e61e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f505e61c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f505e46b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f505af60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f505af5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f87d351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f87d351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f87d351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f505af5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c (3210 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m2_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv8bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv8bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m1( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv4bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv4bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m4_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv16bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv16bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m2( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv8bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv8bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16m8_bf16m4( %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca , align 2 # | %index.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = call @llvm.vector.extract.nxv16bf16.nxv32bf16( %0, i64 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.extract.nxv16bf16.nxv32bf16(, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x2_bf16mf4(target("riscv.vector.tuple", , 2) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", , 2), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x3_bf16mf4(target("riscv.vector.tuple", , 3) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", , 3), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x4_bf16mf4(target("riscv.vector.tuple", , 4) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", , 4), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x5_bf16mf4(target("riscv.vector.tuple", , 5) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 5), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 5) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 5), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", , 5), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x6_bf16mf4(target("riscv.vector.tuple", , 6) %src, i64 noundef %index) #0 { # | entry: # | %src.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %index.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %src, ptr %src.addr, align 2 # | store i64 %index, ptr %index.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %src.addr, align 2 # | %1 = call @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6) %0, i32 0) # | ret %1 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.riscv.tuple.extract.nxv1bf16.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", , 6), i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vget_v_bf16mf4x7_bf16mf4(target("riscv.vector.tuple", ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c (3211 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmacc_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b21727515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b2172720f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b21727589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f75c8249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f75c82a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f75c8249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f75c8231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b21720ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b21720ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b2171efb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b216e9f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b216e9edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f75c8232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f75c82330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f75c82330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b216e9ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c (3212 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_f16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv2i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16mf2x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv4i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_i16m1x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 7), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 7), i64 } @llvm.riscv.vlseg7ff.triscv.vector.tuple_nxv8i8_7t.i64.p0(target("riscv.vector.tuple", , 7) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 7), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 7) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vlseg7e16ff_v_u16mf4x7_tu(target("riscv.vector.tuple", , 7) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %base.addr = alloca # | ... # `---data was truncated (10240/60551) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056099b7de15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056099b7db0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056099b7de89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe7a5849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe7a58a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe7a5849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe7a5831507 abort ./stdlib/abort.c:85:3 # | #7 0x000056099b773e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056099b773c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056099b758b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056099b4080b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056099b407dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe7a5832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe7a58330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe7a58330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056099b407cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/X86/sse.c (3213 of 27911) ******************** TEST 'Clang :: CodeGen/X86/sse.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -ffreestanding -triple x86_64-- -target-feature +sse4.1 -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c" # | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" # | target triple = "x86_64-unknown-unknown" # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %pslldq = shufflevector <16 x i8> zeroinitializer, <16 x i8> %1, <16 x i32> # | %2 = bitcast <16 x i8> %pslldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_slli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_0(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | %psrldq = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> # | %2 = bitcast <16 x i8> %psrldq to <2 x i64> # | ret <2 x i64> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local <2 x i64> @test_mm_srli_si128_16(<2 x i64> noundef %a) #0 { # | entry: # | %a.addr = alloca <2 x i64>, align 16 # | store <2 x i64> %a, ptr %a.addr, align 16 # | %0 = load <2 x i64>, ptr %a.addr, align 16 # | %1 = bitcast <2 x i64> %0 to <16 x i8> # | ret <2 x i64> zeroinitializer # | } # | # | attributes #0 = { noinline nounwind "min-legal-vector-width"="128" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" } # | # | !llvm.ident = !{!0} # | # | !0 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b9ed1415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b9ed110f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b9ed1489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f08fec49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f08feca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f08fec49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f08fec31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b9eca9e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b9eca9c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b9ec8eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b9e93e0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b9e93ddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f08fec32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f08fec330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f08fec330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b9e93dcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/X86/sse.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c (3214 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2. # | ... # `---data was truncated (10240/18498) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e82afed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e82afea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e82afed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efca9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efca918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efca9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efca911b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e82af82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e82af82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e82af67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e82ac170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e82ac16dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efca911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efca911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efca911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e82ac16cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c (3215 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +xsfmm32a8f -target-feature +experimental-zvfofp8min -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_sf_mm_e4m3_e4m3_w4_f8e4m3m8_f8e4m3m8( %vs2, %vs1, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) #0 { # | entry: # | %vs2.addr = alloca , align 1 # | %vs1.addr = alloca , align 1 # | %tm.addr = alloca i64, align 8 # | %tn.addr = alloca i64, align 8 # | %tk.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store %vs1, ptr %vs1.addr, align 1 # | store i64 %tm, ptr %tm.addr, align 8 # | store i64 %tn, ptr %tn.addr, align 8 # | store i64 %tk, ptr %tk.addr, align 8 # | %0 = load , ptr %vs2.addr, align 1 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load i64, ptr %tm.addr, align 8 # | %3 = load i64, ptr %tn.addr, align 8 # | %4 = load i64, ptr %tk.addr, align 8 # | call void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 0, %0, %1, i64 %2, i64 %3, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare void @llvm.riscv.sf.mm.e4m3.e4m3.i64.nxv64i8(i64 immarg, , , i64, i64, i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+experimental-zvfofp8min,+f,+i,+xsfmm32a8f,+xsfmmbase,+zicsr,+zve32f,+zve32x,+zvl32b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p9_zvl32b1p0_xsfmm32a8f0p6_xsfmmbase0p6"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055bb9ea3615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055bb9ea330f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055bb9ea3689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faf8d249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faf8d2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faf8d249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faf8d231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055bb9e9cbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055bb9e9cbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055bb9e9b0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055bb9e6600b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055bb9e65fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faf8d232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faf8d2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faf8d2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055bb9e65fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c (3216 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 7) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564061f8d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564061f8a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564061f8d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8b7e733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8b7e78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8b7e733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8b7e71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564061f22e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564061f22c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564061f07b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564061bb70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564061bb6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8b7e71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8b7e71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8b7e71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564061bb6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c (3217 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vluxseg6ei8_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005653252bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005653252b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005653252bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd905d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd905d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd905d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd905d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565325251e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565325251c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565325236b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565324ee60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565324ee5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd905d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd905d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd905d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565324ee5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c (3218 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf8x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv1i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf4x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv2i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8mf2x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv4i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_u8m1x5(ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load ptr, ptr %new_vl.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call { target("riscv.vector.tuple", , 5), i64 } @llvm.riscv.vlseg5ff.triscv.vector.tuple_nxv8i8_5t.i64.p0(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %2, i64 3) # | %4 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 0 # | %5 = extractvalue { target("riscv.vector.tuple", , 5), i64 } %3, 1 # | store i64 %5, ptr %1, align 8 # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e8ff_v_i8mf8x5_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %m # | ... # `---data was truncated (10240/22258) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ca29a6315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ca29a600f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ca29a6389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e09b05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e09b5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e09b05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e09aed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ca299f8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ca299f8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ca299ddb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ca2968d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ca2968cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e09aeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e09aef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e09aef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ca2968ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c (3219 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +zknd -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsi(i32, i32, i32 immarg) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @aes32dsmi(i32 noundef %rs1, i32 noundef %rs2) #0 { # | entry: # | %rs1.addr = alloca i32, align 4 # | %rs2.addr = alloca i32, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i32 %rs2, ptr %rs2.addr, align 4 # | %0 = load i32, ptr %rs1.addr, align 4 # | %1 = load i32, ptr %rs2.addr, align 4 # | %2 = call i32 @llvm.riscv.aes32dsmi(i32 %0, i32 %1, i32 3) # | ret i32 %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.riscv.aes32dsmi(i32, i32, i32 immarg) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+zknd" } # | attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_zknd1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005580a4ad915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005580a4ad60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005580a4ad989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f929ea49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f929eaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f929ea49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f929ea31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005580a4a6ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005580a4a6ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005580a4a53b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005580a47030b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005580a4702dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f929ea32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f929ea330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f929ea330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005580a4702cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c -check-prefix=RV32ZKND # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c (3220 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d5de8b115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d5de8ae0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d5de8b189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff69db33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff69db8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff69db33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff69db1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d5de846e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d5de846c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d5de82bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d5de4db0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d5de4dadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff69db1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff69db1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff69db1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d5de4dacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c (3221 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m2x3_tu(target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf4x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16mf2x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 3), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 3) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 3), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlsseg3e16_v_bf16m1x3_tum( %vm, target("riscv.vector.tuple", , 3) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 # | ... # `---data was truncated (10240/24373) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d28eaed15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d28eaea0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d28eaed89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f36dd333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f36dd38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f36dd333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f36dd31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d28ea82e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d28ea82c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d28ea67b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d28e7170b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d28e716dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f36dd31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f36dd31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f36dd31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d28e716cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/builtins-arm.c (3222 of 27911) ******************** TEST 'Clang :: CodeGen/builtins-arm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 1 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -Wall -Wno-unused-but-set-variable -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv7-unknown-unknown-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local ptr @f0() #0 { # | entry: # | %0 = call ptr @llvm.thread.pointer.p0() # | ret ptr %0 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare ptr @llvm.thread.pointer.p0() #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @f1(ptr noundef %a, ptr noundef %b) #0 { # | entry: # | %a.addr = alloca ptr, align 4 # | %b.addr = alloca ptr, align 4 # | store ptr %a, ptr %a.addr, align 4 # | store ptr %b, ptr %b.addr, align 4 # | %0 = load ptr, ptr %a.addr, align 4 # | %1 = load ptr, ptr %b.addr, align 4 # | call void @llvm.clear_cache.p0(ptr %0, ptr %1) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.clear_cache.p0(ptr, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf0(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtr.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local float @test_vcvtrf1(float noundef %f) #0 { # | entry: # | %f.addr = alloca float, align 4 # | store float %f, ptr %f.addr, align 4 # | %0 = load float, ptr %f.addr, align 4 # | %vcvtr = call float @llvm.arm.vcvtru.f32(float %0) # | ret float %vcvtr # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f32(float) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd0(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtr.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtr.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local double @test_vcvtrd1(double noundef %d) #0 { # | entry: # | %d.addr = alloca double, align 8 # | store double %d, ptr %d.addr, align 8 # | %0 = load double, ptr %d.addr, align 8 # | %vcvtr = call float @llvm.arm.vcvtru.f64(double %0) # | %conv = fpext float %vcvtr to double # | ret double %conv # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare float @llvm.arm.vcvtru.f64(double) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_eh_return_data_regno() #0 { # | entry: # | %res = alloca i32, align 4 # | store volatile i32 0, ptr %res, align 4 # | store volatile i32 1, ptr %res, align 4 # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @nop() #0 { # | entry: # | call void @llvm.arm.hint(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.hint(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @yield() #0 { # | entry: # | call void @llvm.arm.hint(i32 1) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfe() #0 { # | entry: # | call void @llvm.arm.hint(i32 2) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @wfi() #0 { # | entry: # | call void @llvm.arm.hint(i32 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sev() #0 { # | entry: # | call void @llvm.arm.hint(i32 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @sevl() #0 { # | entry: # | call void @llvm.arm.hint(i32 5) # | ret void # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local void @dbg() #0 { # | entry: # | call void @llvm.arm.dbg(i32 0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dbg(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @test_barrier() #0 { # | entry: # | call void @llvm.arm.dmb(i32 1) # | call void @llvm.arm.dsb(i32 2) # | call void @llvm.arm.isb(i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dmb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.dsb(i32) #2 # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.isb(i32) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @rbit(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %rbit = call i32 @llvm.bitreverse.i32(i32 %0) # | ret i32 %rbit # | } # | # | ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) # | declare i32 @llvm.bitreverse.i32(i32) #3 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @prefetch(i32 noundef %i) #0 { # | entry: # | %i.addr = alloca i32, align 4 # | store i32 %i, ptr %i.addr, align 4 # | call void @llvm.prefetch.p0(ptr %i.addr, i32 0, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 1) # | call void @llvm.prefetch.p0(ptr %i.addr, i32 1, i32 3, i32 0) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) # | declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg range(i32 0, 2), i32 immarg range(i32 0, 4), i32 immarg range(i32 0, 2)) #4 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @ldc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.ldc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.ldc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stcl(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stcl(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stcl(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @stc2l(ptr noundef %i) #0 { # | entry: # | %i.addr = alloca ptr, align 4 # | store ptr %i, ptr %i.addr, align 4 # | %0 = load ptr, ptr %i.addr, align 4 # | call void @llvm.arm.stc2l(i32 1, i32 2, ptr %0) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.stc2l(i32 immarg, i32 immarg, ptr) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp() #0 { # | entry: # | call void @llvm.arm.cdp(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @cdp2() #0 { # | entry: # | call void @llvm.arm.cdp2(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.cdp2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @mrc2() #0 { # | entry: # | %0 = call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) # | ret i32 %0 # | } # | # | ; Function Attrs: nounwind # | declare i32 @llvm.arm.mrc2(i32 immarg, i32 immarg, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_local void @mcr2(i32 noundef %a) #0 { # | entry: # | %a.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | call void @llvm.arm.mcr2(i32 15, i32 0, i32 %0, i32 13, i32 0, i32 3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.arm.mcr2(i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32 immarg) #2 # | # | ; Function Attrs: noinline nounwind # | define dso_lo # | ... # `---data was truncated (10240/15632) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055efc46c315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055efc46c00f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055efc46c389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f84c5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f84c598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f84c5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f84c591b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055efc4658e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055efc4658c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055efc463db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055efc42ed0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055efc42ecdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f84c591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f84c591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f84c591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055efc42eccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/builtins-arm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c (3223 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv1i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv1i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv2i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv2i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv4i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv4i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m4_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv8i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv8i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m8_tu( %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i32, ptr %rs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4au.nxv16i32.i32.i64( %0, %1, i32 %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.nxv16i32.i32.i64(, , i32, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32mf2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv1i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m1_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv2i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4au_vx_u32m2_tum( %vm, %vd, %vs2, i32 noundef signext %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %rs1.addr = alloca i32, align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i32 %rs1, ptr %rs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i32, ptr %rs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64( %1, %2, i32 %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4au.mask.nxv4i32.i32.i64(, , i32, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nou # | ... # `---data was truncated (10240/25034) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575a462315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575a46200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575a462389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f090c449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f090c4a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f090c449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f090c431507 abort ./stdlib/abort.c:85:3 # | #7 0x00005575a45b8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005575a45b8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005575a459db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575a424d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575a424cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f090c432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f090c4330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f090c4330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575a424ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c (3224 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zve32f -target-feature +zvfbfmin -target-feature +xsfvfbfexp16e -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv1bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv2bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv4bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv8bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv16bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m8( %vs2, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.sf.vfexp.nxv32bf16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv1bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16mf2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv2bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m1_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv4bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m2_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64( poison, %1, %0, i64 %2, i64 3) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vfexp.mask.nxv8bf16.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_sf_vfexp_v_bf16m4_m( %vm, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | # | ... # `---data was truncated (10240/12381) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056445358715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005644535840f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056445358789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7caf733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7caf78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7caf733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7caf71b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056445351ce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056445351cc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564453501b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005644531b10b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005644531b0dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7caf71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7caf71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7caf71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005644531b0cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c (3225 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_f16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e16_v_i16m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_ # | ... # `---data was truncated (10240/63061) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556765ce915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556765ce60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556765ce989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2999849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f29998a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2999849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2999831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556765c7ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556765c7ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556765c63b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005567659130b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556765912dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2999832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f29998330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f29998330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556765912cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c (3226 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_x_f_v_i16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16mf2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m1( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m2( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m4( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfcvt_rtz_xu_f_v_u16m8( %src, i64 noundef %vl) #0 { # | entry: # | %src.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %src, ptr %src.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %src.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfcvt.rtz # | ... # `---data was truncated (10240/58675) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a927dd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a927da0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a927dd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3ac5133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3ac518a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3ac5133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3ac511b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a92772e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a92772c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a92757b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a924070b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a92406dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3ac511cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3ac511d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3ac511d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a92406cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c (3227 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f68504615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f6850430f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f68504689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f4dc4e49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f4dc4ea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f4dc4e49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f4dc4e31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f684fdbe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f684fdbc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f684fc0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f684c700b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f684c6fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f4dc4e32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f4dc4e330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f4dc4e330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f684c6fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/cfi.ll (3228 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/cfi.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -thinlto-split-lto-unit -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/cfi.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/cfi.ll # | #0 0x000055baa946b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055baa94680f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055baa946b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9780933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f978098a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9780933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f978091b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055baa9400e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055baa9400c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055baa93e5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055baa90950b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055baa9094dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f978091cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f978091d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f978091d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055baa9094cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c (3229 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsm4r.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vsm4r_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsm4r.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare # | ... # `---data was truncated (10240/20139) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fe22ca115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fe22c9e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fe22ca189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1b6f81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1b6f8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1b6f81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1b6f803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fe22c36e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fe22c36c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fe22c1bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fe228cb0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fe228cadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1b6f804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1b6f8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1b6f8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fe228cacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c (3230 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_i64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv8i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_u64m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 8 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 4), i64 } @llvm.riscv.vlseg4ff.triscv.vector.tuple_nxv16i8_4t.i64.p0(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %3, i64 6) # | %5 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 4), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e64ff_v_f64m1x4_tum( %mask, target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 8 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store target("riscv.vector.tuple", # | ... # `---data was truncated (10240/40860) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005559a13fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005559a13f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005559a13fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007faee0849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007faee08a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007faee0849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007faee0831507 abort ./stdlib/abort.c:85:3 # | #7 0x00005559a1390e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005559a1390c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005559a1375b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005559a10250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005559a1024dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007faee0832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007faee08330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007faee08330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005559a1024cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c (3231 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32m1x5(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, i64 %1, i64 5) # | ret target("riscv.vector.tuple", , 5) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_f32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_i32m1x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vlseg5e32_v_u32mf2x5_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8 # | ... # `---data was truncated (10240/12059) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f3ee0cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f3ee0c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f3ee0cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6b5001bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6b500725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6b5001ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6b50003507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f3ee061e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f3ee061c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f3ee046b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f3edcf60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f3edcf5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6b50004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6b500050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6b500050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f3edcf5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c (3232 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -disable-O0-optnone -target-feature +zve64x -target-feature +zvfbfmin -target-feature +experimental-zvzip -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m1_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m2_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m4_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv16bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16m8_tu( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vpaire.nxv32bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf4_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load , ptr %vs1.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vpaire.mask.nxv1bf16.i64( %1, %2, %3, %0, i64 %4, i64 2) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vpaire.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vpaire_vv_bf16mf2_tum( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c (3233 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv1bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv2bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m1_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv4bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m2_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv8bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m4_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv16bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16m8_tu( %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0( %0, ptr %1, i64 %3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 2 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.nxv32bf16.i64.p0(, ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf4_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0( %1, ptr %2, %0, i64 %4, i64 2) # | %6 = extractvalue { , i64 } %5, 0 # | %7 = extractvalue { , i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vle16ff_v_bf16mf2_tum( %vm, %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64.p0(' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c (3234 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vx_i8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef signext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgt_vv_i8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgt.mask.nxv8i8.nxv8i8.i64(, , , , i # | ... # `---data was truncated (10240/63579) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005591a158215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005591a157f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005591a158289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7e57733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7e5778a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7e57733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7e5771b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005591a1517e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005591a1517c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005591a14fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005591a11ac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005591a11abdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7e5771cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7e5771d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7e5771d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005591a11abcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c (3235 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_f32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_i32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32mf2x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e32_v_u32m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562f2c87615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562f2c8730f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562f2c87689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8f07b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8f07b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8f07b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8f07b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562f2c80be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562f2c80bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562f2c7f0b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562f2c4a00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562f2c49fdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8f07b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8f07b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8f07b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562f2c49fcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c (3236 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4a.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4a_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load < # | ... # `---data was truncated (10240/14421) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005573f364b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005573f36480f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005573f364b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f25afe49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f25afea05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f25afe49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f25afe31507 abort ./stdlib/abort.c:85:3 # | #7 0x00005573f35e0e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005573f35e0c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005573f35c5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005573f32750b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005573f3274dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f25afe32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f25afe330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f25afe330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005573f3274cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c (3237 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv1bf16.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv2bf16.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv4bf16.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv8bf16.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64( %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.nxv16bf16.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf4_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv1bf16.nxv1f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16mf2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv2bf16.nxv2f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m1_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 2 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64( %1, %2, %0, i64 7, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvtbf16.f.f.w.mask.nxv4bf16.nxv4f32.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vfncvtbf16_f_f_w_bf16m2_tum( %vm, %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 2 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 2 # | store %vs2, ptr %vs2.addr, align 4 # | # | ... # `---data was truncated (10240/43478) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ccb834115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ccb833e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ccb834189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1496c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1496ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1496c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1496c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ccb82d6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ccb82d6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ccb82bbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ccb7f6b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ccb7f6add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1496c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1496c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1496c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ccb7f6acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c (3238 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr %0, i64 %1, i64 6) # | ret target("riscv.vector.tuple", , 8) %2 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_f64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_i64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e64_v_u64m1x8_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 8) poison, ptr %1, %0, i64 %2, i64 3, i64 6) # | ret target("riscv.vector.tuple", , 8) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558eb241a15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558eb24170f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558eb241a89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f0e0f733b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f0e0f78a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f0e0f733a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f0e0f71b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558eb23afe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558eb23afc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558eb2394b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558eb20440b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558eb2043dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f0e0f71cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f0e0f71d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f0e0f71d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558eb2043cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c (3239 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=sroa | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64-none-linux-gnu -target-feature +zve64d -target-feature +f -target-feature +d -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64-none-linux-gnu" # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <32 x i8> @llvm.vector.extract.v32i8.nxv8i8(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv8i8.v32i8(, <32 x i8>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <16 x i16> @llvm.vector.extract.v16i16.nxv4i16(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv4i16.v16i16(, <16 x i16>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <8 x i32> @llvm.vector.extract.v8i32.nxv2i32(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv2i32.v8i32(, <8 x i32>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_i64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare <4 x i64> @llvm.vector.extract.v4i64.nxv1i64(, i64 immarg) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) # | declare @llvm.vector.insert.nxv1i64.v4i64(, <4 x i64>, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %and = and <32 x i8> %0, %1 # | store <32 x i8> %and, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv8i8.v32i8( poison, <32 x i8> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u16( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <16 x i16>, align 8 # | %a.addr = alloca <16 x i16>, align 8 # | %b.addr = alloca <16 x i16>, align 8 # | %a = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %a.coerce, i64 0) # | %b = call <16 x i16> @llvm.vector.extract.v16i16.nxv4i16( %b.coerce, i64 0) # | store <16 x i16> %a, ptr %a.addr, align 8 # | store <16 x i16> %b, ptr %b.addr, align 8 # | %0 = load <16 x i16>, ptr %a.addr, align 8 # | %1 = load <16 x i16>, ptr %b.addr, align 8 # | %and = and <16 x i16> %0, %1 # | store <16 x i16> %and, ptr %retval, align 8 # | %2 = load <16 x i16>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv4i16.v16i16( poison, <16 x i16> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u32( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <8 x i32>, align 8 # | %a.addr = alloca <8 x i32>, align 8 # | %b.addr = alloca <8 x i32>, align 8 # | %a = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %a.coerce, i64 0) # | %b = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( %b.coerce, i64 0) # | store <8 x i32> %a, ptr %a.addr, align 8 # | store <8 x i32> %b, ptr %b.addr, align 8 # | %0 = load <8 x i32>, ptr %a.addr, align 8 # | %1 = load <8 x i32>, ptr %b.addr, align 8 # | %and = and <8 x i32> %0, %1 # | store <8 x i32> %and, ptr %retval, align 8 # | %2 = load <8 x i32>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv2i32.v8i32( poison, <8 x i32> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @and_u64( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <4 x i64>, align 8 # | %a.addr = alloca <4 x i64>, align 8 # | %b.addr = alloca <4 x i64>, align 8 # | %a = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %a.coerce, i64 0) # | %b = call <4 x i64> @llvm.vector.extract.v4i64.nxv1i64( %b.coerce, i64 0) # | store <4 x i64> %a, ptr %a.addr, align 8 # | store <4 x i64> %b, ptr %b.addr, align 8 # | %0 = load <4 x i64>, ptr %a.addr, align 8 # | %1 = load <4 x i64>, ptr %b.addr, align 8 # | %and = and <4 x i64> %0, %1 # | store <4 x i64> %and, ptr %retval, align 8 # | %2 = load <4 x i64>, ptr %retval, align 8 # | %cast.scalable = call @llvm.vector.insert.nxv1i64.v4i64( poison, <4 x i64> %2, i64 0) # | ret %cast.scalable # | } # | # | ; Function Attrs: noinline nounwind vscale_range(4,4) # | define dso_local @or_i8( noundef %a.coerce, noundef %b.coerce) #0 { # | entry: # | %retval = alloca <32 x i8>, align 8 # | %a.addr = alloca <32 x i8>, align 8 # | %b.addr = alloca <32 x i8>, align 8 # | %a = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %a.coerce, i64 0) # | %b = call <32 x i8> @llvm.vector.extract.v32i8.nxv8i8( %b.coerce, i64 0) # | store <32 x i8> %a, ptr %a.addr, align 8 # | store <32 x i8> %b, ptr %b.addr, align 8 # | %0 = load <32 x i8>, ptr %a.addr, align 8 # | %1 = load <32 x i8>, ptr %b.addr, align 8 # | %or = or <32 x i8> %0, %1 # | store <32 x i8> %or, ptr %retval, align 8 # | %2 = load <32 x i8>, ptr %retval, align 8 # | %cast.scalable = call ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-vls-bitwise-ops.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c (3240 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vluxseg7ei16_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i16. # | ... # `---data was truncated (10240/62079) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560b3d3c615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560b3d3c30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560b3d3c689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc008b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc008b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc008b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc008b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560b3d35be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560b3d35bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560b3d340b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560b3cff00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560b3cfefdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc008b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc008b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc008b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560b3cfefcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/distributed-thin-lto/basic.ll (3241 of 27911) ******************** TEST 'Clang :: CodeGen/distributed-thin-lto/basic.ll' FAILED ******************** Exit Code: -6 Command Output (stdout): -- # RUN: at line 5 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -thinlto-bc -o /usr/local/google/home/thakis/src/llvm-project/out/gn/obj/clang/test/CodeGen/distributed-thin-lto/Output/basic.ll.tmp.o /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/distributed-thin-lto/basic.ll # | #0 0x000055954ed3515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055954ed320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055954ed3589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2f0af05b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2f0af5c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2f0af05a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2f0aeed507 abort ./stdlib/abort.c:85:3 # | #7 0x000055954eccae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055954eccac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055954ecafb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055954e95f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055954e95edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2f0aeeefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2f0aeef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2f0aeef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055954e95ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c (3242 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tu(target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf2x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16m1x6_tum( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 6) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 6), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 6) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlsseg6e16_v_bf16mf4x6_tumu( %vm, target("riscv.vector.tuple", , 6) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055871b95115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055871b94e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055871b95189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f2d55b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f2d55b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f2d55b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f2d55b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055871b8e6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055871b8e6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055871b8cbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055871b57b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055871b57add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f2d55b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f2d55b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f2d55b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055871b57acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c (3243 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m1_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv4i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m2_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m4_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(4,1024) # | define dso_local @test_sf_vqmaccu_4x8x4_i32m8_tu( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 2) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(4,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccqoq,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl256b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e414e0115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e414dfe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e414e0189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f93e1649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f93e16a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f93e1649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f93e1631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e414d96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e414d96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e414d7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e414a2b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e414a2add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f93e1632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f93e16330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f93e16330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e414a2acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c (3244 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei64_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005595e2a9615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005595e2a930f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005595e2a9689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f340bb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f340bb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f340bb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f340bb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x00005595e2a2be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005595e2a2bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005595e2a10b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005595e26c00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005595e26bfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f340bb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f340bb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f340bb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005595e26bfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c (3245 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m1x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16m2x4_tu(target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf4x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vloxseg4ei32_v_bf16mf2x4_tum( %vm, target("riscv.vector.tuple", , 4) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 4) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 4) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e226f1015b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e226f0d0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e226f1089b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ffbe1c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ffbe1ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ffbe1c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ffbe1c31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e226ea5e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e226ea5c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e226e8ab29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e226b3a0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e226b39dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ffbe1c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ffbe1c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ffbe1c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e226b39cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c (3246 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.nxv1bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf4( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv1bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16mf2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.nxv2bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16mf2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv2bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.nxv4bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m1( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv4bf16.bf16.i64(, bfloat, , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vv_bf16m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 7, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfnmacc.nxv8bf16.nxv8bf16.i64(, , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfnmacc_vf_bf16m2( %vd, bfloat noundef %rs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 2 # | %rs1.addr = alloca bfloat, align 2 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 2 # | store bfloat %rs1, ptr %rs1.addr, align 2 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 2 # | %1 = load bfloat, ptr %rs1.addr, align 2 # | %2 = load , ptr %vs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfnmacc.nxv8bf16.bf16.i64( %0, bfloat %1, %2, i64 7, i64 %3, i64 3) # | ... # `---data was truncated (10240/34438) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562d1499215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562d1498f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562d1499289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3d4d049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f3d4d0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3d4d049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3d4d031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562d14927e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562d14927c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562d1490cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562d145bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562d145bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3d4d032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f3d4d0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f3d4d0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562d145bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c (3247 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i64.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei64_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", < # | ... # `---data was truncated (10240/25817) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c7d058f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c7d058c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c7d058f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb6bc81bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb6bc8725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb6bc81ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb6bc803507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c7d0524e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c7d0524c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c7d0509b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c7d01b90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c7d01b8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb6bc804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb6bc8050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb6bc8050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c7d01b8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c (3248 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf4_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf4_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv1bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16mf2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16mf2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv2bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m1_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m1_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64( %0, %1, bfloat %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv4bf16.bf16.i64(, , bfloat, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vv_bf16m2_tu( %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load , ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64( %0, %1, %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfsgnjn.nxv8bf16.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfsgnjn_vf_bf16m2_tu( %maskedoff, %op1, bfloat noundef %op2, i64 noundef %vl) #0 { # | entry: # | %maskedoff.addr = alloca , align 2 # | %op1.addr = alloca , align 2 # | %op2.addr = alloca bfloat, align 2 # | %vl.addr = alloca i64, align 8 # | store %maskedoff, ptr %maskedoff.addr, align 2 # | store %op1, ptr %op1.addr, align 2 # | store bfloat %op2, ptr %op2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %maskedoff.addr, align 2 # | %1 = load , ptr %op1.addr, align 2 # | %2 = load bfloat, ptr %op2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vfsgnjn.nxv8bf16.bf16.i64( %0, %1, bfloat %2, # | ... # `---data was truncated (10240/65194) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005637aed8115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005637aed7e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005637aed8189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f603b649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f603b6a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f603b649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f603b631507 abort ./stdlib/abort.c:85:3 # | #7 0x00005637aed16e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005637aed16c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005637aecfbb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005637ae9ab0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005637ae9aadd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f603b632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f603b6330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f603b6330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005637ae9aacc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c (3249 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv64i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv64i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv32i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv32i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv16i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv16i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv8i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv8i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b16( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv4i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv4i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b32( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv2i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv2i1.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmnor_mm_b64( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load , ptr %op2.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vmnor.nxv1i1.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmnor.nxv1i1.i64(, , i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055b91e30515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055b91e3020f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055b91e30589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f406f249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f406f2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f406f249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f406f231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055b91e29ae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055b91e29ac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055b91e27fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055b91df2f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055b91df2edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f406f232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f406f2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f406f2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055b91df2ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c (3250 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m2x3(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg3ei8_v_bf16m1x3_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 3) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 3), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 3) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 3), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i8.nxv4i1.i64(target("riscv.vector.tuple", , 3) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosy # | ... # `---data was truncated (10240/12666) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000562a474fb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000562a474f80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000562a474fb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9646333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f964638a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9646333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f964631b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000562a47490e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000562a47490c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000562a47475b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000562a471250b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000562a47124dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f964631cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f964631d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f964631d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000562a47124cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c (3251 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv2i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %rs2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %rs2, ptr %rs2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %rs2.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8) %1, ptr %2, i64 %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.i64.nxv4i1(target("riscv.vector.tuple", , 8), ptr captures(none), i64, , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlsseg8e16_v_bf16mf4x8_tumu( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, i64 noundef %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | ... # `---data was truncated (10240/18506) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000563c5be1515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000563c5be120f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000563c5be1589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc1f9133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc1f918a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc1f9133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc1f911b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000563c5bdaae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000563c5bdaac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000563c5bd8fb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000563c5ba3f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000563c5ba3edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc1f911cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc1f911d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc1f911d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000563c5ba3ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c (3252 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei16_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i16.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e6ea2f915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e6ea2f60f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e6ea2f989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff673f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff673f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff673f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff673f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e6ea28ee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e6ea28ec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e6ea273b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e6e9f230b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e6e9f22dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff673f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff673f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff673f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e6e9f22cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c (3253 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_f16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16mf2x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_i16m1x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_u16mf4x8_tu(target("riscv.vector.tuple", , 8) %maskedoff_tuple, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %base.addr = alloca ptr, ali # | ... # `---data was truncated (10240/60543) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005615a7e3115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005615a7e2e0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005615a7e3189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fcce9305b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fcce935c5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fcce9305a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fcce92ed507 abort ./stdlib/abort.c:85:3 # | #7 0x00005615a7dc6e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x00005615a7dc6c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005615a7dabb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005615a7a5b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005615a7a5add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fcce92eefba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fcce92ef0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fcce92ef0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005615a7a5acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c (3254 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_i32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32mf2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m1x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_u32m2x4(ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, i64 %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlsseg4e32_v_f32mf2x4_m( %mask, ptr noundef %base, i64 noundef %bstride, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 4) poison, ptr %1, i64 %2, %0, i64 %3, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlsseg # | ... # `---data was truncated (10240/20483) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x00005575155cc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005575155c90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x00005575155cc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f3284049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f32840a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f3284049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f3284031507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557515561e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557515561c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557515546b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x00005575151f60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x00005575151f5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f3284032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f32840330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f32840330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x00005575151f5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c (3255 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m1x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 4) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vluxseg4ei16_v_bf16m2x4_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, # | ... # `---data was truncated (10240/11871) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558506f4715b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558506f440f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558506f4789b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f480cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f480cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f480cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f480cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558506edce2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558506edcc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558506ec1b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558506b710b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558506b70dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f480cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f480cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f480cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558506b70cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c (3256 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f16m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32mf2x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f32m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 5) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_f64m1x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 6) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf8x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv1i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 7) @test_vloxseg7ei64_v_i8mf4x7(ptr noundef %base, %bindex, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bindex.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store %bindex, ptr %bindex.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load , ptr %bindex.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) poison, ptr %0, %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 7) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv2i64.i64(targ # | ... # `---data was truncated (10240/62071) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f4211fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f4211fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f4211fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1962449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f19624a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1962449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1962431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f421193e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f421193c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f421178b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f420e280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f420e27dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1962432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f19624330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f19624330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f420e27cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c (3257 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv2i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv4i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8) %0, ptr %1, i64 %3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.triscv.vector.tuple_nxv8i8_8t.i64.p0(target("riscv.vector.tuple", , 8), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv2i8_8t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8) %1, ptr %2, %0, i64 %4, i64 2, i64 4) # | %6 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 0 # | %7 = extractvalue { target("riscv.vector.tuple", , 8), i64 } %5, 1 # | store i64 %7, ptr %3, align 8 # | ret target("riscv.vector.tuple", , 8) %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 8), i64 } @llvm.riscv.vlseg8ff.mask.triscv.vector.tuple_nxv4i8_8t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vlseg8e16ff_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load ptr, ptr %new_vl.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call { targ # | ... # `---data was truncated (10240/21111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a4830d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a4830a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a4830d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc988849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc9888a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc988849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc988831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a482a2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a482a2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a48287b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a47f370b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a47f36dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc988832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc9888330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc9888330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a47f36cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c (3258 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4(ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv2i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m1x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg4e16_v_bf16m2x4_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 4) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 4) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 4), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwin # | ... # `---data was truncated (10240/10798) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c4a317b15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c4a31780f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c4a317b89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8250d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f8250d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8250d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8250d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c4a3110e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c4a3110c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c4a30f5b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c4a2da50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c4a2da4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8250d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f8250d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f8250d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c4a2da4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c (3259 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei16_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f61a6bc15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f61a6b90f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f61a6bc89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa580649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa5806a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa580649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa580631507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f61a651e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f61a651c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f61a636b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f61a2e60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f61a2e5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa580632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa5806330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa5806330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f61a2e5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c (3260 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m1x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m2x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16m4x2(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 1 # | %2 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i8.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf4x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i8.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg2ei8_v_bf16mf2x2_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 2) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 1 # | %vs3.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load target("riscv.vector.tuple", , 2), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i8.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , # | ... # `---data was truncated (10240/15607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000555cdbc2315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000555cdbc200f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000555cdbc2389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fdd0901bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fdd090725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fdd0901ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fdd09003507 abort ./stdlib/abort.c:85:3 # | #7 0x0000555cdbbb8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000555cdbbb8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000555cdbb9db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000555cdb84d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000555cdb84cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fdd09004fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fdd090050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fdd090050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000555cdb84ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c (3261 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_i16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf4x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16mf2x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_u16m1x6(ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg6e16_v_f16mf4x6_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 2 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 6) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsse # | ... # `---data was truncated (10240/20441) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000557b4b9d415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000557b4b9d10f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000557b4b9d489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb4b5933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb4b598a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb4b5933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb4b591b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000557b4b969e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000557b4b969c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000557b4b94eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000557b4b5fe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000557b4b5fddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb4b591cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb4b591d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb4b591d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000557b4b5fdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c (3262 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tu(target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 8) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf4x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv2i8_8t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16mf2x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 8), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 8) @test_vluxseg8ei32_v_bf16m1x8_tum( %vm, target("riscv.vector.tuple", , 8) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 8), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 8) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 8), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 8) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 8) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv4i32.nx # | ... # `---data was truncated (10240/19590) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056258d5bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056258d5ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056258d5bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f002a049b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f002a0a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f002a049a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f002a031507 abort ./stdlib/abort.c:85:3 # | #7 0x000056258d552e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056258d552c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056258d537b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056258d1e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056258d1e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f002a032fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f002a0330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f002a0330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056258d1e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c (3263 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5(ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) %1, ptr %0, i64 %2, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_f64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_i64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsseg5e64_v_u64m1x5_m( %mask, ptr noundef %base, target("riscv.vector.tuple", , 5) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 5), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store target("riscv.vector.tuple", , 5) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 5), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 5) %2, ptr %1, %0, i64 %3, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055fb337bd15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055fb337ba0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055fb337bd89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f14bfb33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f14bfb8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f14bfb33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f14bfb1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055fb33752e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055fb33752c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055fb33737b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055fb333e70b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055fb333e6dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f14bfb1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f14bfb1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f14bfb1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055fb333e6cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c (3264 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv16i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 2) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %0, i64 %3, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16_v_bf16m1x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, i64 nou # | ... # `---data was truncated (10240/27442) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055dd87de215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055dd87ddf0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055dd87de289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1c23449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1c234a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1c23449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1c23431507 abort ./stdlib/abort.c:85:3 # | #7 0x000055dd87d77e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055dd87d77c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055dd87d5cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055dd87a0c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055dd87a0bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1c23432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1c234330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1c234330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055dd87a0bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c (3265 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %2, ptr %0, i64 %1, i64 %3, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_f64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6), ptr captures(none), i64, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_i64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg6e64_v_u64m1x6_m( %mask, ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 6) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 6) %v_tuple, ptr %v_tuple.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %bstride.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 6), ptr %v_tuple.addr, align 8 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", , 6) %3, ptr %1, i64 %2, %0, i64 %4, i64 6) # | ret void # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvfhmin1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000565005fb615b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000565005fb30f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000565005fb689b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1ed5c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1ed5ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1ed5c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1ed5c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000565005f4be2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000565005f4bc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000565005f30b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000565005be00b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000565005bdfdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1ed5c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1ed5c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1ed5c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000565005bdfcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vornq.c (3266 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vornq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = xor <16 x i8> %1, splat (i8 -1) # | %3 = or <16 x i8> %0, %2 # | ret <16 x i8> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = xor <8 x i16> %1, splat (i16 -1) # | %3 = or <8 x i16> %0, %2 # | ret <8 x i16> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = xor <4 x i32> %1, splat (i32 -1) # | %3 = or <4 x i32> %0, %2 # | ret <4 x i32> %3 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = xor <4 x i32> %3, splat (i32 -1) # | %5 = or <4 x i32> %1, %4 # | %6 = bitcast <4 x i32> %5 to <4 x float> # | ret <4 x float> %6 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> noundef %inactive, <8 x half> noundef %a, <8 x half> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x half>, align 8 # | %a.addr = alloca <8 x half>, align 8 # | %b.addr = alloca <8 x half>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x half> %inactive, ptr %inactive.addr, align 8 # | store <8 x half> %a, ptr %a.addr, align 8 # | store <8 x half> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x half>, ptr %a.addr, align 8 # | %1 = bitcast <8 x half> %0 to <8 x i16> # | %2 = load <8 x half>, ptr %b.addr, align 8 # | %3 = bitcast <8 x half> %2 to <8 x i16> # | %4 = load i16, ptr %p.addr, align 2 # | %5 = zext i16 %4 to i32 # | %6 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %5) # | %7 = load <8 x half>, ptr %inactive.addr, align 8 # | %8 = bitcast <8 x half> %7 to <8 x i16> # | %9 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %1, <8 x i16> %3, <8 x i1> %6, <8 x i16> %8) # | %10 = bitcast <8 x i16> %9 to <8 x half> # | ret <8 x half> %10 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> noundef %a, <4 x float> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x float>, align 8 # | %b.addr = alloca <4 x float>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x float> %a, ptr %a.addr, align 8 # | store <4 x float> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x float>, ptr %a.addr, align 8 # | %1 = bitcast <4 x float> %0 to <4 x i32> # | %2 = load <4 x float>, ptr %b.addr, align 8 # | %3 = bitcast <4 x float> %2 to <4 x i32> # | %4 = load i16, ptr %p.addr, al # | ... # `---data was truncated (10240/11056) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055659dabb15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055659dab80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055659dabb89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1230f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1230f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1230f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1230f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055659da50e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055659da50c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055659da35b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055659d6e50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055659d6e4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1230f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1230f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1230f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055659d6e4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vornq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c (3267 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_f32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_i32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32mf2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m1x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e32_v_u32m2x3_m( %mask, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv16i8_3t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %0, i64 %2, i64 3, i64 5) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zfh,+zfhmin,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvfh,+zvfhmin,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0 # | ... # `---data was truncated (10240/10425) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a61e01815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a61e0150f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a61e01889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f5e2e933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f5e2e98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f5e2e933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f5e2e91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a61dfade2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a61dfadc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a61df92b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a61dc420b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a61dc41dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f5e2e91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f5e2e91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f5e2e91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a61dc41cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c (3268 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf8x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv1i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf4x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8mf2x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_u8m1x6_tu(target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 6), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 6) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 6), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vlseg6e8_v_i8mf8x6_tum( %mas # | ... # `---data was truncated (10240/43111) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055abce93d15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055abce93a0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055abce93d89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd2ca933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd2ca98a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd2ca933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd2ca91b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055abce8d2e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055abce8d2c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055abce8b7b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055abce5670b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055abce566dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd2ca91cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd2ca91d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd2ca91d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055abce566cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c (3269 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvfbfa -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf4_i8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16mf2_i8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m1_i8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m2_i8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m4_i8m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_x_f_w_bf16m8_i8m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf4_u8mf8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16mf2_u8mf4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m1_u8mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64( %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4bf16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfncvt_rtz_xu_f_w_bf16m2_u8m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.v # | ... # `---data was truncated (10240/53192) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056345f34915b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056345f3460f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056345f34989b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9754649b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f97546a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9754649a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9754631507 abort ./stdlib/abort.c:85:3 # | #7 0x000056345f2dee2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056345f2dec76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056345f2c3b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056345ef730b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056345ef72dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9754632fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f97546330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f97546330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056345ef72cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c (3270 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv1bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv2bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv4bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m2( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv8bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m4( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv16bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m8( %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vs2.addr, align 2 # | %1 = load , ptr %vs1.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.nxv32bf16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf4_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16mf2_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load , ptr %vs1.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64( poison, %1, %2, %0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local @test_vrgatherei16_vv_bf16m1_m( %vm, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vs2.addr = alloca , align 2 # | %vs1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vs2, ptr %vs2.addr, align 2 # | store %vs1, ptr %vs1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vs2.addr, align 2 # | %2 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c (3271 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_f16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf4x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16mf2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m1x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e16_v_i16m2x4_tu(target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 4), align 2 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 4) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 2 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 4), ptr %maskedoff_tuple.addr, align 2 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) %0, ptr %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 4) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 4) @test_vlseg4e1 # | ... # `---data was truncated (10240/63053) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561a3087815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561a308750f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561a3087889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fc06f333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fc06f38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fc06f333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fc06f31b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561a3080de2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561a3080dc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561a307f2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561a304a20b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561a304a1dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fc06f31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fc06f31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fc06f31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561a304a1cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c (3272 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei32_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d0f782815b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d0f78250f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d0f782889b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fa20cd33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fa20cd8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fa20cd33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fa20cd1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d0f77bde2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d0f77bdc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d0f77a2b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d0f74520b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d0f7451dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fa20cd1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fa20cd1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fa20cd1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d0f7451cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c (3273 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv32f16.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv32f16.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv2f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv2f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv4f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv4f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv8f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv8f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv16f32.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv16f32.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfrec7_v_f64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vfrec7.nxv1f64.i64( poison, %0, i64 7, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfrec7.nxv1f64.i64(, , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local # | ... # `---data was truncated (10240/51412) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560396c0115b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560396bfe0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560396c0189b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb950133b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb95018a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb950133a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb95011b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560396b96e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560396b96c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560396b7bb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056039682b0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056039682add3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb95011cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb95011d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb95011d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056039682acc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c (3274 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16mf2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m1_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m2_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m4_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f16m8_f32m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32mf2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m1_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vfwredosum_vs_f32m2_f64m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 4 # | %scalar.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 4 # | store %scalar, ptr %scalar.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 4 # | %1 = load , ptr %scalar.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32.i64( poison, %0, %1, i64 7, i64 %2) # | ret # | ... # `---data was truncated (10240/50516) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055d2bbbee15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055d2bbbeb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055d2bbbee89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8210849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f82108a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8210849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f8210831507 abort ./stdlib/abort.c:85:3 # | #7 0x000055d2bbb83e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055d2bbb83c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055d2bbb68b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055d2bb8180b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055d2bb817dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f8210832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f82108330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f82108330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055d2bb817cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c (3275 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_i8m2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf8x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf4x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8mf2x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %v_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store target("riscv.vector.tuple", , 3) %v_tuple, ptr %v_tuple.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 3), ptr %v_tuple.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %2, ptr %0, i64 %1, i64 %3, i64 3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vssseg3e8_v_u8m1x3(ptr noundef %base, i64 noundef %bstride, target("riscv.vector.tuple", , 3) %v_tuple, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, a # | ... # `---data was truncated (10240/26721) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055f236d9215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055f236d8f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055f236d9289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff3eb249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff3eb2a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff3eb249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff3eb231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055f236d27e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055f236d27c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055f236d0cb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055f2369bc0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055f2369bbdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff3eb232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff3eb2330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff3eb2330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055f2369bbcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c (3276 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv1i32.nxv1i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv2i32.nxv2i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv4i32.nxv4i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m4( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv8i32.nxv8i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m8( %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load , ptr %vs1.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.nxv16i32.nxv16i32.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32mf2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv1i32.nxv1i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m1_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load , ptr %vd.addr, align 4 # | %2 = load , ptr %vs2.addr, align 4 # | %3 = load , ptr %vs1.addr, align 4 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64( %1, %2, %3, %0, i64 %4, i64 3) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vdot4asu.mask.nxv2i32.nxv2i32.i64(, , , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vdot4asu_vv_i32m2_m( %vm, %vd, %vs2, %vs1, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vs1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store %vs1, ptr %vs1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c (3277 of 27911) ******************** TEST 'Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -emit-llvm -o - /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c" # | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" # | target triple = "thumbv8.1m.main-none-none-eabi" # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %1, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8>, <16 x i8>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %1, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16>, <8 x i16>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = call <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32> %0, <4 x i32> %1, i32 1) # | ret <4 x i32> %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.vhadd.v4i32(<4 x i32>, <4 x i32>, i32) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_m_s8(<16 x i8> noundef %inactive, <16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <16 x i8>, align 8 # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %inactive, ptr %inactive.addr, align 8 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = load <16 x i8>, ptr %inactive.addr, align 8 # | %6 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 0, <16 x i1> %4, <16 x i8> %5) # | ret <16 x i8> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_m_u16(<8 x i16> noundef %inactive, <8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <8 x i16>, align 8 # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %inactive, ptr %inactive.addr, align 8 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = load <8 x i16>, ptr %inactive.addr, align 8 # | %6 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 1, <8 x i1> %4, <8 x i16> %5) # | ret <8 x i16> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_m_s32(<4 x i32> noundef %inactive, <4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %inactive.addr = alloca <4 x i32>, align 8 # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %inactive, ptr %inactive.addr, align 8 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = load <4 x i32>, ptr %inactive.addr, align 8 # | %6 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 0, <4 x i1> %4, <4 x i32> %5) # | ret <4 x i32> %6 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca <16 x i8>, align 8 # | %p.addr = alloca i16, align 2 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store <16 x i8> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load <16 x i8>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %3) # | %5 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %0, <16 x i8> %1, i32 1, <16 x i1> %4, <16 x i8> undef) # | ret <16 x i8> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> noundef %a, <8 x i16> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca <8 x i16>, align 8 # | %p.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store <8 x i16> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load <8 x i16>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3) # | %5 = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, i32 0, <8 x i1> %4, <8 x i16> undef) # | ret <8 x i16> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> noundef %a, <4 x i32> noundef %b, i16 noundef zeroext %p) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca <4 x i32>, align 8 # | %p.addr = alloca i16, align 2 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store <4 x i32> %b, ptr %b.addr, align 8 # | store i16 %p, ptr %p.addr, align 2 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load <4 x i32>, ptr %b.addr, align 8 # | %2 = load i16, ptr %p.addr, align 2 # | %3 = zext i16 %2 to i32 # | %4 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %3) # | %5 = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, i32 1, <4 x i1> %4, <4 x i32> undef) # | ret <4 x i32> %5 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <16 x i8> @test_vhaddq_n_u8(<16 x i8> noundef %a, i8 noundef zeroext %b) #0 { # | entry: # | %a.addr = alloca <16 x i8>, align 8 # | %b.addr = alloca i8, align 1 # | store <16 x i8> %a, ptr %a.addr, align 8 # | store i8 %b, ptr %b.addr, align 1 # | %0 = load <16 x i8>, ptr %a.addr, align 8 # | %1 = load i8, ptr %b.addr, align 1 # | %.splatinsert = insertelement <16 x i8> poison, i8 %1, i64 0 # | %.splat = shufflevector <16 x i8> %.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer # | %2 = call <16 x i8> @llvm.arm.mve.vhadd.v16i8(<16 x i8> %0, <16 x i8> %.splat, i32 1) # | ret <16 x i8> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <8 x i16> @test_vhaddq_n_s16(<8 x i16> noundef %a, i16 noundef signext %b) #0 { # | entry: # | %a.addr = alloca <8 x i16>, align 8 # | %b.addr = alloca i16, align 2 # | store <8 x i16> %a, ptr %a.addr, align 8 # | store i16 %b, ptr %b.addr, align 2 # | %0 = load <8 x i16>, ptr %a.addr, align 8 # | %1 = load i16, ptr %b.addr, align 2 # | %.splatinsert = insertelement <8 x i16> poison, i16 %1, i64 0 # | %.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer # | %2 = call <8 x i16> @llvm.arm.mve.vhadd.v8i16(<8 x i16> %0, <8 x i16> %.splat, i32 0) # | ret <8 x i16> %2 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local arm_aapcs_vfpcc <4 x i32> @test_vhaddq_n_u32(<4 x i32> noundef %a, i32 noundef %b) #0 { # | entry: # | %a.addr = alloca <4 x i32>, align 8 # | %b.addr = alloca i32, align 4 # | store <4 x i32> %a, ptr %a.addr, align 8 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load <4 x i32>, ptr %a.addr, align 8 # | %1 = load i32, ptr %b.addr, align 4 # | %.splatinsert = insertelement <4 x i32> poison, i32 %1, i64 0 # | %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> # | ... # `---data was truncated (10240/16951) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055e0f0d1315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055e0f0d100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055e0f0d1389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f7a73f33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f7a73f8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f7a73f33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f7a73f1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055e0f0ca8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055e0f0ca8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055e0f0c8db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055e0f093d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055e0f093cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f7a73f1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f7a73f1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f7a73f1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055e0f093ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c (3278 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv16i8_3t.p0.nxv8i32.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf4x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv2i8_3t.p0.nxv1i32.nxv1i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16mf2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv2i32.nxv2i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m1x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 4 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 3) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv4i32.nxv4i1.i64(target("riscv.vector.tuple", , 3), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vluxseg3ei32_v_bf16m2x3_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm # | ... # `---data was truncated (10240/11863) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056013009415b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x00005601300910f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056013009489b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9f33333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f9f3338a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9f33333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9f3331b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560130029e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560130029c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056013000eb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056012fcbe0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056012fcbddd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9f3331cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f9f3331d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f9f3331d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056012fcbdcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c (3279 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m1x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv8i8_2t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m2x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv16i8_2t.p0.nxv8i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16m4x2_tu(target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2) %0, ptr %1, %2, i64 %3, i64 4) # | ret target("riscv.vector.tuple", , 2) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.p0.nxv16i16.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf4x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %vd.addr = alloca target("riscv.vector.tuple", , 2), align 2 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store target("riscv.vector.tuple", , 2) %vd, ptr %vd.addr, align 2 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load target("riscv.vector.tuple", , 2), ptr %vd.addr, align 2 # | %2 = load ptr, ptr %rs1.addr, align 8 # | %3 = load , ptr %rs2.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2) %1, ptr %2, %3, %0, i64 %4, i64 2, i64 4) # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv2i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 2), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vloxseg2ei16_v_bf16mf2x2_tum( %vm, target("riscv.vector.tuple", , 2) %vd, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c (3280 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m1( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m2( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m4( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(, , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vqmaccsu_2x8x2_i32m8( %vd, %vs1, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs1.addr = alloca , align 1 # | %vs2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs1, ptr %vs1.addr, align 1 # | store %vs2, ptr %vs2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs1.addr, align 1 # | %2 = load , ptr %vs2.addr, align 1 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64( %0, %1, %2, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(, , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+xsfvqmaccdod,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056377c18c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056377c1890f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056377c18c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6d0d333b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6d0d38a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6d0d333a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6d0d31b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056377c121e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056377c121c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056377c106b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056377bdb60b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056377bdb5dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6d0d31cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6d0d31d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6d0d31d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056377bdb5cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c (3281 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b1(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv64i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv64i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b2(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv32i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv32i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b4(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv16i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv16i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b8(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv8i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv8i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b16(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv4i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv4i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b32(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv2i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv2i1.p0.i64(ptr captures(none), i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vlm_v_b64(ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vlm.nxv1i1.p0.i64(ptr %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare @llvm.riscv.vlm.nxv1i1.p0.i64(ptr captures(none), i64) #1 # | # | attributes #0 = { noinline nounwind vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64d"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000556fe723515b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000556fe72320f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000556fe723589b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1985d33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1985d8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1985d33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1985d1b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000556fe71cae2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000556fe71cac76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000556fe71afb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000556fe6e5f0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000556fe6e5edd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1985d1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1985d1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1985d1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000556fe6e5ecc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c (3282 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsgtu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsgtu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c (3283 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zvl512b -target-feature +zvbb -target-feature +zvbc -target-feature +zvkb -target-feature +zvkg -target-feature +zvkned -target-feature +zvknhb -target-feature +zvksed -target-feature +zvksh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32mf2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv1i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv8i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32mf2_u32m8_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv16i32.nxv1i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vv_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vv.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vv.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m1_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv2i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m2_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vaesef.vs.nxv4i32.nxv2i32.i64(, , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(8,1024) # | define dso_local @test_vaesef_vs_u32m1_u32m4_tu( %vd, %vs2, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 4 # | %vs2.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 4 # | store %vs2, ptr %vs2.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 4 # | %1 = load , ptr %vs2.addr, align 4 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vaesef.vs.nxv8i32.nxv2i32.i64( %0, %1, i64 %2, i64 2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind w # | ... # `---data was truncated (10240/20198) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055a0c06fa15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055a0c06f70f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055a0c06fa89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f85e9b33b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f85e9b8a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f85e9b33a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f85e9b1b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055a0c068fe2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055a0c068fc76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055a0c0674b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055a0c03240b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055a0c0323dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f85e9b1cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f85e9b1d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f85e9b1d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055a0c0323cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c (3284 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 6) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf4x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv2i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16mf2x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 6) @test_vloxseg6ei16_v_bf16m1x6_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 6) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 6), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055cc866ff15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055cc866fc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055cc866ff89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007ff498933b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007ff49898a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007ff498933a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007ff49891b507 abort ./stdlib/abort.c:85:3 # | #7 0x000055cc86694e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055cc86694c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055cc86679b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055cc863290b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055cc86328dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007ff49891cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007ff49891d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007ff49891d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055cc86328cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c (3285 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7(ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7) %2, ptr %0, %1, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf4x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i64.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16mf2x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i64.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsoxseg7ei64_v_bf16m1x7_m( %vm, ptr noundef %rs1, %vs2, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs2.addr = alloca , align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %vs2.addr, align 8 # | %3 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %4 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7) %3, ptr %1, %2, %0, i64 %4, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i64.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000561e6715c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000561e671590f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000561e6715c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fbb99c49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fbb99ca05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fbb99c49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fbb99c31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561e670f1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561e670f1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000561e670d6b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561e66d860b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561e66d85dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fbb99c32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fbb99c330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fbb99c330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561e66d85cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c (3286 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i16.nxv1i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i16.nxv1i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i16.nxv2i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i16.nxv2i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i16.nxv4i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i16.nxv4i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i16.nxv8i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i16.nxv8i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i16.nxv16i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i16.nxv16i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u16m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 1 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv32i16.nxv32i8.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv32i16.nxv32i8.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32mf2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i32.nxv1i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i32.nxv1i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv2i32.nxv2i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv2i32.nxv2i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv4i32.nxv4i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv4i32.nxv4i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m4( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv8i32.nxv8i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv8i32.nxv8i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u32m8( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 2 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv16i32.nxv16i16.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv16i32.nxv16i16.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m1( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 4 # | %1 = load i64, ptr %vl.addr, align 8 # | %2 = call @llvm.riscv.vzext.nxv1i64.nxv1i32.i64( poison, %0, i64 %1) # | ret %2 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vzext_vf2_u64m2( %op1, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 4 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 4 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , # | ... # `---data was truncated (10240/28571) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564020f2e15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564020f2b0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564020f2e89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb57981bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb5798725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb57981ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb579803507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564020ec3e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564020ec3c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564020ea8b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564020b580b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564020b57dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb579804fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb5798050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb5798050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564020b57cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c (3287 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv1i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv2i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8mf2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv4i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m1_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv8i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m2_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv16i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m4_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv32i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i8m8_i8m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 1 # | %scalar.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 1 # | store %scalar, ptr %scalar.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 1 # | %1 = load , ptr %scalar.addr, align 1 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv8i8.nxv64i8.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf4_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv1i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16mf2_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vector.addr, align 2 # | %1 = load , ptr %scalar.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64( poison, %0, %1, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vredmin.nxv4i16.nxv2i16.i64(, , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vredmin_vs_i16m1_i16m1( %vector, %scalar, i64 noundef %vl) #0 { # | entry: # | %vector.addr = alloca , align 2 # | %scalar.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vector, ptr %vector.addr, align 2 # | store %scalar, ptr %scalar.addr, align # | ... # `---data was truncated (10240/52607) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000564751f8f15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000564751f8c0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000564751f8f89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f6769a49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f6769aa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f6769a49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f6769a31507 abort ./stdlib/abort.c:85:3 # | #7 0x0000564751f24e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000564751f24c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000564751f09b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000564751bb90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000564751bb8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f6769a32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f6769a330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f6769a330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000564751bb8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c (3288 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m1_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_f16m8_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf4_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractvalue { , i64 } %4, 0 # | %6 = extractvalue { , i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64.p0(, ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vle16ff_v_i16mf2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64.p0( poison, ptr %1, %0, i64 %3, i64 3) # | %5 = extractva # | ... # `---data was truncated (10240/22708) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055af75b7215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055af75b6f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055af75b7289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007efd4aa49b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007efd4aaa05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007efd4aa49a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007efd4aa31507 abort ./stdlib/abort.c:85:3 # | #7 0x000055af75b07e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055af75b07c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055af75aecb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055af7579c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055af7579bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007efd4aa32fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007efd4aa330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007efd4aa330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055af7579bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c (3289 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5(ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load , ptr %rs2.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5) poison, ptr %0, %1, i64 %2, i64 4) # | ret target("riscv.vector.tuple", , 5) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf4x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv2i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16mf2x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv2i16.nxv2i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local target("riscv.vector.tuple", , 5) @test_vloxseg5ei16_v_bf16m1x5_m( %vm, ptr noundef %rs1, %rs2, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %rs2.addr = alloca , align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store %rs2, ptr %rs2.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load , ptr %rs2.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5) poison, ptr %1, %2, %0, i64 %3, i64 3, i64 4) # | ret target("riscv.vector.tuple", , 5) %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) # | declare target("riscv.vector.tuple", , 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv4i16.nxv4i1.i64(target("riscv.vector.tuple", , 5), ptr captures(none), , , i64, i64 immarg, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056167b50c15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056167b5090f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056167b50c89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f9222249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f92222a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f9222249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f9222231507 abort ./stdlib/abort.c:85:3 # | #7 0x000056167b4a1e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056167b4a1c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056167b486b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056167b1360b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056167b135dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f9222232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f92222330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f92222330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056167b135cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c (3290 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m1x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_i8m2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read) # | declare target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv16i8_3t.p0.i64(target("riscv.vector.tuple", , 3), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf8x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv1i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf4x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t.p0.i64(target("riscv.vector.tuple", , 3) %0, ptr %1, i64 %2, i64 3) # | ret target("riscv.vector.tuple", , 3) %3 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 3) @test_vlseg3e8_v_u8mf2x3_tu(target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr noundef %base, i64 noundef %vl) #0 { # | entry: # | %maskedoff_tuple.addr = alloca target("riscv.vector.tuple", , 3), align 1 # | %base.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store target("riscv.vector.tuple", , 3) %maskedoff_tuple, ptr %maskedoff_tuple.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load target("riscv.vector.tuple", , 3), ptr %maskedoff_tuple.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(targe # | ... # `---data was truncated (10240/53734) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055c6995fe15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055c6995fb0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055c6995fe89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fe632249b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fe6322a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fe632249a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fe632231507 abort ./stdlib/abort.c:85:3 # | #7 0x000055c699593e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055c699593c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055c699578b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055c6992280b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055c699227dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fe632232fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fe6322330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fe6322330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055c699227cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c (3291 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_f64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8f64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8f64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv1i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv2i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m4(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv4i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv4i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_i64m8(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv8i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) # | declare void @llvm.riscv.vsse.nxv8i64.p0.i64(, ptr captures(none), i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m1(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv1i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_vsse64_v_u64m2(ptr noundef %base, i64 noundef %bstride, %value, i64 noundef %vl) #0 { # | entry: # | %base.addr = alloca ptr, align 8 # | %bstride.addr = alloca i64, align 8 # | %value.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store ptr %base, ptr %base.addr, align 8 # | store i64 %bstride, ptr %bstride.addr, align 8 # | store %value, ptr %value.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %base.addr, align 8 # | %1 = load i64, ptr %bstride.addr, align 8 # | %2 = load , ptr %value.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsse.nxv2i64.p0.i64( %2, ptr %0, i64 %1, i64 %3) # | ret void # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | def # | ... # `---data was truncated (10240/26764) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000560a48f6215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000560a48f5f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000560a48f6289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fb88f849b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fb88f8a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fb88f849a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fb88f831507 abort ./stdlib/abort.c:85:3 # | #7 0x0000560a48ef7e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000560a48ef7c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000560a48edcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000560a48b8c0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000560a48b8bdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fb88f832fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fb88f8330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fb88f8330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000560a48b8bcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c (3292 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfh -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf8_b64_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.nxv1i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf8_b64_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf4_b32_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.nxv2i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf4_b32_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv2i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8mf2_b16_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.nxv4i8.i64(, , , , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vx_u8mf2_b16_mu( %mask, %maskedoff, %op1, i8 noundef zeroext %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca i8, align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store i8 %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load i8, ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64( %1, %2, i8 %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv4i8.i8.i64(, , i8, , i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vmsltu_vv_u8m1_b8_mu( %mask, %maskedoff, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %maskedoff.addr = alloca , align 1 # | %op1.addr = alloca , align 1 # | %op2.addr = alloca , align 1 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %maskedoff, ptr %maskedoff.addr, align 1 # | store %op1, ptr %op1.addr, align 1 # | store %op2, ptr %op2.addr, align 1 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %maskedoff.addr, align 1 # | %2 = load , ptr %op1.addr, align 1 # | %3 = load , ptr %op2.addr, align 1 # | %4 = load i64, ptr %vl.addr, align 8 # | %5 = call @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64( %1, %2, %3, %0, i64 %4) # | ret %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vmsltu.mask.nxv8i8.nxv8i8.i64(, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c (3293 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +zvfhmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv4i8_2t.i64.p0.nxv2i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m1x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv8i8_2t.i64.p0.nxv4i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv16i8_2t.i64.p0.nxv8i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_f16m4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn # | declare { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t.i64.p0.nxv16i1(target("riscv.vector.tuple", , 2), ptr captures(none), , i64, i64 immarg, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf4x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store ptr %base, ptr %base.addr, align 8 # | store ptr %new_vl, ptr %new_vl.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load ptr, ptr %base.addr, align 8 # | %2 = load ptr, ptr %new_vl.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call { target("riscv.vector.tuple", , 2), i64 } @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv2i8_2t.i64.p0.nxv1i1(target("riscv.vector.tuple", , 2) poison, ptr %1, %0, i64 %3, i64 3, i64 4) # | %5 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 0 # | %6 = extractvalue { target("riscv.vector.tuple", , 2), i64 } %4, 1 # | store i64 %6, ptr %2, align 8 # | ret target("riscv.vector.tuple", , 2) %5 # | } # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local target("riscv.vector.tuple", , 2) @test_vlseg2e16ff_v_i16mf2x2_m( %mask, ptr noundef %base, ptr noundef %new_vl, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %base.addr = alloca ptr, align 8 # | %new_vl.addr = alloca ptr, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | # | ... # `---data was truncated (10240/22074) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000055ec67cbf15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000055ec67cbc0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000055ec67cbf89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007fd94b41bb70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007fd94b4725cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007fd94b41ba42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007fd94b403507 abort ./stdlib/abort.c:85:3 # | #7 0x000055ec67c54e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000055ec67c54c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000055ec67c39b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000055ec678e90b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000055ec678e8dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007fd94b404fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007fd94b4050d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007fd94b4050d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000055ec678e8cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c (3294 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +zve64x -target-feature +zvfbfmin -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv2i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7(ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load ptr, ptr %rs1.addr, align 8 # | %1 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %2 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) %1, ptr %0, i64 %2, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7), ptr captures(none), i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv2i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(1,1024) # | define dso_local void @test_vsseg7e16_v_bf16m1x7_m( %vm, ptr noundef %rs1, target("riscv.vector.tuple", , 7) %vs3, i64 noundef %vl) #0 { # | entry: # | %vm.addr = alloca , align 1 # | %rs1.addr = alloca ptr, align 8 # | %vs3.addr = alloca target("riscv.vector.tuple", , 7), align 2 # | %vl.addr = alloca i64, align 8 # | store %vm, ptr %vm.addr, align 1 # | store ptr %rs1, ptr %rs1.addr, align 8 # | store target("riscv.vector.tuple", , 7) %vs3, ptr %vs3.addr, align 2 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vm.addr, align 1 # | %1 = load ptr, ptr %rs1.addr, align 8 # | %2 = load target("riscv.vector.tuple", , 7), ptr %vs3.addr, align 2 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7) %2, ptr %1, %0, i64 %3, i64 4) # | ret void # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) # | declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 7), ptr captures(none), , i64, i64 immarg) #1 # | # | attributes #0 = { noinline nounwind vscale_range(1,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+f,+i,+zicsr,+zve32f,+zve32x,+zve64x,+zvfbfmin,+zvl32b,+zvl64b" } # | attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"lp64f"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64x1p0_zvfbfmin1p0_zvl32b1p0_zvl64b1p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056094f91315b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056094f9100f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056094f91389b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f8496533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f849658a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f8496533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f849651b507 abort ./stdlib/abort.c:85:3 # | #7 0x000056094f8a8e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x000056094f8a8c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x000056094f88db29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x000056094f53d0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x000056094f53cdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f849651cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f849651d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f849651d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x000056094f53ccc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c (3295 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 2 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv32 -target-feature +xandesperf -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c -o - -disable-O0-optnone # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c" # | target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" # | target triple = "riscv32" # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffb(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffb.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffzmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffzmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_ffmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.ffmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: noinline nounwind # | define dso_local i32 @test_flmism(i32 noundef %a, i32 noundef %b) #0 { # | entry: # | %__a.addr.i = alloca i32, align 4 # | %__b.addr.i = alloca i32, align 4 # | %a.addr = alloca i32, align 4 # | %b.addr = alloca i32, align 4 # | store i32 %a, ptr %a.addr, align 4 # | store i32 %b, ptr %b.addr, align 4 # | %0 = load i32, ptr %a.addr, align 4 # | %1 = load i32, ptr %b.addr, align 4 # | store i32 %0, ptr %__a.addr.i, align 4 # | store i32 %1, ptr %__b.addr.i, align 4 # | %2 = load i32, ptr %__a.addr.i, align 4 # | %3 = load i32, ptr %__b.addr.i, align 4 # | %4 = call i32 @llvm.riscv.nds.flmism.i32(i32 %2, i32 %3) # | ret i32 %4 # | } # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffb.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffzmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.ffmism.i32(i32, i32) #1 # | # | ; Function Attrs: nounwind speculatable memory(none) # | declare i32 @llvm.riscv.nds.flmism.i32(i32, i32) #1 # | # | attributes #0 = { noinline nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+i,+xandesperf" } # | attributes #1 = { nounwind speculatable memory(none) } # | # | !llvm.module.flags = !{!0, !1, !3} # | !llvm.ident = !{!4} # | # | !0 = !{i32 1, !"target-abi", !"ilp32"} # | !1 = !{i32 6, !"riscv-isa", !2} # | !2 = !{!"rv32i2p1_xandesperf5p0"} # | !3 = !{i32 8, !"SmallDataLimit", i32 0} # | !4 = !{!"clang version 24.0.0"} # `----------------------------- # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x000056162918215b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x000056162917f0f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x000056162918289b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f1e50449b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f1e504a05cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f1e50449a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f1e50431507 abort ./stdlib/abort.c:85:3 # | #7 0x0000561629117e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000561629117c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x00005616290fcb29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000561628dac0b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000561628dabdd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f1e50432fba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f1e504330d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f1e504330d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000561628dabcc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20 FAIL: Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c (3296 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local void @test_sf_vc_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret void # | } # | # | ; Function Attrs: nounwind # | declare void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m2( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.nxv2i64.nxv2i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m4( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.nxv4i64.nxv4i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_se_u64m8( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind # | declare @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.nxv8i64.nxv8i64.i64.i64(i64 immarg, , , i64, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_sf_vc_v_xvv_u64m1( %vd, %vs2, i64 noundef %rs1, i64 noundef %vl) #0 { # | entry: # | %vd.addr = alloca , align 8 # | %vs2.addr = alloca , align 8 # | %rs1.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %vd, ptr %vd.addr, align 8 # | store %vs2, ptr %vs2.addr, align 8 # | store i64 %rs1, ptr %rs1.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %vd.addr, align 8 # | %1 = load , ptr %vs2.addr, align 8 # | %2 = load i64, ptr %rs1.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 3, %0, %1, i64 %2, i64 %3) # | ret %4 # | } # | # | ; Function Attrs: nounwind memory(none) # | declare @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.nxv1i64.nxv1i64.i64.i64(i64 immarg, , ' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40. FAIL: Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c (3625 of 27911) ******************** TEST 'Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' FAILED ******************** Exit Code: 2 Command Output (stdout): -- # RUN: at line 3 /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg | /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/clang -cc1 -internal-isystem /usr/local/google/home/thakis/src/llvm-project/out/gn/lib/clang/24/include -nostdsysteminc -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c -o - # .---command stdout------------ # | ; ModuleID = '/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c' # | source_filename = "/usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c" # | target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" # | target triple = "riscv64" # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.nxv1i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv1i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv1i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m2( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.nxv2i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m2( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv2i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv2i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m4( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.nxv4i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m4( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv4i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv4i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m8( %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load , ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64( poison, %0, %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.nxv8i64.i64(, , , i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m8( %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %op1.addr, align 8 # | %1 = load i64, ptr %op2.addr, align 8 # | %2 = load i64, ptr %vl.addr, align 8 # | %3 = call @llvm.riscv.vsmul.nxv8i64.i64.i64( poison, %0, i64 %1, i64 0, i64 %2) # | ret %3 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.nxv8i64.i64.i64(, , i64, i64 immarg, i64) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vv_i64m1_m( %mask, %op1, %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca , align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr %op1.addr, align 8 # | %2 = load , ptr %op2.addr, align 8 # | %3 = load i64, ptr %vl.addr, align 8 # | %4 = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64( poison, %1, %2, %0, i64 0, i64 %3, i64 3) # | ret %4 # | } # | # | ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) # | declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64.i64(, , , , i64 immarg, i64, i64 immarg) #1 # | # | ; Function Attrs: noinline nounwind vscale_range(2,1024) # | define dso_local @test_vsmul_vx_i64m1_m( %mask, %op1, i64 noundef %op2, i64 noundef %vl) #0 { # | entry: # | %mask.addr = alloca , align 1 # | %op1.addr = alloca , align 8 # | %op2.addr = alloca i64, align 8 # | %vl.addr = alloca i64, align 8 # | store %mask, ptr %mask.addr, align 1 # | store %op1, ptr %op1.addr, align 8 # | store i64 %op2, ptr %op2.addr, align 8 # | store i64 %vl, ptr %vl.addr, align 8 # | %0 = load , ptr %mask.addr, align 1 # | %1 = load , ptr # | ... # `---data was truncated (10240/18895) (change limit with -D output_limit=N) # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # .---command stderr------------ # | opt: CommandLine Error: Option 'lanai-mem-alu-combiner' registered more than once! # | LLVM ERROR: inconsistency in registered CommandLine options # | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug. # | Stack dump: # | 0. Program arguments: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt -S -passes=mem2reg # | #0 0x0000558ceddab15b llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a2315b) # | #1 0x0000558cedda80f5 llvm::sys::RunSignalHandlers() (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x5a200f5) # | #2 0x0000558ceddab89b SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0 # | #3 0x00007f44b3533b70 (/usr/lib/x86_64-linux-gnu/libc.so.6+0x40b70) # | #4 0x00007f44b358a5cc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 # | #5 0x00007f44b3533a42 raise ./signal/../sysdeps/posix/raise.c:27:6 # | #6 0x00007f44b351b507 abort ./stdlib/abort.c:85:3 # | #7 0x0000558cedd40e2d llvm::report_fatal_error(llvm::Twine const&, bool) (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8e2d) # | #8 0x0000558cedd40c76 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x59b8c76) # | #9 0x0000558cedd25b29 (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x599db29) # | #10 0x0000558ced9d50b6 optMain (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564d0b6) # | #11 0x0000558ced9d4dd3 main (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564cdd3) # | #12 0x00007f44b351cfba __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:83:3 # | #13 0x00007f44b351d0d7 call_init ./csu/../csu/libc-start.c:128:20 # | #14 0x00007f44b351d0d7 __libc_start_main ./csu/../csu/libc-start.c:347:5 # | #15 0x0000558ced9d4cc1 _start (/usr/local/google/home/thakis/src/llvm-project/out/gn/bin/opt+0x564ccc1) # `----------------------------- # error: command failed with exit status: -6 # executed command: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # .---command stderr------------ # | FileCheck error: '' is empty. # | FileCheck command line: /usr/local/google/home/thakis/src/llvm-project/out/gn/bin/FileCheck --check-prefix=CHECK-RV64 /usr/local/google/home/thakis/src/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c # `----------------------------- # error: command failed with exit status: 2 -- ******************** Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. ******************** Failed Tests (3297): Clang :: CodeGen/2005-06-15-ExpandGotoInternalProblem.c Clang :: CodeGen/2005-09-24-AsmUserPrefix.c Clang :: CodeGen/2008-07-17-no-emit-on-error.c Clang :: CodeGen/AArch64/atomic-hint-template.cpp Clang :: CodeGen/AArch64/bf16-dotprod-intrinsics.c Clang :: CodeGen/AArch64/bf16-getset-intrinsics.c Clang :: CodeGen/AArch64/bf16-lane-intrinsics.c Clang :: CodeGen/AArch64/bf16-reinterpret-intrinsics.c Clang :: CodeGen/AArch64/builtin-shufflevector-fp8.c Clang :: CodeGen/AArch64/f16f32dot-intrinsics.c Clang :: CodeGen/AArch64/fp8-cast.c Clang :: CodeGen/AArch64/fp8-extract.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_reinterpret.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_untyped.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_scale.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c Clang :: CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_reinterpret.c Clang :: CodeGen/AArch64/neon-2velem.c Clang :: CodeGen/AArch64/neon-3v.c Clang :: CodeGen/AArch64/neon-dot-product.c Clang :: CodeGen/AArch64/neon-extract.c Clang :: CodeGen/AArch64/neon-fma.c Clang :: CodeGen/AArch64/neon-fp16fml.c Clang :: CodeGen/AArch64/neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/neon-intrinsics.c Clang :: CodeGen/AArch64/neon-ldst-one-rcpc3.c Clang :: CodeGen/AArch64/neon-misc-constrained.c Clang :: CodeGen/AArch64/neon-misc.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem-constrained.c Clang :: CodeGen/AArch64/neon-scalar-x-indexed-elem.c Clang :: CodeGen/AArch64/neon-shifts.c Clang :: CodeGen/AArch64/neon-tbl.c Clang :: CodeGen/AArch64/neon-vcmla.c Clang :: CodeGen/AArch64/neon-vcombine.c Clang :: CodeGen/AArch64/neon-vget-hilo.c Clang :: CodeGen/AArch64/neon-vsqadd-float-conversion.c Clang :: CodeGen/AArch64/neon/add.c Clang :: CodeGen/AArch64/neon/bf16-getset.c Clang :: CodeGen/AArch64/neon/conversion-fullfp16.c Clang :: CodeGen/AArch64/neon/f16-getset.c Clang :: CodeGen/AArch64/neon/fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiple-fullfp16.c Clang :: CodeGen/AArch64/neon/fused-multiply-constrained.c Clang :: CodeGen/AArch64/neon/fused-multiply.c Clang :: CodeGen/AArch64/neon/getset.c Clang :: CodeGen/AArch64/neon/intrinsics-constrained.c Clang :: CodeGen/AArch64/neon/intrinsics.c Clang :: CodeGen/AArch64/neon/load.c Clang :: CodeGen/AArch64/neon/perm.c Clang :: CodeGen/AArch64/neon/rounding-v8.5.c Clang :: CodeGen/AArch64/neon/rounding.c Clang :: CodeGen/AArch64/neon/store.c Clang :: CodeGen/AArch64/neon/subtraction.c Clang :: CodeGen/AArch64/neon/vpaddl.c Clang :: CodeGen/AArch64/neon/widen.c Clang :: CodeGen/AArch64/poly128.c Clang :: CodeGen/AArch64/poly64.c Clang :: CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/aarch64-sme2-attrs.cpp Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfmul.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bfscale.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_bmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_clamp.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_cvtn.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_faminmax.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp8_fvdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_fp_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_frint.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_int_dots.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_ldr_str_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_luti4_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_max.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_maxnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_min.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_minnm.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mla.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlal.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlall.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mls.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mlsl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_1x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x1.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_2x2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_mop4_fp8.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_read.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sqdmulh.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_sub.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_unpkx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vdot.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_add.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_qrshr.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_rshl.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_selx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_uzpx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx2.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_vector_zipx4.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_write_lane_zt.c Clang :: CodeGen/AArch64/sme2-intrinsics/acle_sme2_zero_zt.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_movaz.c Clang :: CodeGen/AArch64/sme2p1-intrinsics/acle_sme2p1_zero.c Clang :: CodeGen/AArch64/sme2p2-intrinsics/acle_sme2p2_fmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_abs.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_acle.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_aclt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_add.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adda.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_adrw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_and.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmlalt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfmmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bfscale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_bic.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brka.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_brkpb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_clz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpeq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpge.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpgt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmple.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmplt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpne.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cmpuo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cnth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_compact.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_create4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt-bfloat.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_cvtnt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_div.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_divr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_dupq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_eor.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_exth.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_extw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_fmmla-f32f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_get4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_index.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lasta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lastb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ro.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1rq.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ld4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldff1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1sw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1ub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnf1uw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ldnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_lsr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp32.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_matmul_fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_max.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_maxnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_min.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_minnm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-bf16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla-f16.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mov.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_msb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_mulx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_neg.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmla.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmls.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_nmsb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_not.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pfirst.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_pnext.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_prfw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptest.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_ptrue.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qadd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdech.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qdecw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincd.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qinch.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qincw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_qsub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rbit.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rdffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_recpx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_reinterpret.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revb.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revh.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_revw.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinta.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rinti.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintm.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintn.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintp.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_rintz.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_scale.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_set4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_setffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_splice.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sqrt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1b.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1h.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st1w.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_st4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_stnt1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sub.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_subr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_sudot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tbl.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tmad.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_trn2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tsmul.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_tssel.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef3.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_undef4.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpkhi.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_unpklo.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_uzp2.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilele.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_whilelt.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_wrffr.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip1.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2-fp64.c Clang :: CodeGen/AArch64/sve-intrinsics/acle_sve_zip2.c Clang :: CodeGen/AArch64/sve-vector-arith-ops.c Clang :: CodeGen/AArch64/sve-vector-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vector-compare-ops.c Clang :: CodeGen/AArch64/sve-vector-shift-ops.c Clang :: CodeGen/AArch64/sve-vector-subscript-ops.c Clang :: CodeGen/AArch64/sve-vls-arith-ops.c Clang :: CodeGen/AArch64/sve-vls-bitwise-ops.c Clang :: CodeGen/AArch64/sve-vls-compare-ops.c Clang :: CodeGen/AArch64/sve-vls-shift-ops.c Clang :: CodeGen/AArch64/sve-vls-subscript-ops.c Clang :: CodeGen/AArch64/sve/addv.c Clang :: CodeGen/AArch64/sve/andv.c Clang :: CodeGen/AArch64/sve/dup.c Clang :: CodeGen/AArch64/sve/eorv.c Clang :: CodeGen/AArch64/sve/len.c Clang :: CodeGen/AArch64/sve/maxnmv.c Clang :: CodeGen/AArch64/sve/maxv.c Clang :: CodeGen/AArch64/sve/minnmv.c Clang :: CodeGen/AArch64/sve/minv.c Clang :: CodeGen/AArch64/sve/nand.c Clang :: CodeGen/AArch64/sve/nor.c Clang :: CodeGen/AArch64/sve/orn.c Clang :: CodeGen/AArch64/sve/orv.c Clang :: CodeGen/AArch64/sve/pfalse.c Clang :: CodeGen/AArch64/sve/recpe.c Clang :: CodeGen/AArch64/sve/recps.c Clang :: CodeGen/AArch64/sve/rsqrte.c Clang :: CodeGen/AArch64/sve/rsqrts.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f16mf8.c Clang :: CodeGen/AArch64/sve2-intrinsics/acle_sve2_fmmla-f32mf8.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul_lane.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dupq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_extq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_ld1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_load_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_loads.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pfalse.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_pred.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_pmov_to_vector.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_st1_single.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_store_struct.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tblq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_tbxq.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uzpq2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq1.c Clang :: CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_zipq2.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_compact.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_expand.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_firstp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve2p2_lastp.c Clang :: CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c Clang :: CodeGen/AArch64/sve2p3-intrinsics/acle_sve2p3_dot.c Clang :: CodeGen/AArch64/v8.1a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-fp16-intrinsics.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-constrained.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/AArch64/v8.2a-neon-intrinsics.c Clang :: CodeGen/AArch64/v8.5a-scalar-frint3264-intrinsic.c Clang :: CodeGen/AArch64/v8.6a-neon-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f16-intrinsics.c Clang :: CodeGen/AArch64/v9.6a-neon-f32-intrinsics.c Clang :: CodeGen/AArch64/v9.7a-neon-mmla-intrinsics.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dots.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotsu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vd4dotu.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfncvtbf16s.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadb.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfpmadt.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vfwcvtsbf16.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c Clang :: CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c Clang :: CodeGen/RISCV/builtin-cpu-is.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt-c-api.c Clang :: CodeGen/RISCV/riscv-xandesbfhcvt.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-c-api-rv64.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv32.c Clang :: CodeGen/RISCV/riscv-xandesperf-rv64.c Clang :: CodeGen/RISCV/riscv-xcvalu-c-api.c Clang :: CodeGen/RISCV/riscv-xcvalu.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkb.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkc.c Clang :: CodeGen/RISCV/rvb-intrinsics/zbkx.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknd.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zkne.c Clang :: CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksed.c Clang :: CodeGen/RISCV/rvk-intrinsics/zksh.c Clang :: CodeGen/RISCV/rvp-intrinsics.c Clang :: CodeGen/RISCV/rvv-builtin-reduce-ops.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmclr.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfirst.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmorn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxnor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vasubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vdivu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrdiv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsqrt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredosum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwredusum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsbf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmseq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgeu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsgtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsif.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsleu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmslt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsltu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmsof.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnclipu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnot.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vnsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredand.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmaxu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredminu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vredxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vremu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsbc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssra.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssrl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vssubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwaddu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwcvtu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmaccus.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwmulu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsum.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwredsumu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vwsubu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vxor.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf4.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vzext_vf8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/non-policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/non-overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdf.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesdm.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesef.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesem.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf1.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaeskf2.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vaesz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vandn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vbrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vclz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vcpop.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vctz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vghsh.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vgmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrev8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vrol.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vror.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ch.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2cl.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsha2ms.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3c.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm3me.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4k.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vsm4r.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/vector-crypto/policy/overloaded/vwsll.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/non-policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/non-overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabdu.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabda.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvabd/policy/overloaded/vwabdau.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4a_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4asu_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4au_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdot4aus_vx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/non-policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/non-overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfabs.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfclass.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmax.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmerge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmin.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfmv.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rod.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfncvt_rtz.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfneg.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfnmsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrec7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsqrt7.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfrsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnj.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjn.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsgnjx.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1down.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfslide1up.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwadd.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwcvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwmul.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmacc.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwnmsac.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vfwsub.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfeq.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfge.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfgt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfle.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmflt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfa/policy/overloaded/vmfne.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vcreate.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vundefined.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vget.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_ext_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlmul_trunc_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vset.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsoxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vssseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vsuxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vcompress.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vle16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vloxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlse16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg2e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg3e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg4e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg5e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg6e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg7e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlseg8e16ff.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg2e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg3e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg4e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg5e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg6e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg7e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vlsseg8e16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg2ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg3ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg4ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg5ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg6ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg7ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei32.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei64.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vluxseg8ei8.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgather.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vrgatherei16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslidedown.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vslideup.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfmin/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/non-policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/non-overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfbfwma/policy/overloaded/vfwmaccbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/non-overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/non-policy/overloaded/vreinterpret.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvt.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfncvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvfofp8min/policy/overloaded/vfwcvtbf16.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/non-policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/non-overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpaire.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vpairo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipe.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vunzipo.c Clang :: CodeGen/RISCV/rvv-intrinsics-autogenerated/zvzip/policy/overloaded/vzip.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-utils.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vget-vset-ice.cpp Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulh.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhsu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vmulhu.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vset-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64-overloaded.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/vsmul-eew64.c Clang :: CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettk.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettm.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettn.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vsettnt.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtdiscard.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtmv_v_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/sf_vtzero_t.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e4m3_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e4m3.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_e5m2_e5m2.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_f_f.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_s_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_s.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_mm_u_u.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vlte8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vste8.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/sf_vtmv_t_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_16.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_32.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexp_v_bf.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v.c Clang :: CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/sf_vfexpa_v_64.c Clang :: CodeGen/RISCV/rvv-vls-arith-ops.c Clang :: CodeGen/RISCV/rvv-vls-bitwise-ops.c Clang :: CodeGen/RISCV/rvv-vls-compare-ops.c Clang :: CodeGen/RISCV/rvv-vls-shift-ops.c Clang :: CodeGen/RISCV/rvv-vls-subscript-ops.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-x.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv-rv64.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvv.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/non-overloaded/xsfvcp-xvw.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/non-policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/non-overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_x_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfnrclip_xu_f_qf_rm.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vfwmacc_4x4x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmacc_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccsu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccu_4x8x4.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_2x8x2.c Clang :: CodeGen/RISCV/sifive-intrinsics/policy/overloaded/sf_vqmaccus_4x8x4.c Clang :: CodeGen/SystemZ/zvector.c Clang :: CodeGen/WebAssembly/builtins-table-externref.c Clang :: CodeGen/WebAssembly/builtins-table-funcref.c Clang :: CodeGen/X86/avx-cmp-builtins.c Clang :: CodeGen/X86/avx-shuffle-builtins.c Clang :: CodeGen/X86/bfloat16-convert-half.c Clang :: CodeGen/X86/sse.c Clang :: CodeGen/aapcs-bitfield.c Clang :: CodeGen/arm-bf16-convert-intrinsics.c Clang :: CodeGen/arm-bf16-dotprod-intrinsics.c Clang :: CodeGen/arm-bf16-params-returns.c Clang :: CodeGen/arm-bf16-reinterpret-intrinsics.c Clang :: CodeGen/arm-cde-gpr.c Clang :: CodeGen/arm-cde-reinterpret.c Clang :: CodeGen/arm-cde-vec.c Clang :: CodeGen/arm-cde-vfp.c Clang :: CodeGen/arm-crc32.c Clang :: CodeGen/arm-mfp8.c Clang :: CodeGen/arm-mve-intrinsics/absneg.c Clang :: CodeGen/arm-mve-intrinsics/admin.c Clang :: CodeGen/arm-mve-intrinsics/bitwise-imm.c Clang :: CodeGen/arm-mve-intrinsics/compare.c Clang :: CodeGen/arm-mve-intrinsics/cplusplus.cpp Clang :: CodeGen/arm-mve-intrinsics/dup.c Clang :: CodeGen/arm-mve-intrinsics/get-set-lane.c Clang :: CodeGen/arm-mve-intrinsics/idup.c Clang :: CodeGen/arm-mve-intrinsics/load-store.c Clang :: CodeGen/arm-mve-intrinsics/predicates.c Clang :: CodeGen/arm-mve-intrinsics/reinterpret.c Clang :: CodeGen/arm-mve-intrinsics/scalar-shifts.c Clang :: CodeGen/arm-mve-intrinsics/scatter-gather.c Clang :: CodeGen/arm-mve-intrinsics/ternary.c Clang :: CodeGen/arm-mve-intrinsics/vabavq.c Clang :: CodeGen/arm-mve-intrinsics/vabdq.c Clang :: CodeGen/arm-mve-intrinsics/vadc.c Clang :: CodeGen/arm-mve-intrinsics/vaddq.c Clang :: CodeGen/arm-mve-intrinsics/vaddv.c Clang :: CodeGen/arm-mve-intrinsics/vandq.c Clang :: CodeGen/arm-mve-intrinsics/vbicq.c Clang :: CodeGen/arm-mve-intrinsics/vbrsrq.c Clang :: CodeGen/arm-mve-intrinsics/vcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vclz.c Clang :: CodeGen/arm-mve-intrinsics/vcmlaq.c Clang :: CodeGen/arm-mve-intrinsics/vcmulq.c Clang :: CodeGen/arm-mve-intrinsics/vcvt.c Clang :: CodeGen/arm-mve-intrinsics/vcvt_anpm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-imm.c Clang :: CodeGen/arm-mve-intrinsics/vector-shift-var.c Clang :: CodeGen/arm-mve-intrinsics/veorq.c Clang :: CodeGen/arm-mve-intrinsics/vhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhcaddq.c Clang :: CodeGen/arm-mve-intrinsics/vhsubq.c Clang :: CodeGen/arm-mve-intrinsics/vld24.c Clang :: CodeGen/arm-mve-intrinsics/vldr.c Clang :: CodeGen/arm-mve-intrinsics/vmaxaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxnmq.c Clang :: CodeGen/arm-mve-intrinsics/vmaxq.c Clang :: CodeGen/arm-mve-intrinsics/vminaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmaq.c Clang :: CodeGen/arm-mve-intrinsics/vminnmq.c Clang :: CodeGen/arm-mve-intrinsics/vminq.c Clang :: CodeGen/arm-mve-intrinsics/vminvq.c Clang :: CodeGen/arm-mve-intrinsics/vmldav.c Clang :: CodeGen/arm-mve-intrinsics/vmlldav.c Clang :: CodeGen/arm-mve-intrinsics/vmovl.c Clang :: CodeGen/arm-mve-intrinsics/vmovn.c Clang :: CodeGen/arm-mve-intrinsics/vmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vmulq.c Clang :: CodeGen/arm-mve-intrinsics/vornq.c Clang :: CodeGen/arm-mve-intrinsics/vorrq.c Clang :: CodeGen/arm-mve-intrinsics/vqaddq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmlad.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmullbq.c Clang :: CodeGen/arm-mve-intrinsics/vqdmulltq.c Clang :: CodeGen/arm-mve-intrinsics/vqmovn.c Clang :: CodeGen/arm-mve-intrinsics/vqrdmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vqsubq.c Clang :: CodeGen/arm-mve-intrinsics/vrev.c Clang :: CodeGen/arm-mve-intrinsics/vrhaddq.c Clang :: CodeGen/arm-mve-intrinsics/vrmulhq.c Clang :: CodeGen/arm-mve-intrinsics/vrnd.c Clang :: CodeGen/arm-mve-intrinsics/vshlc.c Clang :: CodeGen/arm-mve-intrinsics/vsubq.c Clang :: CodeGen/arm-neon-directed-rounding-constrained.c Clang :: CodeGen/arm-neon-directed-rounding.c Clang :: CodeGen/arm-neon-dot-product.c Clang :: CodeGen/arm-neon-endianness.c Clang :: CodeGen/arm-neon-fma.c Clang :: CodeGen/arm-neon-numeric-maxmin.c Clang :: CodeGen/arm-neon-shifts.c Clang :: CodeGen/arm-neon-vcadd.c Clang :: CodeGen/arm-neon-vcvtX.c Clang :: CodeGen/arm-neon-vget.c Clang :: CodeGen/arm-neon-vld.c Clang :: CodeGen/arm-neon-vst.c Clang :: CodeGen/arm-poly-add.c Clang :: CodeGen/arm-v8.1a-neon-intrinsics.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics-generic.c Clang :: CodeGen/arm-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm-v8.6a-neon-intrinsics.c Clang :: CodeGen/arm-vector_type-params-returns.c Clang :: CodeGen/arm64-crc32.c Clang :: CodeGen/arm64-lanes.c Clang :: CodeGen/arm64_vcopy.c Clang :: CodeGen/arm64_vcreate.c Clang :: CodeGen/arm64_vdupq_n_f64.c Clang :: CodeGen/arm_acle.c Clang :: CodeGen/arm_acle_swp.c Clang :: CodeGen/arm_neon_intrinsics.c Clang :: CodeGen/attr-counted-by-issue200014.c Clang :: CodeGen/builtin-align.c Clang :: CodeGen/builtins-arm-exclusive.c Clang :: CodeGen/builtins-arm.c Clang :: CodeGen/builtins-arm64.c Clang :: CodeGen/builtins-loongarch.c Clang :: CodeGen/builtins-riscv.c Clang :: CodeGen/cx-complex-range-real.c Clang :: CodeGen/cx-complex-range.c Clang :: CodeGen/distributed-thin-lto/backend-skip.ll Clang :: CodeGen/distributed-thin-lto/basic.ll Clang :: CodeGen/distributed-thin-lto/cfi-devirt.ll Clang :: CodeGen/distributed-thin-lto/cfi.ll Clang :: CodeGen/distributed-thin-lto/newpm.ll Clang :: CodeGen/distributed-thin-lto/objc-contract-pass.ll Clang :: CodeGen/distributed-thin-lto/supports-hot-cold-new.ll Clang :: CodeGen/linker-diagnostic.ll Clang :: CodeGen/memcmp-inline-builtin-to-asm.c Clang :: CodeGen/mozilla-ms-inline-asm.c Clang :: CodeGen/packed-structure.c Clang :: CodeGen/thinlto-diagnostic-handler-remarks-with-hotness.ll Clang :: CodeGen/thinlto-funcattr-prop.ll Clang :: CodeGen/thinlto-multi-module.ll Clang :: CodeGen/thinlto-opaque-typed-mix.ll Clang :: CodeGen/thinlto_backend.ll Clang :: CodeGen/thinlto_backend_local_name_conflict.ll Clang :: CodeGen/thinlto_embed_bitcode.ll Clang :: CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu Clang :: CodeGenCXX/aarch64-sve-vector-conditional-op.cpp Clang :: CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp Clang :: CodeGenCXX/attr-musttail.cpp Clang :: CodeGenCXX/ctor-globalopt.cpp Clang :: CodeGenCXX/inline-then-fold-variadics.cpp Clang :: CodeGenCXX/thinlto_public_type_test_distributed.ll Clang :: CodeGenCXX/virtual-base-ctor.cpp Clang :: CodeGenCoroutines/coro-gro4.cpp Clang :: CodeGenCoroutines/pr65054.cpp Clang :: CodeGenHIP/offload-pgo-sections.hip Clang :: CodeGenOpenCL/amdgpu-enqueue-kernel-linking.cl Clang :: Modules/pr93497.cppm Testing Time: 161.38s Total Discovered Tests: 55927 Skipped : 37 (0.07%) Unsupported : 1675 (2.99%) Passed : 50889 (90.99%) Expectedly Failed: 29 (0.05%) Failed : 3297 (5.90%) FAILED: gen/clang/test/run-lit python3 bin/llvm-lit -sv ../../clang/test ninja: build stopped: subcommand failed. Command '['ninja', '-C', 'out/gn', 'check-clang']' returned non-zero exit status 1.